Lines Matching +full:0 +full:x00000700
39 } while (0)
41 #define DEBUGF_BRK(message, args...) do { } while (0)
44 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
45 #define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */
46 #define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */
47 #define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */
48 #define XGMAC_VERSION 0x00000008 /* Version */
50 #define XGMAC_VLAN_INCL 0x00000009
51 #define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */
52 #define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */
53 #define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */
54 #define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */
55 #define XGMAC_DEBUG 0x0000000e /* Debug */
56 #define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */
58 #define XGMAC_HASH(n) ((0x00000300/4) + (n))
61 #define XGMAC_OPMODE (0x00000400/4)
63 #define XGMAC_REMOTE_WAKE (0x00000700/4)
65 #define XGMAC_PMT (0x00000704/4)
67 #define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2))
68 #define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2))
70 #define DMA_BUS_MODE 0x000003c0 /* Bus Mode */
71 #define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */
72 #define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */
73 #define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */
74 #define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */
75 #define DMA_STATUS 0x000003c5 /* Status Register */
76 #define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */
77 #define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */
78 #define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */
80 #define DMA_RI_WATCHDOG_TIMER 0x000003c9
81 #define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */
82 #define DMA_AXI_STATUS 0x000003cb /* AXI Status */
83 #define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */
84 #define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */
85 #define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */
86 #define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */
87 #define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */
90 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
91 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
92 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
93 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
94 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
95 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
97 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
99 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
100 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
101 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
102 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
103 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
104 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
105 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
106 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
107 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
108 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
109 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
110 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
111 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
112 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
113 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
116 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
117 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
118 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
130 #define R_MAX 0x400
177 VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
195 if (!rx && (d->ctl_stat & 0x00200000)) { in xgmac_write_desc()
197 } else if (rx && (d->buffer1_size & 0x8000)) { in xgmac_write_desc()
214 frame_size = 0; in xgmac_enet_send()
216 xgmac_read_desc(s, &bd, 0); in xgmac_enet_send()
217 if ((bd.ctl_stat & 0x80000000) == 0) { in xgmac_enet_send()
221 len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff); in xgmac_enet_send()
230 if ((bd.buffer1_size & 0xfff) > 2048) { in xgmac_enet_send()
232 "xgmac buffer 1 len on send > 2048 (0x%x)\n", in xgmac_enet_send()
233 __func__, bd.buffer1_size & 0xfff); in xgmac_enet_send()
236 if ((bd.buffer2_size & 0xfff) != 0) { in xgmac_enet_send()
238 "xgmac buffer 2 len on send != 0 (0x%x)\n", in xgmac_enet_send()
239 __func__, bd.buffer2_size & 0xfff); in xgmac_enet_send()
253 if (bd.ctl_stat & 0x20000000) { in xgmac_enet_send()
257 frame_size = 0; in xgmac_enet_send()
260 bd.ctl_stat &= ~0x80000000; in xgmac_enet_send()
262 xgmac_write_desc(s, &bd, 0); in xgmac_enet_send()
275 uint64_t r = 0; in enet_read()
280 r = 0x1012; in enet_read()
299 s->regs[DMA_BUS_MODE] = value & ~0x1; in enet_write()
337 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, in eth_rx()
338 0xff, 0xff, 0xff}; in eth_rx()
346 unicast = ~buf[0] & 0x1; in eth_rx()
347 broadcast = memcmp(buf, sa_bcast, 6) == 0; in eth_rx()
356 if ((bd.ctl_stat & 0x80000000) == 0) { in eth_rx()
366 bd.ctl_stat = (size << 16) | 0x300; in eth_rx()
397 "xgmac", 0x1000); in xgmac_enet_realize()
409 s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) | in xgmac_enet_realize()
411 s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) | in xgmac_enet_realize()
414 s->conf.macaddr.a[0]; in xgmac_enet_realize()