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/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c47 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
48 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
49 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
50 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
51 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
54 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
55 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
56 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
Dcik.c129 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
140 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
169 0xc200, 0xe0ffffff, 0xe0000000
174 0x31dc, 0xffffffff, 0x00000800,
175 0x31dd, 0xffffffff, 0x00000800,
176 0x31e6, 0xffffffff, 0x00007fbf,
177 0x31e7, 0xffffffff, 0x00007faf
182 0xcd5, 0x00000333, 0x00000333,
183 0xcd4, 0x000c0fc0, 0x00040200,
184 0x2684, 0x00010000, 0x00058208,
[all …]
Dsi.c59 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
60 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
61 mmDB_DEBUG, 0xffffffff, 0x00000000,
62 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
63 mmDB_DEBUG3, 0x0002021c, 0x00020200,
64 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
65 0x340c, 0x000000c0, 0x00800040,
66 0x360c, 0x000000c0, 0x00800040,
67 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
68 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
Dsdma_v3_0.c82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
[all …]
Dgfx_v8_0.c62 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
63 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
65 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
77 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
78 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
79 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
80 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
82 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
[all …]
/linux-5.10/drivers/gpu/drm/sti/
Dsti_hqvdp_lut.h24 0x0000ffff, 0x00010000, 0x000100ff, 0x00000000,
25 0x00000000, 0x00050000, 0xfffc00ff, 0x00000000,
26 0x00000000, 0x00090000, 0xfff900fe, 0x00000000,
27 0x00000000, 0x0010ffff, 0xfff600fb, 0x00000000,
28 0x00000000, 0x0017fffe, 0xfff400f7, 0x00000000,
29 0x00000000, 0x001ffffd, 0xfff200f2, 0x00000000,
30 0x00000000, 0x0027fffc, 0xfff100ec, 0x00000000,
31 0x00000000, 0x0030fffb, 0xfff000e5, 0x00000000,
32 0x00000000, 0x003afffa, 0xffee00de, 0x00000000,
33 0x00000000, 0x0044fff9, 0xffed00d6, 0x00000000,
[all …]
/linux-5.10/drivers/gpu/drm/radeon/
Dbtc_dpm.c36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
41 #define MC_CG_SEQ_DRAMCONF_S0 0x05
42 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
44 #define MC_CG_SEQ_YCLK_RESUME 0x0a
46 #define SMC_RAM_END 0x8000
61 0x000008f8, 0x00000010, 0xffffffff,
[all …]
Devergreen.c42 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
43 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
44 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
55 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
66 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
77 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
88 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
99 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
110 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
129 0x98fc,
[all …]
Dsi.c166 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
167 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
168 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
172 (0x8000 << 16) | (0x98f4 >> 2),
173 0x00000000,
174 (0x8040 << 16) | (0x98f4 >> 2),
175 0x00000000,
176 (0x8000 << 16) | (0xe80 >> 2),
177 0x00000000,
178 (0x8040 << 16) | (0xe80 >> 2),
[all …]
Dtrinity_dpm.c44 0x0000802c, 0xc0000000, 0xffffffff,
45 0x00003fc4, 0xc0000000, 0xffffffff,
46 0x00005448, 0x00000100, 0xffffffff,
47 0x000055e4, 0x00000100, 0xffffffff,
48 0x0000160c, 0x00000100, 0xffffffff,
49 0x00008984, 0x06000100, 0xffffffff,
50 0x0000c164, 0x00000100, 0xffffffff,
51 0x00008a18, 0x00000100, 0xffffffff,
52 0x0000897c, 0x06000100, 0xffffffff,
53 0x00008b28, 0x00000100, 0xffffffff,
[all …]
Dcik.c159 * Returns 0 for success or -EINVAL for an invalid register
179 return 0; in cik_get_allowed_info_register()
214 int actual_temp = 0; in ci_get_temp()
219 if (temp & 0x200) in ci_get_temp()
222 actual_temp = temp & 0x1ff; in ci_get_temp()
231 int actual_temp = 0; in kv_get_temp()
233 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
238 actual_temp = 0; in kv_get_temp()
273 (0x0e00 << 16) | (0xc12c >> 2),
274 0x00000000,
[all …]
/linux-5.10/drivers/net/ethernet/renesas/
Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/linux-5.10/drivers/gpu/drm/etnaviv/
Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux-5.10/drivers/net/ethernet/smsc/
Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_4_1_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
Dmmhub_1_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
/linux-5.10/arch/mips/include/asm/txx9/
Dtx4927pcic.h87 #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
88 #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
89 #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
92 #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
95 #define TX4927_PCIC_PBACFG_FIXPA 0x00000008
96 #define TX4927_PCIC_PBACFG_RPBA 0x00000004
97 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002
98 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001
101 #define TX4927_PCIC_PBASTATUS_ALL 0x00000001
102 #define TX4927_PCIC_PBASTATUS_BM 0x00000001
[all …]
/linux-5.10/arch/openrisc/include/asm/
Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux-5.10/drivers/net/usb/
Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
/linux-5.10/arch/sparc/include/uapi/asm/
Dtermbits.h64 #define VINTR 0
93 #define IGNBRK 0x00000001
94 #define BRKINT 0x00000002
95 #define IGNPAR 0x00000004
96 #define PARMRK 0x00000008
97 #define INPCK 0x00000010
98 #define ISTRIP 0x00000020
99 #define INLCR 0x00000040
100 #define IGNCR 0x00000080
101 #define ICRNL 0x00000100
[all …]
/linux-5.10/include/uapi/linux/
Dfanotify.h8 #define FAN_ACCESS 0x00000001 /* File was accessed */
9 #define FAN_MODIFY 0x00000002 /* File was modified */
10 #define FAN_ATTRIB 0x00000004 /* Metadata changed */
11 #define FAN_CLOSE_WRITE 0x00000008 /* Writtable file closed */
12 #define FAN_CLOSE_NOWRITE 0x00000010 /* Unwrittable file closed */
13 #define FAN_OPEN 0x00000020 /* File was opened */
14 #define FAN_MOVED_FROM 0x00000040 /* File was moved from X */
15 #define FAN_MOVED_TO 0x00000080 /* File was moved to Y */
16 #define FAN_CREATE 0x00000100 /* Subfile was created */
17 #define FAN_DELETE 0x00000200 /* Subfile was deleted */
[all …]
/linux-5.10/drivers/scsi/aic94xx/
Daic94xx_reg_def.h22 #define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
23 #define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
24 #define LmSEQ_HOST_REG_SIZE 0x4000 /* LmSEQ Host Register size */
32 * CHIM Registers, Address Range : (0x00-0xFF)
34 #define COMBIST (REG_BASE_ADDR + 0x00)
37 #define L7BLKRST 0x80000000
38 #define L6BLKRST 0x40000000
39 #define L5BLKRST 0x20000000
40 #define L4BLKRST 0x10000000
41 #define L3BLKRST 0x08000000
[all …]
/linux-5.10/arch/mips/include/asm/mips-boards/
Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]

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