Lines Matching +full:0 +full:x00000100
62 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
63 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
65 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
77 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
78 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
79 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
80 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
82 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
86 #define CLE_BPM_SERDES_CMD 0
90 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
198 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
199 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
200 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
201 mmGB_GPU_ID, 0x0000000f, 0x00000000,
202 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
203 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
204 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
205 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
206 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
207 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
208 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
209 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
210 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
211 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
212 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
213 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
218 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
219 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
220 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
221 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
222 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
223 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
225 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
230 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
231 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
232 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
233 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
237 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
238 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
239 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
240 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
241 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
242 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
252 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
253 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
255 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
256 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
257 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
258 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
260 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
261 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
262 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
263 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
264 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
265 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
266 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
267 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
268 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
269 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
270 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
271 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
272 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
273 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
274 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
275 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
276 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
277 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
278 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
279 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
280 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
281 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
282 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
283 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
284 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
285 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
286 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
287 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
288 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
289 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
290 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
291 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
292 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
293 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
294 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
295 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
296 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
297 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
298 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
299 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
300 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
301 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
302 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
303 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
304 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
309 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
310 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
311 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
312 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
313 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
314 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
315 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
316 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
317 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
318 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
319 mmSQ_CONFIG, 0x07f80000, 0x01180000,
320 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
321 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
322 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
323 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
324 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
325 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
330 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
331 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
332 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
333 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
335 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
340 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
341 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
342 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
343 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
344 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
345 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
346 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
347 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
348 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
349 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
350 mmSQ_CONFIG, 0x07f80000, 0x01180000,
351 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
352 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
353 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
354 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
355 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
356 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
361 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
362 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
363 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
364 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
366 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
371 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
372 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
373 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
374 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
375 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
376 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
377 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
378 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
379 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
380 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
381 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
382 mmSQ_CONFIG, 0x07f80000, 0x07180000,
383 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
384 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
385 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
386 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
387 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
392 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
393 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
394 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
395 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
396 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
397 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
399 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
404 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
405 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
406 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
407 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
408 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
409 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
411 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
412 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
413 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
418 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
419 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
420 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
421 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
422 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
423 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
424 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
425 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
426 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
427 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
428 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
433 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
434 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
435 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
436 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
440 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
442 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
444 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
445 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
455 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
456 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
458 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
459 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
460 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
461 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
463 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
464 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
465 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
466 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
467 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
472 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
473 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
474 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
475 mmGB_GPU_ID, 0x0000000f, 0x00000000,
476 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
477 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
478 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
479 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
480 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
481 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
482 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
483 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
484 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
485 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
486 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
487 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
492 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
493 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
494 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
495 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
496 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
497 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
499 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
504 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
505 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
506 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
507 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
509 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
512 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
513 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
514 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
515 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
516 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
526 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
527 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
528 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
529 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
530 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
531 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
532 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
534 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
535 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
536 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
537 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
538 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
539 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
540 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
541 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
542 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
543 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
544 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
545 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
546 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
547 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
548 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
549 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
550 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
551 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
552 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
553 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
554 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
555 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
556 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
557 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
558 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
559 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
560 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
561 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
562 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
563 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
564 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
565 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
566 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
567 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
572 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
573 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
574 mmGB_GPU_ID, 0x0000000f, 0x00000000,
575 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
576 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
577 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
578 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
579 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
580 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
581 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
582 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
583 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
588 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
589 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
590 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
591 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
592 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
593 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
595 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
600 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
601 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
602 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
603 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
609 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
610 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
611 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
612 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
622 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
623 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
625 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
626 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
627 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
628 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
630 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
631 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
632 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
633 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
634 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
635 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
636 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
637 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
638 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
639 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
640 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
641 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
642 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
643 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
644 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
645 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
646 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
647 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
648 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
649 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
650 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
651 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
652 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
653 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
654 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
655 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
656 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
657 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
658 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
659 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
660 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
661 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
662 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
663 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
664 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
665 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
666 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
667 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
668 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
669 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
670 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
671 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
672 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
673 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
674 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
679 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
680 mmGB_GPU_ID, 0x0000000f, 0x00000000,
681 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
682 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
683 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
684 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
685 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
686 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
687 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
688 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
693 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
694 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
695 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
696 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
697 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
698 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
700 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
705 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
706 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
707 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
708 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
793 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); in gfx_v8_0_init_golden_registers()
794 if (adev->pdev->revision == 0xc7 && in gfx_v8_0_init_golden_registers()
795 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || in gfx_v8_0_init_golden_registers()
796 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || in gfx_v8_0_init_golden_registers()
797 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) { in gfx_v8_0_init_golden_registers()
798 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); in gfx_v8_0_init_golden_registers()
799 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); in gfx_v8_0_init_golden_registers()
840 uint32_t tmp = 0; in gfx_v8_0_ring_test_ring()
848 WREG32(scratch, 0xCAFEDEAD); in gfx_v8_0_ring_test_ring()
855 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
858 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_ring_test_ring()
860 if (tmp == 0xDEADBEEF) in gfx_v8_0_ring_test_ring()
889 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); in gfx_v8_0_ring_test_ib()
890 memset(&ib, 0, sizeof(ib)); in gfx_v8_0_ring_test_ib()
896 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
900 ib.ptr[4] = 0xDEADBEEF; in gfx_v8_0_ring_test_ib()
908 if (r == 0) { in gfx_v8_0_ring_test_ib()
911 } else if (r < 0) { in gfx_v8_0_ring_test_ib()
916 if (tmp == 0xDEADBEEF) in gfx_v8_0_ring_test_ib()
917 r = 0; in gfx_v8_0_ring_test_ib()
1106 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1113 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1160 err = 0; in gfx_v8_0_init_microcode()
1246 u32 count = 0, i; in gfx_v8_0_get_csb_buffer()
1255 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1259 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v8_0_get_csb_buffer()
1260 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v8_0_get_csb_buffer()
1269 for (i = 0; i < ext->reg_count; i++) in gfx_v8_0_get_csb_buffer()
1280 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1281 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1283 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1287 buffer[count++] = cpu_to_le32(0); in gfx_v8_0_get_csb_buffer()
1322 /* init spm vmid with 0xf */ in gfx_v8_0_rlc_init()
1324 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v8_0_rlc_init()
1326 return 0; in gfx_v8_0_rlc_init()
1357 memset(hpd, 0, mec_hpd_size); in gfx_v8_0_mec_init()
1363 return 0; in gfx_v8_0_mec_init()
1368 0x7e000209, 0x7e020208,
1369 0x7e040207, 0x7e060206,
1370 0x7e080205, 0x7e0a0204,
1371 0x7e0c0203, 0x7e0e0202,
1372 0x7e100201, 0x7e120200,
1373 0x7e140209, 0x7e160208,
1374 0x7e180207, 0x7e1a0206,
1375 0x7e1c0205, 0x7e1e0204,
1376 0x7e200203, 0x7e220202,
1377 0x7e240201, 0x7e260200,
1378 0x7e280209, 0x7e2a0208,
1379 0x7e2c0207, 0x7e2e0206,
1380 0x7e300205, 0x7e320204,
1381 0x7e340203, 0x7e360202,
1382 0x7e380201, 0x7e3a0200,
1383 0x7e3c0209, 0x7e3e0208,
1384 0x7e400207, 0x7e420206,
1385 0x7e440205, 0x7e460204,
1386 0x7e480203, 0x7e4a0202,
1387 0x7e4c0201, 0x7e4e0200,
1388 0x7e500209, 0x7e520208,
1389 0x7e540207, 0x7e560206,
1390 0x7e580205, 0x7e5a0204,
1391 0x7e5c0203, 0x7e5e0202,
1392 0x7e600201, 0x7e620200,
1393 0x7e640209, 0x7e660208,
1394 0x7e680207, 0x7e6a0206,
1395 0x7e6c0205, 0x7e6e0204,
1396 0x7e700203, 0x7e720202,
1397 0x7e740201, 0x7e760200,
1398 0x7e780209, 0x7e7a0208,
1399 0x7e7c0207, 0x7e7e0206,
1400 0xbf8a0000, 0xbf810000,
1405 0xbe8a0100, 0xbe8c0102,
1406 0xbe8e0104, 0xbe900106,
1407 0xbe920108, 0xbe940100,
1408 0xbe960102, 0xbe980104,
1409 0xbe9a0106, 0xbe9c0108,
1410 0xbe9e0100, 0xbea00102,
1411 0xbea20104, 0xbea40106,
1412 0xbea60108, 0xbea80100,
1413 0xbeaa0102, 0xbeac0104,
1414 0xbeae0106, 0xbeb00108,
1415 0xbeb20100, 0xbeb40102,
1416 0xbeb60104, 0xbeb80106,
1417 0xbeba0108, 0xbebc0100,
1418 0xbebe0102, 0xbec00104,
1419 0xbec20106, 0xbec40108,
1420 0xbec60100, 0xbec80102,
1421 0xbee60004, 0xbee70005,
1422 0xbeea0006, 0xbeeb0007,
1423 0xbee80008, 0xbee90009,
1424 0xbefc0000, 0xbf8a0000,
1425 0xbf810000, 0x00000000,
1430 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1431 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1435 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1437 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1438 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1439 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1440 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1441 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1442 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1443 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1444 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1445 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1446 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1451 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1452 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1456 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1458 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1459 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1460 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1461 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1462 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1463 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1464 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1465 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1466 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1467 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1472 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1473 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1477 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1479 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1480 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1481 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1482 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1483 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1484 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1485 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1486 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1487 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1488 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1522 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1532 return 0; in gfx_v8_0_do_edc_gpr_workarounds()
1536 return 0; in gfx_v8_0_do_edc_gpr_workarounds()
1539 WREG32(mmGB_EDC_MODE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1554 memset(&ib, 0, sizeof(ib)); in gfx_v8_0_do_edc_gpr_workarounds()
1563 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1566 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1569 /* init the ib length to 0 */ in gfx_v8_0_do_edc_gpr_workarounds()
1570 ib.length_dw = 0; in gfx_v8_0_do_edc_gpr_workarounds()
1574 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1592 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1595 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1600 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1618 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1621 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1626 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { in gfx_v8_0_do_edc_gpr_workarounds()
1644 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1647 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); in gfx_v8_0_do_edc_gpr_workarounds()
1669 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; in gfx_v8_0_do_edc_gpr_workarounds()
1674 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) in gfx_v8_0_do_edc_gpr_workarounds()
1704 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1705 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1706 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1707 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1721 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1722 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1723 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1724 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1736 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1737 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1738 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1751 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1752 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1753 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1754 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1768 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1769 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1771 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1785 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1786 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1802 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1805 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1819 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1820 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1821 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1822 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1848 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map… in gfx_v8_0_gpu_early_init()
1849 dimm00_addr_map = 0; in gfx_v8_0_gpu_early_init()
1850 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map… in gfx_v8_0_gpu_early_init()
1851 dimm01_addr_map = 0; in gfx_v8_0_gpu_early_init()
1852 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map… in gfx_v8_0_gpu_early_init()
1853 dimm10_addr_map = 0; in gfx_v8_0_gpu_early_init()
1854 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map… in gfx_v8_0_gpu_early_init()
1855 dimm11_addr_map = 0; in gfx_v8_0_gpu_early_init()
1878 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
1889 return 0; in gfx_v8_0_gpu_early_init()
1927 return 0; in gfx_v8_0_compute_ring_init()
2015 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2034 ring_id = 0; in gfx_v8_0_sw_init()
2035 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2036 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2037 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2068 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2074 return 0; in gfx_v8_0_sw_init()
2082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2084 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2104 return 0; in gfx_v8_0_sw_fini()
2117 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2118 modearray[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2120 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2121 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2125 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2228 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2285 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2290 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2297 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2420 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2477 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2480 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2486 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2609 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2666 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2669 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2676 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2799 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2869 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2872 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2878 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3001 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3071 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3074 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3080 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3183 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3240 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3245 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3257 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3360 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3422 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
3435 if (instance == 0xffffffff) in gfx_v8_0_select_se_sh()
3436 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3438 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3440 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3445 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3497 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3503 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3506 *rconf |= 0x0; in gfx_v8_0_raster_config()
3507 *rconf1 |= 0x0; in gfx_v8_0_raster_config()
3510 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v8_0_raster_config()
3527 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3528 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3536 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3540 if (!se_mask[0] && !se_mask[1]) { in gfx_v8_0_write_harvested_raster_configs()
3549 for (se = 0; se < num_se; se++) { in gfx_v8_0_write_harvested_raster_configs()
3615 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); in gfx_v8_0_write_harvested_raster_configs()
3621 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_write_harvested_raster_configs()
3628 u32 raster_config = 0, raster_config_1 = 0; in gfx_v8_0_setup_rb()
3629 u32 active_rbs = 0; in gfx_v8_0_setup_rb()
3635 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3636 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3637 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v8_0_setup_rb()
3643 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_setup_rb()
3664 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3665 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3666 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v8_0_setup_rb()
3677 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_setup_rb()
3689 #define DEFAULT_SH_MEM_BASES (0x6000)
3698 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v8_0_init_compute_vmid()
3699 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v8_0_init_compute_vmid()
3700 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v8_0_init_compute_vmid()
3713 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_init_compute_vmid()
3717 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v8_0_init_compute_vmid()
3720 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_init_compute_vmid()
3726 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); in gfx_v8_0_init_compute_vmid()
3727 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); in gfx_v8_0_init_compute_vmid()
3728 WREG32(amdgpu_gds_reg_offset[i].gws, 0); in gfx_v8_0_init_compute_vmid()
3729 WREG32(amdgpu_gds_reg_offset[i].oa, 0); in gfx_v8_0_init_compute_vmid()
3744 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); in gfx_v8_0_init_gds_vmid()
3745 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); in gfx_v8_0_init_gds_vmid()
3746 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); in gfx_v8_0_init_gds_vmid()
3747 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); in gfx_v8_0_init_gds_vmid()
3759 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3769 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_constants_init()
3781 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, in gfx_v8_0_constants_init()
3790 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { in gfx_v8_0_constants_init()
3791 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_constants_init()
3793 if (i == 0) { in gfx_v8_0_constants_init()
3794 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); in gfx_v8_0_constants_init()
3799 WREG32(mmSH_MEM_BASES, 0); in gfx_v8_0_constants_init()
3801 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); in gfx_v8_0_constants_init()
3811 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v8_0_constants_init()
3813 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_constants_init()
3824 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_constants_init()
3853 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3854 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3855 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v8_0_wait_for_rlc_serdes()
3856 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
3857 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v8_0_wait_for_rlc_serdes()
3862 gfx_v8_0_select_se_sh(adev, 0xffffffff, in gfx_v8_0_wait_for_rlc_serdes()
3863 0xffffffff, 0xffffffff); in gfx_v8_0_wait_for_rlc_serdes()
3871 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_wait_for_rlc_serdes()
3878 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
3879 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v8_0_wait_for_rlc_serdes()
3890 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3905 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3932 if (register_list_format[ind_offset] == 0xFFFFFFFF) { in gfx_v8_0_parse_ind_reg_list()
3940 for (indices = 0; in gfx_v8_0_parse_ind_reg_list()
3963 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; in gfx_v8_0_init_save_restore_list()
3964 int indices_count = 0; in gfx_v8_0_init_save_restore_list()
3965 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; in gfx_v8_0_init_save_restore_list()
3966 int offset_count = 0; in gfx_v8_0_init_save_restore_list()
3988 WREG32(mmRLC_SRM_ARAM_ADDR, 0); in gfx_v8_0_init_save_restore_list()
3989 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3994 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
4005 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) in gfx_v8_0_init_save_restore_list()
4012 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) { in gfx_v8_0_init_save_restore_list()
4013 if (unique_indices[i] != 0) { in gfx_v8_0_init_save_restore_list()
4014 WREG32(temp + i, unique_indices[i] & 0x3FFFF); in gfx_v8_0_init_save_restore_list()
4020 return 0; in gfx_v8_0_init_save_restore_list()
4032 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); in gfx_v8_0_init_power_gating()
4034 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4035 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4036 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4037 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); in gfx_v8_0_init_power_gating()
4040 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); in gfx_v8_0_init_power_gating()
4041 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); in gfx_v8_0_init_power_gating()
4048 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4054 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4059 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
4085 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4096 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v8_0_rlc_reset()
4115 return 0; in gfx_v8_0_rlc_resume()
4123 return 0; in gfx_v8_0_rlc_resume()
4131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4133 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4145 u32 count = 0; in gfx_v8_0_get_csb_size()
4159 return 0; in gfx_v8_0_get_csb_size()
4174 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4181 WREG32(mmCP_ENDIAN_SWAP, 0); in gfx_v8_0_cp_gfx_start()
4193 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4197 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4198 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4208 for (i = 0; i < ext->reg_count; i++) in gfx_v8_0_cp_gfx_start()
4216 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4217 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4219 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4222 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
4223 amdgpu_ring_write(ring, 0); in gfx_v8_0_cp_gfx_start()
4228 amdgpu_ring_write(ring, 0x8000); in gfx_v8_0_cp_gfx_start()
4229 amdgpu_ring_write(ring, 0x8000); in gfx_v8_0_cp_gfx_start()
4233 return 0; in gfx_v8_0_cp_gfx_start()
4248 DOORBELL_HIT, 0); in gfx_v8_0_set_cpg_door_bell()
4252 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); in gfx_v8_0_set_cpg_door_bell()
4260 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, in gfx_v8_0_set_cpg_door_bell()
4277 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v8_0_cp_gfx_resume()
4279 /* set the RB to use vmid 0 */ in gfx_v8_0_cp_gfx_resume()
4280 WREG32(mmCP_RB_VMID, 0); in gfx_v8_0_cp_gfx_resume()
4283 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4285 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4296 ring->wptr = 0; in gfx_v8_0_cp_gfx_resume()
4302 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v8_0_cp_gfx_resume()
4320 return 0; in gfx_v8_0_cp_gfx_resume()
4326 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable()
4342 tmp &= 0xffffff00; in gfx_v8_0_kiq_setting()
4345 tmp |= 0x80; in gfx_v8_0_kiq_setting()
4352 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable()
4355 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { in gfx_v8_0_kiq_kcq_enable()
4377 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx_v8_0_kiq_kcq_enable()
4380 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v8_0_kiq_kcq_enable()
4381 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v8_0_kiq_kcq_enable()
4382 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v8_0_kiq_kcq_enable()
4383 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v8_0_kiq_kcq_enable()
4384 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4391 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ in gfx_v8_0_kiq_kcq_enable()
4398 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */ in gfx_v8_0_kiq_kcq_enable()
4407 return 0; in gfx_v8_0_kiq_kcq_enable()
4412 int i, r = 0; in gfx_v8_0_deactivate_hqd()
4416 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_deactivate_hqd()
4424 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
4425 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v8_0_deactivate_hqd()
4426 WREG32(mmCP_HQD_PQ_WPTR, 0); in gfx_v8_0_deactivate_hqd()
4451 mqd->header = 0xC0310800; in gfx_v8_0_mqd_init()
4452 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v8_0_mqd_init()
4453 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v8_0_mqd_init()
4454 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v8_0_mqd_init()
4455 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v8_0_mqd_init()
4456 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v8_0_mqd_init()
4457 mqd->compute_misc_reserved = 0x00000003; in gfx_v8_0_mqd_init()
4477 ring->use_doorbell ? 1 : 0); in gfx_v8_0_mqd_init()
4482 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4485 /* set MQD vmid to 0 */ in gfx_v8_0_mqd_init()
4487 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v8_0_mqd_init()
4504 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_mqd_init()
4505 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_mqd_init()
4512 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4514 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4518 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v8_0_mqd_init()
4519 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4521 tmp = 0; in gfx_v8_0_mqd_init()
4531 DOORBELL_SOURCE, 0); in gfx_v8_0_mqd_init()
4533 DOORBELL_HIT, 0); in gfx_v8_0_mqd_init()
4539 ring->wptr = 0; in gfx_v8_0_mqd_init()
4544 mqd->cp_hqd_vmid = 0; in gfx_v8_0_mqd_init()
4547 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); in gfx_v8_0_mqd_init()
4588 return 0; in gfx_v8_0_mqd_init()
4601 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v8_0_mqd_commit()
4625 return 0; in gfx_v8_0_mqd_commit()
4642 ring->wptr = 0; in gfx_v8_0_kiq_init_queue()
4645 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kiq_init_queue()
4647 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kiq_init_queue()
4650 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4651 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v8_0_kiq_init_queue()
4652 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v8_0_kiq_init_queue()
4654 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kiq_init_queue()
4657 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kiq_init_queue()
4664 return 0; in gfx_v8_0_kiq_init_queue()
4671 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4674 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4675 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v8_0_kcq_init_queue()
4676 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v8_0_kcq_init_queue()
4678 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_kcq_init_queue()
4680 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_kcq_init_queue()
4690 ring->wptr = 0; in gfx_v8_0_kcq_init_queue()
4695 return 0; in gfx_v8_0_kcq_init_queue()
4716 if (unlikely(r != 0)) in gfx_v8_0_kiq_resume()
4720 if (unlikely(r != 0)) in gfx_v8_0_kiq_resume()
4728 return 0; in gfx_v8_0_kiq_resume()
4734 int r = 0, i; in gfx_v8_0_kcq_resume()
4738 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4742 if (unlikely(r != 0)) in gfx_v8_0_kcq_resume()
4771 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4781 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4786 return 0; in gfx_v8_0_cp_test_all_rings()
4814 return 0; in gfx_v8_0_cp_resume()
4849 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4853 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v8_0_kcq_disable()
4855 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | in gfx_v8_0_kcq_disable()
4856 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | in gfx_v8_0_kcq_disable()
4859 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4860 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4861 amdgpu_ring_write(kiq_ring, 0); in gfx_v8_0_kcq_disable()
4875 || RREG32(mmGRBM_STATUS2) != 0x8) in gfx_v8_0_is_idle()
4885 if (RREG32(mmGRBM_STATUS2) != 0x8) in gfx_v8_0_rlc_is_idle()
4896 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_wait_for_rlc_idle()
4898 return 0; in gfx_v8_0_wait_for_rlc_idle()
4910 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_wait_for_idle()
4912 return 0; in gfx_v8_0_wait_for_idle()
4923 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4924 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4926 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4928 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4935 return 0; in gfx_v8_0_hw_fini()
4948 return 0; in gfx_v8_0_hw_fini()
4964 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5017 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5018 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5026 u32 grbm_soft_reset = 0; in gfx_v8_0_pre_soft_reset()
5030 return 0; in gfx_v8_0_pre_soft_reset()
5048 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5052 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_pre_soft_reset()
5054 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_pre_soft_reset()
5061 return 0; in gfx_v8_0_pre_soft_reset()
5067 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v8_0_soft_reset()
5072 return 0; in gfx_v8_0_soft_reset()
5088 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
5102 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
5115 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); in gfx_v8_0_soft_reset()
5116 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); in gfx_v8_0_soft_reset()
5123 return 0; in gfx_v8_0_soft_reset()
5129 u32 grbm_soft_reset = 0; in gfx_v8_0_post_soft_reset()
5133 return 0; in gfx_v8_0_post_soft_reset()
5143 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5147 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v8_0_post_soft_reset()
5149 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_post_soft_reset()
5164 return 0; in gfx_v8_0_post_soft_reset()
5195 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5196 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5198 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5203 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5204 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5206 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5211 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5212 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5214 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5219 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_gds_switch()
5220 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5222 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_gds_switch()
5253 /* type 0 wave data */ in gfx_v8_0_read_wave_data()
5254 dst[(*no_fields)++] = 0; in gfx_v8_0_read_wave_data()
5280 adev, simd, wave, 0, in gfx_v8_0_read_wave_sgprs()
5305 return 0; in gfx_v8_0_early_init()
5313 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5317 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5326 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5332 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5340 return 0; in gfx_v8_0_late_init()
5352 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5358 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5364 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5370 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5376 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
5403 return 0; in gfx_v8_0_set_powergating_state()
5464 return 0; in gfx_v8_0_set_powergating_state()
5473 *flags = 0; in gfx_v8_0_get_clockgating_state()
5514 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
5516 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
5517 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v8_0_send_serdes_cmd()
5545 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); in gfx_v8_0_send_serdes_cmd()
5551 #define MSG_EXIT_RLC_SAFE_MODE 0
5552 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5553 #define RLC_GPR_REG2__REQ__SHIFT 0
5554 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5555 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5579 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_set_safe_mode()
5588 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_set_safe_mode()
5605 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_unset_safe_mode()
5688 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); in gfx_v8_0_update_medium_grain_clock_gating()
5695 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); in gfx_v8_0_update_medium_grain_clock_gating()
5704 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */ in gfx_v8_0_update_medium_grain_clock_gating()
5857 return 0; in gfx_v8_0_update_gfx_clock_gating()
5863 uint32_t msg_id, pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5864 uint32_t pp_support_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5876 pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5897 pp_state = 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5906 return 0; in gfx_v8_0_tonga_update_gfx_clock_gating()
5913 uint32_t msg_id, pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5914 uint32_t pp_support_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5926 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5945 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5966 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5979 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
5994 pp_state = 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
6004 return 0; in gfx_v8_0_polaris_update_gfx_clock_gating()
6013 return 0; in gfx_v8_0_set_clockgating_state()
6034 return 0; in gfx_v8_0_set_clockgating_state()
6083 reg_mem_engine = 0; in gfx_v8_0_ring_emit_hdp_flush()
6097 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v8_0_ring_emit_hdp_flush()
6102 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6106 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v8_0_ring_emit_vgt_flush()
6108 EVENT_INDEX(0)); in gfx_v8_0_ring_emit_vgt_flush()
6117 u32 header, control = 0; in gfx_v8_0_ring_emit_ib_gfx()
6136 (2 << 0) | in gfx_v8_0_ring_emit_ib_gfx()
6138 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v8_0_ring_emit_ib_gfx()
6139 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v8_0_ring_emit_ib_gfx()
6159 * GDS to 0 for this ring (me/pipe). in gfx_v8_0_ring_emit_ib_compute()
6170 (2 << 0) | in gfx_v8_0_ring_emit_ib_compute()
6172 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v8_0_ring_emit_ib_compute()
6173 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v8_0_ring_emit_ib_compute()
6192 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_gfx()
6193 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v8_0_ring_emit_fence_gfx()
6194 DATA_SEL(1) | INT_SEL(0)); in gfx_v8_0_ring_emit_fence_gfx()
6206 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_gfx()
6207 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v8_0_ring_emit_fence_gfx()
6208 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6224 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_pipeline_sync()
6225 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v8_0_ring_emit_pipeline_sync()
6227 amdgpu_ring_write(ring, 0xffffffff); in gfx_v8_0_ring_emit_pipeline_sync()
6240 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in gfx_v8_0_ring_emit_vm_flush()
6241 WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v8_0_ring_emit_vm_flush()
6242 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v8_0_ring_emit_vm_flush()
6244 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_vm_flush()
6245 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v8_0_ring_emit_vm_flush()
6246 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v8_0_ring_emit_vm_flush()
6247 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v8_0_ring_emit_vm_flush()
6252 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v8_0_ring_emit_vm_flush()
6253 amdgpu_ring_write(ring, 0x0); in gfx_v8_0_ring_emit_vm_flush()
6285 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
6286 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v8_0_ring_emit_fence_compute()
6300 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_fence_kiq()
6309 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v8_0_ring_emit_fence_kiq()
6310 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6312 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_fence_kiq()
6313 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ in gfx_v8_0_ring_emit_fence_kiq()
6319 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v8_ring_emit_sb()
6320 amdgpu_ring_write(ring, 0); in gfx_v8_ring_emit_sb()
6325 uint32_t dw2 = 0; in gfx_v8_ring_emit_cntxcntl()
6330 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v8_ring_emit_cntxcntl()
6334 dw2 |= 0x8001; in gfx_v8_ring_emit_cntxcntl()
6336 dw2 |= 0x01000000; in gfx_v8_ring_emit_cntxcntl()
6338 dw2 |= 0x10002; in gfx_v8_ring_emit_cntxcntl()
6342 dw2 |= 0x10000000; in gfx_v8_ring_emit_cntxcntl()
6348 dw2 |= 0x10000000; in gfx_v8_ring_emit_cntxcntl()
6353 amdgpu_ring_write(ring, 0); in gfx_v8_ring_emit_cntxcntl()
6363 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ in gfx_v8_0_ring_emit_init_cond_exec()
6365 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ in gfx_v8_0_ring_emit_init_cond_exec()
6374 BUG_ON(ring->ring[offset] != 0x55aa55aa); in gfx_v8_0_ring_emit_patch_cond_exec()
6389 amdgpu_ring_write(ring, 0 | /* src: register*/ in gfx_v8_0_ring_emit_rreg()
6393 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_rreg()
6420 amdgpu_ring_write(ring, 0); in gfx_v8_0_ring_emit_wreg()
6427 uint32_t value = 0; in gfx_v8_0_ring_soft_recovery()
6429 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v8_0_ring_soft_recovery()
6430 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v8_0_ring_soft_recovery()
6440 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()
6457 case 0: in gfx_v8_0_set_compute_eop_interrupt_state()
6500 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()
6502 return 0; in gfx_v8_0_set_priv_reg_fault_state()
6511 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()
6513 return 0; in gfx_v8_0_set_priv_inst_fault_state()
6526 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v8_0_set_eop_interrupt_state()
6538 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v8_0_set_eop_interrupt_state()
6552 return 0; in gfx_v8_0_set_eop_interrupt_state()
6564 enable_flag = 0; in gfx_v8_0_set_cp_ecc_int_state()
6597 return 0; in gfx_v8_0_set_cp_ecc_int_state()
6613 enable_flag = 0; in gfx_v8_0_set_sq_int_state()
6623 return 0; in gfx_v8_0_set_sq_int_state()
6635 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v8_0_eop_irq()
6636 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v8_0_eop_irq()
6637 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v8_0_eop_irq()
6640 case 0: in gfx_v8_0_eop_irq()
6641 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6645 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6655 return 0; in gfx_v8_0_eop_irq()
6665 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v8_0_fault()
6666 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v8_0_fault()
6667 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v8_0_fault()
6670 case 0: in gfx_v8_0_fault()
6671 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6675 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6691 return 0; in gfx_v8_0_priv_reg_irq()
6700 return 0; in gfx_v8_0_priv_inst_irq()
6708 return 0; in gfx_v8_0_cp_ecc_error_irq()
6721 case 0: in gfx_v8_0_parse_sq_irq()
6755 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_parse_sq_irq()
6794 unsigned ih_data = entry->src_data[0]; in gfx_v8_0_sq_irq()
6808 return 0; in gfx_v8_0_sq_irq()
6819 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v8_0_emit_mem_sync()
6820 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v8_0_emit_mem_sync()
6821 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v8_0_emit_mem_sync()
6832 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v8_0_emit_mem_sync_compute()
6833 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ in gfx_v8_0_emit_mem_sync_compute()
6834 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v8_0_emit_mem_sync_compute()
6835 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v8_0_emit_mem_sync_compute()
6836 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v8_0_emit_mem_sync_compute()
6862 .align_mask = 0xff,
6863 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6909 .align_mask = 0xff,
6910 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6940 .align_mask = 0xff,
6941 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6968 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
6971 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
7060 int i, j, k, counter, active_cu_number = 0; in gfx_v8_0_get_cu_info()
7061 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v8_0_get_cu_info()
7066 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v8_0_get_cu_info()
7076 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7077 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7079 ao_bitmap = 0; in gfx_v8_0_get_cu_info()
7080 counter = 0; in gfx_v8_0_get_cu_info()
7081 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v8_0_get_cu_info()
7088 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()
7102 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v8_0_get_cu_info()
7118 .minor = 0,
7119 .rev = 0,
7128 .rev = 0,
7155 WRITE_DATA_CACHE_POLICY(0)); in gfx_v8_0_ring_emit_ce_meta()
7188 WRITE_DATA_CACHE_POLICY(0)); in gfx_v8_0_ring_emit_de_meta()