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/qemu/hw/ide/
H A D	ich.c	23 …* 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI C… 44 * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 45 * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 46 * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 47 * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 48 * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 49 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 51 * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 52 * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 [all …]
/qemu/docs/devel/testing/
H A D	blkverify.rst	`52 00000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 53 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 55 000001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 56 000001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................`
/qemu/docs/
H A D	qemupciserial.inf	`73 HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 78 HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 81 HKR,Child0001,VaryingResourceMap,1,00, 08,00,00,00, 08,00,00,00 86 HKR,Child0000,VaryingResourceMap,1,00, 00,00,00,00, 08,00,00,00 89 HKR,Child0001,VaryingResourceMap,1,00, 08,00,00,00, 08,00,00,00 92 HKR,Child0002,VaryingResourceMap,1,00, 10,00,00,00, 08,00,00,00 95 HKR,Child0003,VaryingResourceMap,1,00, 18,00,00,00, 08,00,00,00`
/qemu/tests/qemu-iotests/
H A D	059.out	2309 e100000200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2310 e100000210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2311 e100000220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2312 e100000230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2313 e100000240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2314 e100000250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2315 e100000260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2316 e100000270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2317 e100000280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 2318 e100000290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ [all …]
H A D	154	`63 # 1. Tail unaligned: 00 00 -- -- 64 # 2. Head unaligned: -- -- 00 00 65 # 3. Both unaligned: -- 00 00 -- 66 # 4. Both, 2 clusters: -- -- -- 00 \| 00 -- -- -- 81 # ... \| XX -- 00 -- \| ... 88 # ... \| -- XX 00 -- \| ... 104 # ... \| -- 00 XX -- \| ... 112 # ... \| -- 00 -- XX \| ... 128 # Active layer: -- 00 00 -- 136 # Active layer: -- 00 00 -- [all …]`
H A D	171.out	`15 000001fe: 00 00 0a 0a .... 58 000001fe: 0a 0a 00 00 .... 68 00000ffe: 00 00 .. 80 000001fe: 0a 0a 00 00 .... 90 00000ffe: 00 00 .. 107 000001fe: 00 00 0a 0a .... 150 000001fe: 0a 0a 00 00 .... 160 000009fe: 00 00 .. 174 000001fe: 0a 0a 00 00 .... 184 000009fe: 00 00 .. [all …]`
H A D	287.out	`37 0001fffe: ac ac 00 00 00 00 00 00 ........ 40 0000fffe: 00 00 ac ac ac ac ac ac ........`
H A D	267.out	37 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 48 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 73 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 98 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 109 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 123 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 138 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 149 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 156 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- 170 -- snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 -- [all …]
/qemu/hw/net/rocker/
H A D	rocker-hmp-cmds.c	142 if ((strcmp(key->eth_src, "01:00:00:00:00:00") == 0) && in hmp_rocker_of_dpa_flows() 144 (strcmp(mask->eth_src, "01:00:00:00:00:00") == 0)) { in hmp_rocker_of_dpa_flows() 146 } else if ((strcmp(key->eth_src, "00:00:00:00:00:00") == 0) && in hmp_rocker_of_dpa_flows() 148 (strcmp(mask->eth_src, "01:00:00:00:00:00") == 0)) { in hmp_rocker_of_dpa_flows() 159 if ((strcmp(key->eth_dst, "01:00:00:00:00:00") == 0) && in hmp_rocker_of_dpa_flows() 161 (strcmp(mask->eth_dst, "01:00:00:00:00:00") == 0)) { in hmp_rocker_of_dpa_flows() 163 } else if ((strcmp(key->eth_dst, "00:00:00:00:00:00") == 0) && in hmp_rocker_of_dpa_flows() 165 (strcmp(mask->eth_dst, "01:00:00:00:00:00") == 0)) { in hmp_rocker_of_dpa_flows()
/qemu/tests/tcg/aarch64/
H A D	fcvt.ref	4 00 SINGLE: -nan / 0xffa00000 (0 => OK) 5 00 HALF: 0xff00 (0x1 => INVALID) 22 09 SINGLE: 0.00000000000000000000e+00 / 0000000000 (0 => OK) 34 15 SINGLE: 1.00000000000000000000e+00 / 0x3f800000 (0 => OK) 36 16 SINGLE: 1.00097656250000000000e+00 / 0x3f802000 (0 => OK) 38 17 SINGLE: 2.00000000000000000000e+00 / 0x40000000 (0 => OK) 40 18 SINGLE: 2.71828174591064453125e+00 / 0x402df854 (0 => OK) 42 19 SINGLE: 3.14159274101257324219e+00 / 0x40490fdb (0 => OK) 67 00 SINGLE: -nan / 0xffa00000 (0 => OK) 68 00 DOUBLE: -nan / 0x00fffc000000000000 (0x1 => INVALID) [all …]
/qemu/tests/tcg/arm/
H A D	fcvt.ref	4 00 SINGLE: -nan / 0xffa00000 (0 => OK) 5 00 HALF: 0xff00 (0x1 => INVALID) 22 09 SINGLE: 0.00000000000000000000e+00 / 0000000000 (0 => OK) 34 15 SINGLE: 1.00000000000000000000e+00 / 0x3f800000 (0 => OK) 36 16 SINGLE: 1.00097656250000000000e+00 / 0x3f802000 (0 => OK) 38 17 SINGLE: 2.00000000000000000000e+00 / 0x40000000 (0 => OK) 40 18 SINGLE: 2.71828174591064453125e+00 / 0x402df854 (0 => OK) 42 19 SINGLE: 3.14159274101257324219e+00 / 0x40490fdb (0 => OK) 67 00 SINGLE: -nan / 0xffa00000 (0 => OK) 68 00 DOUBLE: -nan / 0x00fffc000000000000 (0x1 => INVALID) [all …]
/qemu/target/arm/tcg/
H A D	a64.decode	113 ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 114 ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 128 ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 129 SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 137 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 138 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 152 MOVN . 00 100101 .. ................ ..... @movw_64 153 MOVN . 00 100101 .. ................ ..... @movw_32 165 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 166 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 [all …]
H A D	sve.decode	422 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 431 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 432 BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 467 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr 473 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 480 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 488 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 521 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 535 INVALID 00000101 00 01 ---- 01 1 -------- ----- 539 INVALID 00000101 00 01 ---- 00 1 -------- ----- [all …]
H A D	sme.decode	24 ZERO 11000000 00 001 00000000000 imm:8 65 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 66 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 74 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 77 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 78 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 80 SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 81 SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 82 USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 83 UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32
H A D	neon-shared.decode	`49 VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 .... \ 51 VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \ 55 VDOT_b16 1111 110 00 . 00 .... .... 1101 . q:1 . 0 .... \ 85 VUSDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \ 87 VSUDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 1 vm:4 \ 89 VDOT_b16_scal 1111 1110 0 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \`
/qemu/docs/specs/
H A D	ppc-spapr-xive.rst	`221 CPU[0000]: USER 00 00 00 00 00 00 00 00 00000000 222 CPU[0000]: OS 00 ff 00 00 ff 00 ff ff 80000400 223 CPU[0000]: POOL 00 00 00 00 00 00 00 00 00000000 224 CPU[0000]: PHYS 00 00 00 00 00 00 00 ff 00000000`
/qemu/target/rx/
H A D	insns.decode	92 ADC_ir 1111 1101 0111 ..00 0010 .... @b3_rd_li 97 ADC_mr 0000 0110 ..10 00.. 0000 0010 .... .... @b4_rd_ldmi 102 ADD_irr 0111 00.. .... .... @b2_rd_rs_li 107 ADD_mr 0000 0110 ..00 10.. .... .... @b3_rd_ld 117 AND_mr 0101 00.. .... .... @b2_rd_ld_ub 119 AND_mr 0000 0110 ..01 00.. .... .... @b3_rd_ld 124 BCLR_im 1111 00.. .... 1... @b2_ld_imm3 179 BSET_im 1111 00.. .... 0... @b2_ld_imm3 186 BSET_rm 1111 1100 0110 00.. .... .... @b3_rd_ld_ub 220 CMP_mr 0000 0110 ..00 01.. .... .... @b3_rd_ld [all …]
/qemu/target/xtensa/core-de212/
H A D	gdb-config.c.inc	123 …5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:5… 125 …5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:5… 127 …5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:5… 129 …5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:5… 131 …3:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:0… 133 …3:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:0… 135 …3:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:0… 137 …3:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:0… 139 …3:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:0… 141 …4:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6… [all …]
/qemu/target/hexagon/imported/
H A D	encode_pp.def	110 STD_PST_IOENC(rbnew, "101","00ttt") 143 STD_ST_GP(rbnew,"101","00ttt") 175 DEF_ENC32(L4_pload##TAG##t_rr, ICLASS_V4LDST" 00 00 "OPC" sssss PPittttt ivvddddd")\ 176 DEF_ENC32(L4_pload##TAG##f_rr, ICLASS_V4LDST" 00 01 "OPC" sssss PPittttt ivvddddd")\ 177 DEF_ENC32(L4_pload##TAG##tnew_rr,ICLASS_V4LDST" 00 10 "OPC" sssss PPittttt ivvddddd")\ 178 DEF_ENC32(L4_pload##TAG##fnew_rr,ICLASS_V4LDST" 00 11 "OPC" sssss PPittttt ivvddddd") 188 DEF_ENC32(S4_pstore##TAG##t_rr, ICLASS_V4LDST" 01 00 "OPC" sssss PPiuuuuu ivv"SRC)\ 198 STD_PST_RRENC(rbnew, "101","00ttt") 209 DEF_ENC32(S4_storei##TAG##t_io, ICLASS_V4LDST" 100 00 "OPC" sssss PPIiiiii ivvIIIII")\ 214 V4_PSTI(rb, "00") [all …]
/qemu/target/hppa/
H A D	insns.decode	166 ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 245 hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 255 hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 257 mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 259 mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 274 ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 275 ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 403 shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 408 extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 414 dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 [all …]
/qemu/target/riscv/
H A D	insn16.decode	`115 illegal 000 000 000 00 --- 00 116 addi 000 ... ... .. ... 00 @c_addi4spn 119 lq 001 ... ... .. ... 00 @cl_q 120 c_fld 001 ... ... .. ... 00 @cl_d 122 lw 010 ... ... .. ... 00 @cl_w 124 sq 101 ... ... .. ... 00 @cs_q 125 c_fsd 101 ... ... .. ... 00 @cs_d 127 sw 110 ... ... .. ... 00 @cs_w 131 ld 011 ... ... .. ... 00 @cl_d 132 c_flw 011 ... ... .. ... 00 @cl_w [all …]`
/qemu/target/xtensa/core-dsp3400/
H A D	gdb-config.c.inc	`71 "03:03:44:00","03:03:04:00",0,0,0,0) 73 "03:13:44:00","03:13:04:00",0,0,0,0) 75 "03:23:44:00","03:23:04:00",0,0,0,0) 77 "03:33:44:00","03:33:04:00",0,0,0,0) 79 "03:43:44:00","03:43:04:00",0,0,0,0) 81 "03:53:44:00","03:53:04:00",0,0,0,0) 83 "03:63:44:00","03:63:04:00",0,0,0,0) 85 "03:73:44:00","03:73:04:00",0,0,0,0) 87 "03:83:44:00","03:83:04:00",0,0,0,0) 89 "03:93:44:00","03:93:04:00",0,0,0,0) [all …]`
/qemu/docs/system/
H A D	images.rst	`59 1 start 41M 2006-08-06 12:38:02 00:00:14.954 60 2 40M 2006-08-06 12:43:29 00:00:18.633 61 3 msys 40M 2006-08-06 12:44:04 00:00:23.514`
/qemu/docs/config/
H A D	q35-emulated.cfg	`28 # 00:00.0 Host bridge 29 # 00:1f.0 ISA bridge / LPC 30 # 00:1f.2 SATA (AHCI) controller 31 # 00:1f.3 SMBus controller 37 # 00:01.0 VGA compatible controller 38 # 00:19.0 Ethernet controller 39 # 00:1a.* USB controller (#2) 40 # 00:1b.0 Audio device 41 # 00:1c.* PCI bridge (PCI Express Root Ports) 42 # 00:1d.* USB Controller (#1) [all …]`
/qemu/target/xtensa/core-de233_fpu/
H A D	gdb-config.c.inc	`76 "03:03:54:00","03:03:14:00",0,0,0,0) 78 "03:13:54:00","03:13:14:00",0,0,0,0) 80 "03:23:54:00","03:23:14:00",0,0,0,0) 82 "03:33:54:00","03:33:14:00",0,0,0,0) 84 "03:43:54:00","03:43:14:00",0,0,0,0) 86 "03:53:54:00","03:53:14:00",0,0,0,0) 88 "03:63:54:00","03:63:14:00",0,0,0,0) 90 "03:73:54:00","03:73:14:00",0,0,0,0) 92 "03:83:54:00","03:83:14:00",0,0,0,0) 94 "03:93:54:00","03:93:14:00",0,0,0,0) [all …]`

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