| /linux-5.10/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpkg.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
65 #define NH_FLD_ETH_LENGTH BIT(2)
66 #define NH_FLD_ETH_TYPE BIT(3)
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| /linux-5.10/drivers/net/dsa/microchip/ |
| D | ksz9477_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
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| D | ksz8795_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
45 #define SW_CHECK_LENGTH BIT(3)
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| /linux-5.10/drivers/staging/emxx_udc/ |
| D | emxx_udc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 /*---------------------------------------------------------------------------*/
13 /*----------------- Default define */
17 /*------------ Board dependence(Resource) */
26 /*------------ Board dependence(Wait) */
33 /*------------ Controller dependence */
50 #define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
52 #define INT_SEL BIT(10)
53 #define CONSTFS BIT(9)
54 #define SOF_RCV BIT(8)
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| /linux-5.10/drivers/staging/rtl8188eu/include/ |
| D | rtl8188e_spec.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
56 * Multi-Function GPIO Pin Control.
59 * Multi-Function GPIO Select.
63 * Multi-Function control source.
175 /* RTL8723 series ------------------------------ */
250 /* Format for offset 540h-542h:
261 * |<--Setup--|--Hold------------>|
262 * --------------|----------------------
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| /linux-5.10/drivers/staging/comedi/drivers/ |
| D | ni_stc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
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| /linux-5.10/drivers/clk/bcm/ |
| D | clk-bcm63xx-gate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
9 #include <dt-bindings/clock/bcm3368-clock.h>
10 #include <dt-bindings/clock/bcm6318-clock.h>
11 #include <dt-bindings/clock/bcm6328-clock.h>
12 #include <dt-bindings/clock/bcm6358-clock.h>
13 #include <dt-bindings/clock/bcm6362-clock.h>
14 #include <dt-bindings/clock/bcm6368-clock.h>
15 #include <dt-bindings/clock/bcm63268-clock.h>
19 u8 bit; member
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| /linux-5.10/include/linux/ |
| D | hwmon.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 hwmon.h - part of lm_sensors, Linux kernel modules for hardware monitoring
49 #define HWMON_C_TEMP_RESET_HISTORY BIT(hwmon_chip_temp_reset_history)
50 #define HWMON_C_IN_RESET_HISTORY BIT(hwmon_chip_in_reset_history)
51 #define HWMON_C_CURR_RESET_HISTORY BIT(hwmon_chip_curr_reset_history)
52 #define HWMON_C_POWER_RESET_HISTORY BIT(hwmon_chip_power_reset_history)
53 #define HWMON_C_REGISTER_TZ BIT(hwmon_chip_register_tz)
54 #define HWMON_C_UPDATE_INTERVAL BIT(hwmon_chip_update_interval)
55 #define HWMON_C_ALARMS BIT(hwmon_chip_alarms)
56 #define HWMON_C_SAMPLES BIT(hwmon_chip_samples)
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| /linux-5.10/include/linux/mfd/ |
| D | lp87565.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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| /linux-5.10/drivers/net/ieee802154/ |
| D | mcr20a.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
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| /linux-5.10/drivers/usb/typec/tcpm/ |
| D | fusb302_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
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| /linux-5.10/drivers/net/wireless/realtek/rtl8xxxu/ |
| D | rtl8xxxu_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
10 #define SYS_ISO_MD2PP BIT(0)
11 #define SYS_ISO_ANALOG_IPS BIT(5)
12 #define SYS_ISO_DIOR BIT(9)
13 #define SYS_ISO_PWC_EV25V BIT(14)
14 #define SYS_ISO_PWC_EV12V BIT(15)
17 #define SYS_FUNC_BBRSTB BIT(0)
18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
19 #define SYS_FUNC_USBA BIT(2)
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| /linux-5.10/include/linux/mfd/abx500/ |
| D | ab8500-sysctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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| /linux-5.10/drivers/staging/vt6656/ |
| D | mac.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
15 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
16 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
17 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
146 #define I2MCFG_BOUNDCTL BIT(7)
147 #define I2MCFG_WAITCTL BIT(5)
148 #define I2MCFG_SCLOECTL BIT(4)
149 #define I2MCFG_WBUSYCTL BIT(3)
150 #define I2MCFG_NORETRY BIT(2)
151 #define I2MCFG_I2MLDSEQ BIT(1)
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| /linux-5.10/drivers/reset/ |
| D | reset-imx7.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/reset/imx7-reset.h>
17 #include <dt-bindings/reset/imx8mq-reset.h>
18 #include <dt-bindings/reset/imx8mp-reset.h>
21 unsigned int offset, bit; member
51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()
53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()
54 signal->offset, signal->bit, value); in imx7_reset_update()
58 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
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| /linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/ |
| D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
106 /*-----------------------------------------------------
110 *-----------------------------------------------------
121 /*-----------------------------------------------------
125 *-----------------------------------------------------
137 /*-----------------------------------------------------
141 *-----------------------------------------------------
206 *-----------------------------------------------------
210 *-----------------------------------------------------
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| /linux-5.10/arch/mips/include/asm/mach-loongson32/ |
| D | regs-mux.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define UART0_USE_PWM23 BIT(28)
20 #define UART0_USE_PWM01 BIT(27)
21 #define UART1_USE_LCD0_5_6_11 BIT(26)
22 #define I2C2_USE_CAN1 BIT(25)
23 #define I2C1_USE_CAN0 BIT(24)
24 #define NAND3_USE_UART5 BIT(23)
25 #define NAND3_USE_UART4 BIT(22)
26 #define NAND3_USE_UART1_DAT BIT(21)
27 #define NAND3_USE_UART1_CTS BIT(20)
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| /linux-5.10/drivers/net/fddi/skfp/h/ |
| D | skfbi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
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| /linux-5.10/drivers/usb/dwc2/ |
| D | hw.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
44 #define GOTGCTL_CHIRPEN BIT(27)
47 #define GOTGCTL_OTGVER BIT(20)
48 #define GOTGCTL_BSESVLD BIT(19)
49 #define GOTGCTL_ASESVLD BIT(18)
50 #define GOTGCTL_DBNC_SHORT BIT(17)
51 #define GOTGCTL_CONID_B BIT(16)
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| /linux-5.10/drivers/soc/rockchip/ |
| D | pm_domains.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <dt-bindings/power/px30-power.h>
20 #include <dt-bindings/power/rk3036-power.h>
21 #include <dt-bindings/power/rk3066-power.h>
22 #include <dt-bindings/power/rk3128-power.h>
23 #include <dt-bindings/power/rk3188-power.h>
24 #include <dt-bindings/power/rk3228-power.h>
25 #include <dt-bindings/power/rk3288-power.h>
26 #include <dt-bindings/power/rk3328-power.h>
27 #include <dt-bindings/power/rk3366-power.h>
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| /linux-5.10/drivers/media/platform/omap3isp/ |
| D | ispreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
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| /linux-5.10/drivers/usb/mtu3/ |
| D | mtu3_hw_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
23 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
93 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
96 #define EP_CTRL_INTR BIT(5)
97 #define MAC2_INTR BIT(4)
98 #define DMA_INTR BIT(3)
99 #define MAC3_INTR BIT(2)
100 #define QMU_INTR BIT(1)
101 #define BMU_INTR BIT(0)
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| /linux-5.10/include/linux/platform_data/x86/ |
| D | pmc_atom.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 #define BIT_FD_GMM BIT(3)
27 #define BIT_FD_ISH BIT(4)
32 #define BIT_LPC_CLOCK_RUN BIT(4)
33 #define BIT_SHARED_IRQ_GPSC BIT(5)
34 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
35 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
36 #define BIT_SHARED_IRQ_GPSS BIT(20)
56 #define PMC_PSS_BIT_GBE BIT(0)
57 #define PMC_PSS_BIT_SATA BIT(1)
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| /linux-5.10/drivers/net/ethernet/altera/ |
| D | altera_sgdmahw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
22 /* bit 0: error
23 * bit 1: length error
24 * bit 2: crc error
25 * bit 3: truncated error
26 * bit 4: phy error
27 * bit 5: collision error
28 * bit 6: reserved
29 * bit 7: status eop for recv case
33 /* bit 0: eop
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| /linux-5.10/sound/soc/fsl/ |
| D | fsl_micfil.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
35 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
37 #define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
38 #define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
40 #define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
41 #define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
43 #define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
44 #define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
46 #define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
47 #define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
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