Lines Matching +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
23 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
93 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
96 #define EP_CTRL_INTR BIT(5)
97 #define MAC2_INTR BIT(4)
98 #define DMA_INTR BIT(3)
99 #define MAC3_INTR BIT(2)
100 #define QMU_INTR BIT(1)
101 #define BMU_INTR BIT(0)
107 #define EPRISR(x) (BIT(16) << (x))
108 #define SETUPENDISR BIT(16)
109 #define EPTISR(x) (BIT(0) << (x))
110 #define EP0ISR BIT(0)
113 #define EP0_SENDSTALL BIT(25)
114 #define EP0_FIFOFULL BIT(23)
115 #define EP0_SENTSTALL BIT(22)
116 #define EP0_DPHTX BIT(20)
117 #define EP0_DATAEND BIT(19)
118 #define EP0_TXPKTRDY BIT(18)
119 #define EP0_SETUPPKTRDY BIT(17)
120 #define EP0_RXPKTRDY BIT(16)
126 #define TX_DMAREQEN BIT(29)
127 #define TX_FIFOFULL BIT(25)
128 #define TX_FIFOEMPTY BIT(24)
129 #define TX_SENTSTALL BIT(22)
130 #define TX_SENDSTALL BIT(21)
131 #define TX_TXPKTRDY BIT(16)
167 #define RX_DMAREQEN BIT(29)
168 #define RX_SENTSTALL BIT(22)
169 #define RX_SENDSTALL BIT(21)
170 #define RX_RXPKTRDY BIT(16)
200 #define QMU_RX_CS_EN(x) (BIT(16) << (x))
201 #define QMU_TX_CS_EN(x) (BIT(0) << (x))
202 #define QMU_CS16B_EN BIT(0)
205 #define QMU_TX_ZLP(x) (BIT(0) << (x))
208 #define QMU_RX_COZ(x) (BIT(16) << (x))
209 #define QMU_RX_ZLP(x) (BIT(0) << (x))
220 #define QMU_Q_ACTIVE BIT(15)
221 #define QMU_Q_STOP BIT(2)
222 #define QMU_Q_RESUME BIT(1)
223 #define QMU_Q_START BIT(0)
226 #define QMU_RX_DONE_INT(x) (BIT(16) << (x))
227 #define QMU_TX_DONE_INT(x) (BIT(0) << (x))
230 #define RXQ_ZLPERR_INT BIT(20)
231 #define RXQ_LENERR_INT BIT(18)
232 #define RXQ_CSERR_INT BIT(17)
233 #define RXQ_EMPTY_INT BIT(16)
234 #define TXQ_LENERR_INT BIT(2)
235 #define TXQ_CSERR_INT BIT(1)
236 #define TXQ_EMPTY_INT BIT(0)
239 #define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
240 #define QMU_TX_CS_ERR(x) (BIT(0) << (x))
243 #define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
244 #define QMU_RX_CS_ERR(x) (BIT(0) << (x))
247 #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
254 #define DMA_ADDR_36BIT BIT(31)
255 #define VBUS_ON BIT(1)
256 #define VBUS_FRC_EN BIT(0)
259 /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
267 /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
272 #define HW_USB2_3_SEL BIT(18)
273 #define SW_USB2_3_SEL_EN BIT(17)
274 #define SW_USB2_3_SEL BIT(16)
278 #define EP1_IN_RST BIT(17)
279 #define EP1_OUT_RST BIT(1)
280 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
281 #define EP0_RST BIT(0)
285 #define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
288 /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
299 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
302 #define FORCE_POLLING_FAIL BIT(4)
303 #define FORCE_RXDETECT_FAIL BIT(3)
304 #define SOFT_U3_EXIT_EN BIT(2)
305 #define COMPLIANCE_EN BIT(1)
306 #define U1_GO_U2_EN BIT(0)
309 #define USB3_EN BIT(0)
316 #define U3_RESUME_INTR BIT(18)
317 #define U3_LFPS_TMOUT_INTR BIT(17)
318 #define VBUS_FALL_INTR BIT(16)
319 #define VBUS_RISE_INTR BIT(15)
320 #define RXDET_SUCCESS_INTR BIT(14)
321 #define EXIT_U3_INTR BIT(13)
322 #define EXIT_U2_INTR BIT(12)
323 #define EXIT_U1_INTR BIT(11)
324 #define ENTER_U3_INTR BIT(10)
325 #define ENTER_U2_INTR BIT(9)
326 #define ENTER_U1_INTR BIT(8)
327 #define ENTER_U0_INTR BIT(7)
328 #define RECOVERY_INTR BIT(6)
329 #define WARM_RST_INTR BIT(5)
330 #define HOT_RST_INTR BIT(4)
331 #define LOOPBACK_INTR BIT(3)
332 #define COMPLIANCE_INTR BIT(2)
333 #define SS_DISABLE_INTR BIT(1)
334 #define SS_INACTIVE_INTR BIT(0)
337 #define SOFTCON_CLR_AUTO_EN BIT(0)
339 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
345 /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
355 #define SW_U2_ACCEPT_ENABLE BIT(9)
356 #define SW_U1_ACCEPT_ENABLE BIT(8)
357 #define UX_EXIT BIT(5)
358 #define LGO_U3 BIT(4)
359 #define LGO_U2 BIT(3)
360 #define LGO_U1 BIT(2)
361 #define SW_U2_REQUEST_ENABLE BIT(1)
362 #define SW_U1_REQUEST_ENABLE BIT(0)
365 #define CLR_LINK_ERR_CNT BIT(16)
368 /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
381 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
384 #define LPM_BESL_STALL BIT(14)
385 #define LPM_BESLD_STALL BIT(13)
386 #define LPM_RWP BIT(11)
387 #define LPM_HRWE BIT(10)
389 #define ISO_UPDATE BIT(7)
390 #define SOFT_CONN BIT(6)
391 #define HS_ENABLE BIT(5)
392 #define RESUME BIT(2)
393 #define SUSPENDM_ENABLE BIT(0)
396 #define DC_HOSTREQ BIT(1)
397 #define DC_SESSION BIT(0)
400 #define U2U3_AUTO_SWITCH BIT(10)
401 #define LPM_FORCE_STALL BIT(8)
402 #define FIFO_ACCESS BIT(6)
403 #define FORCE_FS BIT(5)
404 #define FORCE_HS BIT(4)
405 #define TEST_PACKET_MODE BIT(3)
406 #define TEST_K_MODE BIT(2)
407 #define TEST_J_MODE BIT(1)
408 #define TEST_SE0_NAK_MODE BIT(0)
412 #define LPM_RESUME_INTR BIT(9)
413 #define LPM_INTR BIT(8)
414 #define DISCONN_INTR BIT(5)
415 #define CONN_INTR BIT(4)
416 #define SOF_INTR BIT(3)
417 #define RESET_INTR BIT(2)
418 #define RESUME_INTR BIT(1)
419 #define SUSPEND_INTR BIT(0)
431 #define LPM_U3_ACK_EN BIT(0)
433 /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
461 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
464 #define SSUSB_IP_SW_RST BIT(0)
467 #define SSUSB_IP_HOST_PDN BIT(0)
470 #define SSUSB_IP_DEV_PDN BIT(0)
473 #define SSUSB_IP_PCIE_PDN BIT(0)
476 #define SSUSB_IP_SLEEP_STS BIT(30)
477 #define SSUSB_U3_MAC_RST_B_STS BIT(16)
478 #define SSUSB_XHCI_RST_B_STS BIT(11)
479 #define SSUSB_SYS125_RST_B_STS BIT(10)
480 #define SSUSB_REF_RST_B_STS BIT(8)
481 #define SSUSB_SYSPLL_STABLE BIT(0)
484 #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
487 #define SSUSB_VBUS_VALID BIT(9)
490 #define SSUSB_VBUS_INTR_CLR BIT(6)
500 #define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
501 #define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
504 #define SSUSB_U3_PORT_SSP_SPEED BIT(9)
505 #define SSUSB_U3_PORT_DUAL_MODE BIT(7)
506 #define SSUSB_U3_PORT_HOST_SEL BIT(2)
507 #define SSUSB_U3_PORT_PDN BIT(1)
508 #define SSUSB_U3_PORT_DIS BIT(0)
511 #define SSUSB_U2_PORT_RG_IDDIG BIT(12)
512 #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
513 #define SSUSB_U2_PORT_VBUSVALID BIT(9)
514 #define SSUSB_U2_PORT_OTG_SEL BIT(7)
515 #define SSUSB_U2_PORT_HOST BIT(2)
516 #define SSUSB_U2_PORT_PDN BIT(1)
517 #define SSUSB_U2_PORT_DIS BIT(0)
521 #define SSUSB_DEV_SW_RST BIT(0)