1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2025 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/if_hsr.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/micrel_phy.h>
26 #include <net/dsa.h>
27 #include <net/ieee8021q.h>
28 #include <net/pkt_cls.h>
29 #include <net/switchdev.h>
30
31 #include "ksz_common.h"
32 #include "ksz_dcb.h"
33 #include "ksz_ptp.h"
34 #include "ksz8.h"
35 #include "ksz9477.h"
36 #include "lan937x.h"
37
38 #define MIB_COUNTER_NUM 0x20
39
40 struct ksz_stats_raw {
41 u64 rx_hi;
42 u64 rx_undersize;
43 u64 rx_fragments;
44 u64 rx_oversize;
45 u64 rx_jabbers;
46 u64 rx_symbol_err;
47 u64 rx_crc_err;
48 u64 rx_align_err;
49 u64 rx_mac_ctrl;
50 u64 rx_pause;
51 u64 rx_bcast;
52 u64 rx_mcast;
53 u64 rx_ucast;
54 u64 rx_64_or_less;
55 u64 rx_65_127;
56 u64 rx_128_255;
57 u64 rx_256_511;
58 u64 rx_512_1023;
59 u64 rx_1024_1522;
60 u64 rx_1523_2000;
61 u64 rx_2001;
62 u64 tx_hi;
63 u64 tx_late_col;
64 u64 tx_pause;
65 u64 tx_bcast;
66 u64 tx_mcast;
67 u64 tx_ucast;
68 u64 tx_deferred;
69 u64 tx_total_col;
70 u64 tx_exc_col;
71 u64 tx_single_col;
72 u64 tx_mult_col;
73 u64 rx_total;
74 u64 tx_total;
75 u64 rx_discards;
76 u64 tx_discards;
77 };
78
79 struct ksz88xx_stats_raw {
80 u64 rx;
81 u64 rx_hi;
82 u64 rx_undersize;
83 u64 rx_fragments;
84 u64 rx_oversize;
85 u64 rx_jabbers;
86 u64 rx_symbol_err;
87 u64 rx_crc_err;
88 u64 rx_align_err;
89 u64 rx_mac_ctrl;
90 u64 rx_pause;
91 u64 rx_bcast;
92 u64 rx_mcast;
93 u64 rx_ucast;
94 u64 rx_64_or_less;
95 u64 rx_65_127;
96 u64 rx_128_255;
97 u64 rx_256_511;
98 u64 rx_512_1023;
99 u64 rx_1024_1522;
100 u64 tx;
101 u64 tx_hi;
102 u64 tx_late_col;
103 u64 tx_pause;
104 u64 tx_bcast;
105 u64 tx_mcast;
106 u64 tx_ucast;
107 u64 tx_deferred;
108 u64 tx_total_col;
109 u64 tx_exc_col;
110 u64 tx_single_col;
111 u64 tx_mult_col;
112 u64 rx_discards;
113 u64 tx_discards;
114 };
115
116 static const struct ksz_mib_names ksz88xx_mib_names[] = {
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
126 { 0x09, "rx_mac_ctrl" },
127 { 0x0a, "rx_pause" },
128 { 0x0b, "rx_bcast" },
129 { 0x0c, "rx_mcast" },
130 { 0x0d, "rx_ucast" },
131 { 0x0e, "rx_64_or_less" },
132 { 0x0f, "rx_65_127" },
133 { 0x10, "rx_128_255" },
134 { 0x11, "rx_256_511" },
135 { 0x12, "rx_512_1023" },
136 { 0x13, "rx_1024_1522" },
137 { 0x14, "tx" },
138 { 0x15, "tx_hi" },
139 { 0x16, "tx_late_col" },
140 { 0x17, "tx_pause" },
141 { 0x18, "tx_bcast" },
142 { 0x19, "tx_mcast" },
143 { 0x1a, "tx_ucast" },
144 { 0x1b, "tx_deferred" },
145 { 0x1c, "tx_total_col" },
146 { 0x1d, "tx_exc_col" },
147 { 0x1e, "tx_single_col" },
148 { 0x1f, "tx_mult_col" },
149 { 0x100, "rx_discards" },
150 { 0x101, "tx_discards" },
151 };
152
153 static const struct ksz_mib_names ksz9477_mib_names[] = {
154 { 0x00, "rx_hi" },
155 { 0x01, "rx_undersize" },
156 { 0x02, "rx_fragments" },
157 { 0x03, "rx_oversize" },
158 { 0x04, "rx_jabbers" },
159 { 0x05, "rx_symbol_err" },
160 { 0x06, "rx_crc_err" },
161 { 0x07, "rx_align_err" },
162 { 0x08, "rx_mac_ctrl" },
163 { 0x09, "rx_pause" },
164 { 0x0A, "rx_bcast" },
165 { 0x0B, "rx_mcast" },
166 { 0x0C, "rx_ucast" },
167 { 0x0D, "rx_64_or_less" },
168 { 0x0E, "rx_65_127" },
169 { 0x0F, "rx_128_255" },
170 { 0x10, "rx_256_511" },
171 { 0x11, "rx_512_1023" },
172 { 0x12, "rx_1024_1522" },
173 { 0x13, "rx_1523_2000" },
174 { 0x14, "rx_2001" },
175 { 0x15, "tx_hi" },
176 { 0x16, "tx_late_col" },
177 { 0x17, "tx_pause" },
178 { 0x18, "tx_bcast" },
179 { 0x19, "tx_mcast" },
180 { 0x1A, "tx_ucast" },
181 { 0x1B, "tx_deferred" },
182 { 0x1C, "tx_total_col" },
183 { 0x1D, "tx_exc_col" },
184 { 0x1E, "tx_single_col" },
185 { 0x1F, "tx_mult_col" },
186 { 0x80, "rx_total" },
187 { 0x81, "tx_total" },
188 { 0x82, "rx_discards" },
189 { 0x83, "tx_discards" },
190 };
191
192 struct ksz_driver_strength_prop {
193 const char *name;
194 int offset;
195 int value;
196 };
197
198 enum ksz_driver_strength_type {
199 KSZ_DRIVER_STRENGTH_HI,
200 KSZ_DRIVER_STRENGTH_LO,
201 KSZ_DRIVER_STRENGTH_IO,
202 };
203
204 /**
205 * struct ksz_drive_strength - drive strength mapping
206 * @reg_val: register value
207 * @microamp: microamp value
208 */
209 struct ksz_drive_strength {
210 u32 reg_val;
211 u32 microamp;
212 };
213
214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
215 *
216 * This values are not documented in KSZ9477 variants but confirmed by
217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
219 *
220 * Documentation in KSZ8795CLX provides more information with some
221 * recommendations:
222 * - for high speed signals
223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
224 * 2.5V or 3.3V VDDIO.
225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
226 * using 1.8V VDDIO.
227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
228 * or 3.3V VDDIO.
229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
230 * 5. In same interface, the heavy loading should use higher one of the
231 * drive current strength.
232 * - for low speed signals
233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
236 * 4. If it is heavy loading, can use higher drive current strength.
237 */
238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
239 { SW_DRIVE_STRENGTH_2MA, 2000 },
240 { SW_DRIVE_STRENGTH_4MA, 4000 },
241 { SW_DRIVE_STRENGTH_8MA, 8000 },
242 { SW_DRIVE_STRENGTH_12MA, 12000 },
243 { SW_DRIVE_STRENGTH_16MA, 16000 },
244 { SW_DRIVE_STRENGTH_20MA, 20000 },
245 { SW_DRIVE_STRENGTH_24MA, 24000 },
246 { SW_DRIVE_STRENGTH_28MA, 28000 },
247 };
248
249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
250 * variants.
251 * This values are documented in KSZ8873 and KSZ8863 datasheets.
252 */
253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
254 { 0, 8000 },
255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
256 };
257
258 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
259 unsigned int mode,
260 const struct phylink_link_state *state);
261 static void ksz_phylink_mac_config(struct phylink_config *config,
262 unsigned int mode,
263 const struct phylink_link_state *state);
264 static void ksz_phylink_mac_link_down(struct phylink_config *config,
265 unsigned int mode,
266 phy_interface_t interface);
267
268 /**
269 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
270 * @config: phylink config structure
271 *
272 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for
273 * a detailed explanation of EEE/LPI handling in KSZ switches.
274 */
ksz_phylink_mac_disable_tx_lpi(struct phylink_config * config)275 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config)
276 {
277 }
278
279 /**
280 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
281 * @config: phylink config structure
282 * @timer: timer value before entering LPI (unused)
283 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused)
284 *
285 * This function signals to phylink that the driver architecture supports
286 * LPI management, enabling phylink to control EEE advertisement during
287 * negotiation according to IEEE Std 802.3 (Clause 78).
288 *
289 * Hardware Management of EEE/LPI State:
290 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2),
291 * observation and testing suggest that the actual EEE / Low Power Idle (LPI)
292 * state transitions are managed autonomously by the hardware based on
293 * the auto-negotiation results. (Note: While the datasheet describes EEE
294 * operation based on negotiation, it doesn't explicitly detail the internal
295 * MAC/PHY interaction, so autonomous hardware management of the MAC state
296 * for LPI is inferred from observed behavior).
297 * This hardware control, consistent with the switch's ability to operate
298 * autonomously via strapping, means MAC-level software intervention is not
299 * required or exposed for managing the LPI state once EEE is negotiated.
300 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining
301 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration
302 * Straps).
303 *
304 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3)
305 * lack documented MAC-level LPI control.
306 *
307 * Therefore, this callback performs no action and serves primarily to inform
308 * phylink of LPI awareness and to document the inferred hardware behavior.
309 *
310 * Returns: 0 (Always success)
311 */
ksz_phylink_mac_enable_tx_lpi(struct phylink_config * config,u32 timer,bool tx_clock_stop)312 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
313 u32 timer, bool tx_clock_stop)
314 {
315 return 0;
316 }
317
318 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
319 .mac_config = ksz88x3_phylink_mac_config,
320 .mac_link_down = ksz_phylink_mac_link_down,
321 .mac_link_up = ksz8_phylink_mac_link_up,
322 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
323 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
324 };
325
326 static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
327 .mac_config = ksz_phylink_mac_config,
328 .mac_link_down = ksz_phylink_mac_link_down,
329 .mac_link_up = ksz8_phylink_mac_link_up,
330 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
331 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
332 };
333
334 static const struct ksz_dev_ops ksz8463_dev_ops = {
335 .setup = ksz8_setup,
336 .get_port_addr = ksz8463_get_port_addr,
337 .cfg_port_member = ksz8_cfg_port_member,
338 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
339 .port_setup = ksz8_port_setup,
340 .r_phy = ksz8463_r_phy,
341 .w_phy = ksz8463_w_phy,
342 .r_mib_cnt = ksz8_r_mib_cnt,
343 .r_mib_pkt = ksz8_r_mib_pkt,
344 .r_mib_stat64 = ksz88xx_r_mib_stats64,
345 .freeze_mib = ksz8_freeze_mib,
346 .port_init_cnt = ksz8_port_init_cnt,
347 .fdb_dump = ksz8_fdb_dump,
348 .fdb_add = ksz8_fdb_add,
349 .fdb_del = ksz8_fdb_del,
350 .mdb_add = ksz8_mdb_add,
351 .mdb_del = ksz8_mdb_del,
352 .vlan_filtering = ksz8_port_vlan_filtering,
353 .vlan_add = ksz8_port_vlan_add,
354 .vlan_del = ksz8_port_vlan_del,
355 .mirror_add = ksz8_port_mirror_add,
356 .mirror_del = ksz8_port_mirror_del,
357 .get_caps = ksz8_get_caps,
358 .config_cpu_port = ksz8_config_cpu_port,
359 .enable_stp_addr = ksz8_enable_stp_addr,
360 .reset = ksz8_reset_switch,
361 .init = ksz8_switch_init,
362 .exit = ksz8_switch_exit,
363 .change_mtu = ksz8_change_mtu,
364 };
365
366 static const struct ksz_dev_ops ksz88xx_dev_ops = {
367 .setup = ksz8_setup,
368 .get_port_addr = ksz8_get_port_addr,
369 .cfg_port_member = ksz8_cfg_port_member,
370 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
371 .port_setup = ksz8_port_setup,
372 .r_phy = ksz8_r_phy,
373 .w_phy = ksz8_w_phy,
374 .r_mib_cnt = ksz8_r_mib_cnt,
375 .r_mib_pkt = ksz8_r_mib_pkt,
376 .r_mib_stat64 = ksz88xx_r_mib_stats64,
377 .freeze_mib = ksz8_freeze_mib,
378 .port_init_cnt = ksz8_port_init_cnt,
379 .fdb_dump = ksz8_fdb_dump,
380 .fdb_add = ksz8_fdb_add,
381 .fdb_del = ksz8_fdb_del,
382 .mdb_add = ksz8_mdb_add,
383 .mdb_del = ksz8_mdb_del,
384 .vlan_filtering = ksz8_port_vlan_filtering,
385 .vlan_add = ksz8_port_vlan_add,
386 .vlan_del = ksz8_port_vlan_del,
387 .mirror_add = ksz8_port_mirror_add,
388 .mirror_del = ksz8_port_mirror_del,
389 .get_caps = ksz8_get_caps,
390 .config_cpu_port = ksz8_config_cpu_port,
391 .enable_stp_addr = ksz8_enable_stp_addr,
392 .reset = ksz8_reset_switch,
393 .init = ksz8_switch_init,
394 .exit = ksz8_switch_exit,
395 .change_mtu = ksz8_change_mtu,
396 .pme_write8 = ksz8_pme_write8,
397 .pme_pread8 = ksz8_pme_pread8,
398 .pme_pwrite8 = ksz8_pme_pwrite8,
399 };
400
401 static const struct ksz_dev_ops ksz87xx_dev_ops = {
402 .setup = ksz8_setup,
403 .get_port_addr = ksz8_get_port_addr,
404 .cfg_port_member = ksz8_cfg_port_member,
405 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
406 .port_setup = ksz8_port_setup,
407 .r_phy = ksz8_r_phy,
408 .w_phy = ksz8_w_phy,
409 .r_mib_cnt = ksz8_r_mib_cnt,
410 .r_mib_pkt = ksz8_r_mib_pkt,
411 .r_mib_stat64 = ksz_r_mib_stats64,
412 .freeze_mib = ksz8_freeze_mib,
413 .port_init_cnt = ksz8_port_init_cnt,
414 .fdb_dump = ksz8_fdb_dump,
415 .fdb_add = ksz8_fdb_add,
416 .fdb_del = ksz8_fdb_del,
417 .mdb_add = ksz8_mdb_add,
418 .mdb_del = ksz8_mdb_del,
419 .vlan_filtering = ksz8_port_vlan_filtering,
420 .vlan_add = ksz8_port_vlan_add,
421 .vlan_del = ksz8_port_vlan_del,
422 .mirror_add = ksz8_port_mirror_add,
423 .mirror_del = ksz8_port_mirror_del,
424 .get_caps = ksz8_get_caps,
425 .config_cpu_port = ksz8_config_cpu_port,
426 .enable_stp_addr = ksz8_enable_stp_addr,
427 .reset = ksz8_reset_switch,
428 .init = ksz8_switch_init,
429 .exit = ksz8_switch_exit,
430 .change_mtu = ksz8_change_mtu,
431 .pme_write8 = ksz8_pme_write8,
432 .pme_pread8 = ksz8_pme_pread8,
433 .pme_pwrite8 = ksz8_pme_pwrite8,
434 };
435
436 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
437 struct phy_device *phydev,
438 unsigned int mode,
439 phy_interface_t interface,
440 int speed, int duplex, bool tx_pause,
441 bool rx_pause);
442
443 static struct phylink_pcs *
ksz_phylink_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)444 ksz_phylink_mac_select_pcs(struct phylink_config *config,
445 phy_interface_t interface)
446 {
447 struct dsa_port *dp = dsa_phylink_to_port(config);
448 struct ksz_device *dev = dp->ds->priv;
449 struct ksz_port *p = &dev->ports[dp->index];
450
451 if (ksz_is_sgmii_port(dev, dp->index) &&
452 (interface == PHY_INTERFACE_MODE_SGMII ||
453 interface == PHY_INTERFACE_MODE_1000BASEX))
454 return p->pcs;
455
456 return NULL;
457 }
458
459 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
460 .mac_config = ksz_phylink_mac_config,
461 .mac_link_down = ksz_phylink_mac_link_down,
462 .mac_link_up = ksz9477_phylink_mac_link_up,
463 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
464 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
465 .mac_select_pcs = ksz_phylink_mac_select_pcs,
466 };
467
468 static const struct ksz_dev_ops ksz9477_dev_ops = {
469 .setup = ksz9477_setup,
470 .get_port_addr = ksz9477_get_port_addr,
471 .cfg_port_member = ksz9477_cfg_port_member,
472 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
473 .port_setup = ksz9477_port_setup,
474 .set_ageing_time = ksz9477_set_ageing_time,
475 .r_phy = ksz9477_r_phy,
476 .w_phy = ksz9477_w_phy,
477 .r_mib_cnt = ksz9477_r_mib_cnt,
478 .r_mib_pkt = ksz9477_r_mib_pkt,
479 .r_mib_stat64 = ksz_r_mib_stats64,
480 .freeze_mib = ksz9477_freeze_mib,
481 .port_init_cnt = ksz9477_port_init_cnt,
482 .vlan_filtering = ksz9477_port_vlan_filtering,
483 .vlan_add = ksz9477_port_vlan_add,
484 .vlan_del = ksz9477_port_vlan_del,
485 .mirror_add = ksz9477_port_mirror_add,
486 .mirror_del = ksz9477_port_mirror_del,
487 .get_caps = ksz9477_get_caps,
488 .fdb_dump = ksz9477_fdb_dump,
489 .fdb_add = ksz9477_fdb_add,
490 .fdb_del = ksz9477_fdb_del,
491 .mdb_add = ksz9477_mdb_add,
492 .mdb_del = ksz9477_mdb_del,
493 .change_mtu = ksz9477_change_mtu,
494 .pme_write8 = ksz_write8,
495 .pme_pread8 = ksz_pread8,
496 .pme_pwrite8 = ksz_pwrite8,
497 .config_cpu_port = ksz9477_config_cpu_port,
498 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
499 .enable_stp_addr = ksz9477_enable_stp_addr,
500 .reset = ksz9477_reset_switch,
501 .init = ksz9477_switch_init,
502 .exit = ksz9477_switch_exit,
503 .pcs_create = ksz9477_pcs_create,
504 };
505
506 static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
507 .mac_config = ksz_phylink_mac_config,
508 .mac_link_down = ksz_phylink_mac_link_down,
509 .mac_link_up = ksz9477_phylink_mac_link_up,
510 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
511 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
512 };
513
514 static const struct ksz_dev_ops lan937x_dev_ops = {
515 .setup = lan937x_setup,
516 .teardown = lan937x_teardown,
517 .get_port_addr = ksz9477_get_port_addr,
518 .cfg_port_member = ksz9477_cfg_port_member,
519 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
520 .port_setup = lan937x_port_setup,
521 .set_ageing_time = lan937x_set_ageing_time,
522 .mdio_bus_preinit = lan937x_mdio_bus_preinit,
523 .create_phy_addr_map = lan937x_create_phy_addr_map,
524 .r_phy = lan937x_r_phy,
525 .w_phy = lan937x_w_phy,
526 .r_mib_cnt = ksz9477_r_mib_cnt,
527 .r_mib_pkt = ksz9477_r_mib_pkt,
528 .r_mib_stat64 = ksz_r_mib_stats64,
529 .freeze_mib = ksz9477_freeze_mib,
530 .port_init_cnt = ksz9477_port_init_cnt,
531 .vlan_filtering = ksz9477_port_vlan_filtering,
532 .vlan_add = ksz9477_port_vlan_add,
533 .vlan_del = ksz9477_port_vlan_del,
534 .mirror_add = ksz9477_port_mirror_add,
535 .mirror_del = ksz9477_port_mirror_del,
536 .get_caps = lan937x_phylink_get_caps,
537 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
538 .fdb_dump = ksz9477_fdb_dump,
539 .fdb_add = ksz9477_fdb_add,
540 .fdb_del = ksz9477_fdb_del,
541 .mdb_add = ksz9477_mdb_add,
542 .mdb_del = ksz9477_mdb_del,
543 .change_mtu = lan937x_change_mtu,
544 .config_cpu_port = lan937x_config_cpu_port,
545 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
546 .enable_stp_addr = ksz9477_enable_stp_addr,
547 .reset = lan937x_reset_switch,
548 .init = lan937x_switch_init,
549 .exit = lan937x_switch_exit,
550 };
551
552 static const u16 ksz8463_regs[] = {
553 [REG_SW_MAC_ADDR] = 0x10,
554 [REG_IND_CTRL_0] = 0x30,
555 [REG_IND_DATA_8] = 0x26,
556 [REG_IND_DATA_CHECK] = 0x26,
557 [REG_IND_DATA_HI] = 0x28,
558 [REG_IND_DATA_LO] = 0x2C,
559 [REG_IND_MIB_CHECK] = 0x2F,
560 [P_FORCE_CTRL] = 0x0C,
561 [P_LINK_STATUS] = 0x0E,
562 [P_LOCAL_CTRL] = 0x0C,
563 [P_NEG_RESTART_CTRL] = 0x0D,
564 [P_REMOTE_STATUS] = 0x0E,
565 [P_SPEED_STATUS] = 0x0F,
566 [S_TAIL_TAG_CTRL] = 0xAD,
567 [P_STP_CTRL] = 0x6F,
568 [S_START_CTRL] = 0x01,
569 [S_BROADCAST_CTRL] = 0x06,
570 [S_MULTICAST_CTRL] = 0x04,
571 };
572
573 static const u32 ksz8463_masks[] = {
574 [PORT_802_1P_REMAPPING] = BIT(3),
575 [SW_TAIL_TAG_ENABLE] = BIT(0),
576 [MIB_COUNTER_OVERFLOW] = BIT(7),
577 [MIB_COUNTER_VALID] = BIT(6),
578 [VLAN_TABLE_FID] = GENMASK(15, 12),
579 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
580 [VLAN_TABLE_VALID] = BIT(19),
581 [STATIC_MAC_TABLE_VALID] = BIT(19),
582 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
583 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
584 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
585 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
586 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
587 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
588 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
589 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
590 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
591 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
592 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
593 };
594
595 static u8 ksz8463_shifts[] = {
596 [VLAN_TABLE_MEMBERSHIP_S] = 16,
597 [STATIC_MAC_FWD_PORTS] = 16,
598 [STATIC_MAC_FID] = 22,
599 [DYNAMIC_MAC_ENTRIES_H] = 8,
600 [DYNAMIC_MAC_ENTRIES] = 24,
601 [DYNAMIC_MAC_FID] = 16,
602 [DYNAMIC_MAC_TIMESTAMP] = 22,
603 [DYNAMIC_MAC_SRC_PORT] = 20,
604 };
605
606 static const u16 ksz8795_regs[] = {
607 [REG_SW_MAC_ADDR] = 0x68,
608 [REG_IND_CTRL_0] = 0x6E,
609 [REG_IND_DATA_8] = 0x70,
610 [REG_IND_DATA_CHECK] = 0x72,
611 [REG_IND_DATA_HI] = 0x71,
612 [REG_IND_DATA_LO] = 0x75,
613 [REG_IND_MIB_CHECK] = 0x74,
614 [REG_IND_BYTE] = 0xA0,
615 [P_FORCE_CTRL] = 0x0C,
616 [P_LINK_STATUS] = 0x0E,
617 [P_LOCAL_CTRL] = 0x07,
618 [P_NEG_RESTART_CTRL] = 0x0D,
619 [P_REMOTE_STATUS] = 0x08,
620 [P_SPEED_STATUS] = 0x09,
621 [S_TAIL_TAG_CTRL] = 0x0C,
622 [P_STP_CTRL] = 0x02,
623 [S_START_CTRL] = 0x01,
624 [S_BROADCAST_CTRL] = 0x06,
625 [S_MULTICAST_CTRL] = 0x04,
626 [P_XMII_CTRL_0] = 0x06,
627 [P_XMII_CTRL_1] = 0x06,
628 [REG_SW_PME_CTRL] = 0x8003,
629 [REG_PORT_PME_STATUS] = 0x8003,
630 [REG_PORT_PME_CTRL] = 0x8007,
631 };
632
633 static const u32 ksz8795_masks[] = {
634 [PORT_802_1P_REMAPPING] = BIT(7),
635 [SW_TAIL_TAG_ENABLE] = BIT(1),
636 [MIB_COUNTER_OVERFLOW] = BIT(6),
637 [MIB_COUNTER_VALID] = BIT(5),
638 [VLAN_TABLE_FID] = GENMASK(6, 0),
639 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
640 [VLAN_TABLE_VALID] = BIT(12),
641 [STATIC_MAC_TABLE_VALID] = BIT(21),
642 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
643 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
644 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
645 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
646 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
647 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
648 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
649 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
650 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
651 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
652 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
653 [P_MII_TX_FLOW_CTRL] = BIT(5),
654 [P_MII_RX_FLOW_CTRL] = BIT(5),
655 };
656
657 static const u8 ksz8795_xmii_ctrl0[] = {
658 [P_MII_100MBIT] = 0,
659 [P_MII_10MBIT] = 1,
660 [P_MII_FULL_DUPLEX] = 0,
661 [P_MII_HALF_DUPLEX] = 1,
662 };
663
664 static const u8 ksz8795_xmii_ctrl1[] = {
665 [P_RGMII_SEL] = 3,
666 [P_GMII_SEL] = 2,
667 [P_RMII_SEL] = 1,
668 [P_MII_SEL] = 0,
669 [P_GMII_1GBIT] = 1,
670 [P_GMII_NOT_1GBIT] = 0,
671 };
672
673 static const u8 ksz8795_shifts[] = {
674 [VLAN_TABLE_MEMBERSHIP_S] = 7,
675 [VLAN_TABLE] = 16,
676 [STATIC_MAC_FWD_PORTS] = 16,
677 [STATIC_MAC_FID] = 24,
678 [DYNAMIC_MAC_ENTRIES_H] = 3,
679 [DYNAMIC_MAC_ENTRIES] = 29,
680 [DYNAMIC_MAC_FID] = 16,
681 [DYNAMIC_MAC_TIMESTAMP] = 27,
682 [DYNAMIC_MAC_SRC_PORT] = 24,
683 };
684
685 static const u16 ksz8863_regs[] = {
686 [REG_SW_MAC_ADDR] = 0x70,
687 [REG_IND_CTRL_0] = 0x79,
688 [REG_IND_DATA_8] = 0x7B,
689 [REG_IND_DATA_CHECK] = 0x7B,
690 [REG_IND_DATA_HI] = 0x7C,
691 [REG_IND_DATA_LO] = 0x80,
692 [REG_IND_MIB_CHECK] = 0x80,
693 [P_FORCE_CTRL] = 0x0C,
694 [P_LINK_STATUS] = 0x0E,
695 [P_LOCAL_CTRL] = 0x0C,
696 [P_NEG_RESTART_CTRL] = 0x0D,
697 [P_REMOTE_STATUS] = 0x0E,
698 [P_SPEED_STATUS] = 0x0F,
699 [S_TAIL_TAG_CTRL] = 0x03,
700 [P_STP_CTRL] = 0x02,
701 [S_START_CTRL] = 0x01,
702 [S_BROADCAST_CTRL] = 0x06,
703 [S_MULTICAST_CTRL] = 0x04,
704 };
705
706 static const u32 ksz8863_masks[] = {
707 [PORT_802_1P_REMAPPING] = BIT(3),
708 [SW_TAIL_TAG_ENABLE] = BIT(6),
709 [MIB_COUNTER_OVERFLOW] = BIT(7),
710 [MIB_COUNTER_VALID] = BIT(6),
711 [VLAN_TABLE_FID] = GENMASK(15, 12),
712 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
713 [VLAN_TABLE_VALID] = BIT(19),
714 [STATIC_MAC_TABLE_VALID] = BIT(19),
715 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
716 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
717 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
718 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
719 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
720 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
721 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
722 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
723 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
724 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
725 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
726 };
727
728 static u8 ksz8863_shifts[] = {
729 [VLAN_TABLE_MEMBERSHIP_S] = 16,
730 [STATIC_MAC_FWD_PORTS] = 16,
731 [STATIC_MAC_FID] = 22,
732 [DYNAMIC_MAC_ENTRIES_H] = 8,
733 [DYNAMIC_MAC_ENTRIES] = 24,
734 [DYNAMIC_MAC_FID] = 16,
735 [DYNAMIC_MAC_TIMESTAMP] = 22,
736 [DYNAMIC_MAC_SRC_PORT] = 20,
737 };
738
739 static const u16 ksz8895_regs[] = {
740 [REG_SW_MAC_ADDR] = 0x68,
741 [REG_IND_CTRL_0] = 0x6E,
742 [REG_IND_DATA_8] = 0x70,
743 [REG_IND_DATA_CHECK] = 0x72,
744 [REG_IND_DATA_HI] = 0x71,
745 [REG_IND_DATA_LO] = 0x75,
746 [REG_IND_MIB_CHECK] = 0x75,
747 [P_FORCE_CTRL] = 0x0C,
748 [P_LINK_STATUS] = 0x0E,
749 [P_LOCAL_CTRL] = 0x0C,
750 [P_NEG_RESTART_CTRL] = 0x0D,
751 [P_REMOTE_STATUS] = 0x0E,
752 [P_SPEED_STATUS] = 0x09,
753 [S_TAIL_TAG_CTRL] = 0x0C,
754 [P_STP_CTRL] = 0x02,
755 [S_START_CTRL] = 0x01,
756 [S_BROADCAST_CTRL] = 0x06,
757 [S_MULTICAST_CTRL] = 0x04,
758 };
759
760 static const u32 ksz8895_masks[] = {
761 [PORT_802_1P_REMAPPING] = BIT(7),
762 [SW_TAIL_TAG_ENABLE] = BIT(1),
763 [MIB_COUNTER_OVERFLOW] = BIT(7),
764 [MIB_COUNTER_VALID] = BIT(6),
765 [VLAN_TABLE_FID] = GENMASK(6, 0),
766 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
767 [VLAN_TABLE_VALID] = BIT(12),
768 [STATIC_MAC_TABLE_VALID] = BIT(21),
769 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
770 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
771 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
772 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
773 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
774 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
775 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
776 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
777 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
778 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
779 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
780 };
781
782 static const u8 ksz8895_shifts[] = {
783 [VLAN_TABLE_MEMBERSHIP_S] = 7,
784 [VLAN_TABLE] = 13,
785 [STATIC_MAC_FWD_PORTS] = 16,
786 [STATIC_MAC_FID] = 24,
787 [DYNAMIC_MAC_ENTRIES_H] = 3,
788 [DYNAMIC_MAC_ENTRIES] = 29,
789 [DYNAMIC_MAC_FID] = 16,
790 [DYNAMIC_MAC_TIMESTAMP] = 27,
791 [DYNAMIC_MAC_SRC_PORT] = 24,
792 };
793
794 static const u16 ksz9477_regs[] = {
795 [REG_SW_MAC_ADDR] = 0x0302,
796 [P_STP_CTRL] = 0x0B04,
797 [S_START_CTRL] = 0x0300,
798 [S_BROADCAST_CTRL] = 0x0332,
799 [S_MULTICAST_CTRL] = 0x0331,
800 [P_XMII_CTRL_0] = 0x0300,
801 [P_XMII_CTRL_1] = 0x0301,
802 [REG_SW_PME_CTRL] = 0x0006,
803 [REG_PORT_PME_STATUS] = 0x0013,
804 [REG_PORT_PME_CTRL] = 0x0017,
805 };
806
807 static const u32 ksz9477_masks[] = {
808 [ALU_STAT_WRITE] = 0,
809 [ALU_STAT_READ] = 1,
810 [P_MII_TX_FLOW_CTRL] = BIT(5),
811 [P_MII_RX_FLOW_CTRL] = BIT(3),
812 };
813
814 static const u8 ksz9477_shifts[] = {
815 [ALU_STAT_INDEX] = 16,
816 };
817
818 static const u8 ksz9477_xmii_ctrl0[] = {
819 [P_MII_100MBIT] = 1,
820 [P_MII_10MBIT] = 0,
821 [P_MII_FULL_DUPLEX] = 1,
822 [P_MII_HALF_DUPLEX] = 0,
823 };
824
825 static const u8 ksz9477_xmii_ctrl1[] = {
826 [P_RGMII_SEL] = 0,
827 [P_RMII_SEL] = 1,
828 [P_GMII_SEL] = 2,
829 [P_MII_SEL] = 3,
830 [P_GMII_1GBIT] = 0,
831 [P_GMII_NOT_1GBIT] = 1,
832 };
833
834 static const u32 lan937x_masks[] = {
835 [ALU_STAT_WRITE] = 1,
836 [ALU_STAT_READ] = 2,
837 [P_MII_TX_FLOW_CTRL] = BIT(5),
838 [P_MII_RX_FLOW_CTRL] = BIT(3),
839 };
840
841 static const u8 lan937x_shifts[] = {
842 [ALU_STAT_INDEX] = 8,
843 };
844
845 static const struct regmap_range ksz8563_valid_regs[] = {
846 regmap_reg_range(0x0000, 0x0003),
847 regmap_reg_range(0x0006, 0x0006),
848 regmap_reg_range(0x000f, 0x001f),
849 regmap_reg_range(0x0100, 0x0100),
850 regmap_reg_range(0x0104, 0x0107),
851 regmap_reg_range(0x010d, 0x010d),
852 regmap_reg_range(0x0110, 0x0113),
853 regmap_reg_range(0x0120, 0x012b),
854 regmap_reg_range(0x0201, 0x0201),
855 regmap_reg_range(0x0210, 0x0213),
856 regmap_reg_range(0x0300, 0x0300),
857 regmap_reg_range(0x0302, 0x031b),
858 regmap_reg_range(0x0320, 0x032b),
859 regmap_reg_range(0x0330, 0x0336),
860 regmap_reg_range(0x0338, 0x033e),
861 regmap_reg_range(0x0340, 0x035f),
862 regmap_reg_range(0x0370, 0x0370),
863 regmap_reg_range(0x0378, 0x0378),
864 regmap_reg_range(0x037c, 0x037d),
865 regmap_reg_range(0x0390, 0x0393),
866 regmap_reg_range(0x0400, 0x040e),
867 regmap_reg_range(0x0410, 0x042f),
868 regmap_reg_range(0x0500, 0x0519),
869 regmap_reg_range(0x0520, 0x054b),
870 regmap_reg_range(0x0550, 0x05b3),
871
872 /* port 1 */
873 regmap_reg_range(0x1000, 0x1001),
874 regmap_reg_range(0x1004, 0x100b),
875 regmap_reg_range(0x1013, 0x1013),
876 regmap_reg_range(0x1017, 0x1017),
877 regmap_reg_range(0x101b, 0x101b),
878 regmap_reg_range(0x101f, 0x1021),
879 regmap_reg_range(0x1030, 0x1030),
880 regmap_reg_range(0x1100, 0x1111),
881 regmap_reg_range(0x111a, 0x111d),
882 regmap_reg_range(0x1122, 0x1127),
883 regmap_reg_range(0x112a, 0x112b),
884 regmap_reg_range(0x1136, 0x1139),
885 regmap_reg_range(0x113e, 0x113f),
886 regmap_reg_range(0x1400, 0x1401),
887 regmap_reg_range(0x1403, 0x1403),
888 regmap_reg_range(0x1410, 0x1417),
889 regmap_reg_range(0x1420, 0x1423),
890 regmap_reg_range(0x1500, 0x1507),
891 regmap_reg_range(0x1600, 0x1612),
892 regmap_reg_range(0x1800, 0x180f),
893 regmap_reg_range(0x1900, 0x1907),
894 regmap_reg_range(0x1914, 0x191b),
895 regmap_reg_range(0x1a00, 0x1a03),
896 regmap_reg_range(0x1a04, 0x1a08),
897 regmap_reg_range(0x1b00, 0x1b01),
898 regmap_reg_range(0x1b04, 0x1b04),
899 regmap_reg_range(0x1c00, 0x1c05),
900 regmap_reg_range(0x1c08, 0x1c1b),
901
902 /* port 2 */
903 regmap_reg_range(0x2000, 0x2001),
904 regmap_reg_range(0x2004, 0x200b),
905 regmap_reg_range(0x2013, 0x2013),
906 regmap_reg_range(0x2017, 0x2017),
907 regmap_reg_range(0x201b, 0x201b),
908 regmap_reg_range(0x201f, 0x2021),
909 regmap_reg_range(0x2030, 0x2030),
910 regmap_reg_range(0x2100, 0x2111),
911 regmap_reg_range(0x211a, 0x211d),
912 regmap_reg_range(0x2122, 0x2127),
913 regmap_reg_range(0x212a, 0x212b),
914 regmap_reg_range(0x2136, 0x2139),
915 regmap_reg_range(0x213e, 0x213f),
916 regmap_reg_range(0x2400, 0x2401),
917 regmap_reg_range(0x2403, 0x2403),
918 regmap_reg_range(0x2410, 0x2417),
919 regmap_reg_range(0x2420, 0x2423),
920 regmap_reg_range(0x2500, 0x2507),
921 regmap_reg_range(0x2600, 0x2612),
922 regmap_reg_range(0x2800, 0x280f),
923 regmap_reg_range(0x2900, 0x2907),
924 regmap_reg_range(0x2914, 0x291b),
925 regmap_reg_range(0x2a00, 0x2a03),
926 regmap_reg_range(0x2a04, 0x2a08),
927 regmap_reg_range(0x2b00, 0x2b01),
928 regmap_reg_range(0x2b04, 0x2b04),
929 regmap_reg_range(0x2c00, 0x2c05),
930 regmap_reg_range(0x2c08, 0x2c1b),
931
932 /* port 3 */
933 regmap_reg_range(0x3000, 0x3001),
934 regmap_reg_range(0x3004, 0x300b),
935 regmap_reg_range(0x3013, 0x3013),
936 regmap_reg_range(0x3017, 0x3017),
937 regmap_reg_range(0x301b, 0x301b),
938 regmap_reg_range(0x301f, 0x3021),
939 regmap_reg_range(0x3030, 0x3030),
940 regmap_reg_range(0x3300, 0x3301),
941 regmap_reg_range(0x3303, 0x3303),
942 regmap_reg_range(0x3400, 0x3401),
943 regmap_reg_range(0x3403, 0x3403),
944 regmap_reg_range(0x3410, 0x3417),
945 regmap_reg_range(0x3420, 0x3423),
946 regmap_reg_range(0x3500, 0x3507),
947 regmap_reg_range(0x3600, 0x3612),
948 regmap_reg_range(0x3800, 0x380f),
949 regmap_reg_range(0x3900, 0x3907),
950 regmap_reg_range(0x3914, 0x391b),
951 regmap_reg_range(0x3a00, 0x3a03),
952 regmap_reg_range(0x3a04, 0x3a08),
953 regmap_reg_range(0x3b00, 0x3b01),
954 regmap_reg_range(0x3b04, 0x3b04),
955 regmap_reg_range(0x3c00, 0x3c05),
956 regmap_reg_range(0x3c08, 0x3c1b),
957 };
958
959 static const struct regmap_access_table ksz8563_register_set = {
960 .yes_ranges = ksz8563_valid_regs,
961 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
962 };
963
964 static const struct regmap_range ksz9477_valid_regs[] = {
965 regmap_reg_range(0x0000, 0x0003),
966 regmap_reg_range(0x0006, 0x0006),
967 regmap_reg_range(0x0010, 0x001f),
968 regmap_reg_range(0x0100, 0x0100),
969 regmap_reg_range(0x0103, 0x0107),
970 regmap_reg_range(0x010d, 0x010d),
971 regmap_reg_range(0x0110, 0x0113),
972 regmap_reg_range(0x0120, 0x012b),
973 regmap_reg_range(0x0201, 0x0201),
974 regmap_reg_range(0x0210, 0x0213),
975 regmap_reg_range(0x0300, 0x0300),
976 regmap_reg_range(0x0302, 0x031b),
977 regmap_reg_range(0x0320, 0x032b),
978 regmap_reg_range(0x0330, 0x0336),
979 regmap_reg_range(0x0338, 0x033b),
980 regmap_reg_range(0x033e, 0x033e),
981 regmap_reg_range(0x0340, 0x035f),
982 regmap_reg_range(0x0370, 0x0370),
983 regmap_reg_range(0x0378, 0x0378),
984 regmap_reg_range(0x037c, 0x037d),
985 regmap_reg_range(0x0390, 0x0393),
986 regmap_reg_range(0x0400, 0x040e),
987 regmap_reg_range(0x0410, 0x042f),
988 regmap_reg_range(0x0444, 0x044b),
989 regmap_reg_range(0x0450, 0x046f),
990 regmap_reg_range(0x0500, 0x0519),
991 regmap_reg_range(0x0520, 0x054b),
992 regmap_reg_range(0x0550, 0x05b3),
993 regmap_reg_range(0x0604, 0x060b),
994 regmap_reg_range(0x0610, 0x0612),
995 regmap_reg_range(0x0614, 0x062c),
996 regmap_reg_range(0x0640, 0x0645),
997 regmap_reg_range(0x0648, 0x064d),
998
999 /* port 1 */
1000 regmap_reg_range(0x1000, 0x1001),
1001 regmap_reg_range(0x1013, 0x1013),
1002 regmap_reg_range(0x1017, 0x1017),
1003 regmap_reg_range(0x101b, 0x101b),
1004 regmap_reg_range(0x101f, 0x1020),
1005 regmap_reg_range(0x1030, 0x1030),
1006 regmap_reg_range(0x1100, 0x1115),
1007 regmap_reg_range(0x111a, 0x111f),
1008 regmap_reg_range(0x1120, 0x112b),
1009 regmap_reg_range(0x1134, 0x113b),
1010 regmap_reg_range(0x113c, 0x113f),
1011 regmap_reg_range(0x1400, 0x1401),
1012 regmap_reg_range(0x1403, 0x1403),
1013 regmap_reg_range(0x1410, 0x1417),
1014 regmap_reg_range(0x1420, 0x1423),
1015 regmap_reg_range(0x1500, 0x1507),
1016 regmap_reg_range(0x1600, 0x1613),
1017 regmap_reg_range(0x1800, 0x180f),
1018 regmap_reg_range(0x1820, 0x1827),
1019 regmap_reg_range(0x1830, 0x1837),
1020 regmap_reg_range(0x1840, 0x184b),
1021 regmap_reg_range(0x1900, 0x1907),
1022 regmap_reg_range(0x1914, 0x191b),
1023 regmap_reg_range(0x1920, 0x1920),
1024 regmap_reg_range(0x1923, 0x1927),
1025 regmap_reg_range(0x1a00, 0x1a03),
1026 regmap_reg_range(0x1a04, 0x1a07),
1027 regmap_reg_range(0x1b00, 0x1b01),
1028 regmap_reg_range(0x1b04, 0x1b04),
1029 regmap_reg_range(0x1c00, 0x1c05),
1030 regmap_reg_range(0x1c08, 0x1c1b),
1031
1032 /* port 2 */
1033 regmap_reg_range(0x2000, 0x2001),
1034 regmap_reg_range(0x2013, 0x2013),
1035 regmap_reg_range(0x2017, 0x2017),
1036 regmap_reg_range(0x201b, 0x201b),
1037 regmap_reg_range(0x201f, 0x2020),
1038 regmap_reg_range(0x2030, 0x2030),
1039 regmap_reg_range(0x2100, 0x2115),
1040 regmap_reg_range(0x211a, 0x211f),
1041 regmap_reg_range(0x2120, 0x212b),
1042 regmap_reg_range(0x2134, 0x213b),
1043 regmap_reg_range(0x213c, 0x213f),
1044 regmap_reg_range(0x2400, 0x2401),
1045 regmap_reg_range(0x2403, 0x2403),
1046 regmap_reg_range(0x2410, 0x2417),
1047 regmap_reg_range(0x2420, 0x2423),
1048 regmap_reg_range(0x2500, 0x2507),
1049 regmap_reg_range(0x2600, 0x2613),
1050 regmap_reg_range(0x2800, 0x280f),
1051 regmap_reg_range(0x2820, 0x2827),
1052 regmap_reg_range(0x2830, 0x2837),
1053 regmap_reg_range(0x2840, 0x284b),
1054 regmap_reg_range(0x2900, 0x2907),
1055 regmap_reg_range(0x2914, 0x291b),
1056 regmap_reg_range(0x2920, 0x2920),
1057 regmap_reg_range(0x2923, 0x2927),
1058 regmap_reg_range(0x2a00, 0x2a03),
1059 regmap_reg_range(0x2a04, 0x2a07),
1060 regmap_reg_range(0x2b00, 0x2b01),
1061 regmap_reg_range(0x2b04, 0x2b04),
1062 regmap_reg_range(0x2c00, 0x2c05),
1063 regmap_reg_range(0x2c08, 0x2c1b),
1064
1065 /* port 3 */
1066 regmap_reg_range(0x3000, 0x3001),
1067 regmap_reg_range(0x3013, 0x3013),
1068 regmap_reg_range(0x3017, 0x3017),
1069 regmap_reg_range(0x301b, 0x301b),
1070 regmap_reg_range(0x301f, 0x3020),
1071 regmap_reg_range(0x3030, 0x3030),
1072 regmap_reg_range(0x3100, 0x3115),
1073 regmap_reg_range(0x311a, 0x311f),
1074 regmap_reg_range(0x3120, 0x312b),
1075 regmap_reg_range(0x3134, 0x313b),
1076 regmap_reg_range(0x313c, 0x313f),
1077 regmap_reg_range(0x3400, 0x3401),
1078 regmap_reg_range(0x3403, 0x3403),
1079 regmap_reg_range(0x3410, 0x3417),
1080 regmap_reg_range(0x3420, 0x3423),
1081 regmap_reg_range(0x3500, 0x3507),
1082 regmap_reg_range(0x3600, 0x3613),
1083 regmap_reg_range(0x3800, 0x380f),
1084 regmap_reg_range(0x3820, 0x3827),
1085 regmap_reg_range(0x3830, 0x3837),
1086 regmap_reg_range(0x3840, 0x384b),
1087 regmap_reg_range(0x3900, 0x3907),
1088 regmap_reg_range(0x3914, 0x391b),
1089 regmap_reg_range(0x3920, 0x3920),
1090 regmap_reg_range(0x3923, 0x3927),
1091 regmap_reg_range(0x3a00, 0x3a03),
1092 regmap_reg_range(0x3a04, 0x3a07),
1093 regmap_reg_range(0x3b00, 0x3b01),
1094 regmap_reg_range(0x3b04, 0x3b04),
1095 regmap_reg_range(0x3c00, 0x3c05),
1096 regmap_reg_range(0x3c08, 0x3c1b),
1097
1098 /* port 4 */
1099 regmap_reg_range(0x4000, 0x4001),
1100 regmap_reg_range(0x4013, 0x4013),
1101 regmap_reg_range(0x4017, 0x4017),
1102 regmap_reg_range(0x401b, 0x401b),
1103 regmap_reg_range(0x401f, 0x4020),
1104 regmap_reg_range(0x4030, 0x4030),
1105 regmap_reg_range(0x4100, 0x4115),
1106 regmap_reg_range(0x411a, 0x411f),
1107 regmap_reg_range(0x4120, 0x412b),
1108 regmap_reg_range(0x4134, 0x413b),
1109 regmap_reg_range(0x413c, 0x413f),
1110 regmap_reg_range(0x4400, 0x4401),
1111 regmap_reg_range(0x4403, 0x4403),
1112 regmap_reg_range(0x4410, 0x4417),
1113 regmap_reg_range(0x4420, 0x4423),
1114 regmap_reg_range(0x4500, 0x4507),
1115 regmap_reg_range(0x4600, 0x4613),
1116 regmap_reg_range(0x4800, 0x480f),
1117 regmap_reg_range(0x4820, 0x4827),
1118 regmap_reg_range(0x4830, 0x4837),
1119 regmap_reg_range(0x4840, 0x484b),
1120 regmap_reg_range(0x4900, 0x4907),
1121 regmap_reg_range(0x4914, 0x491b),
1122 regmap_reg_range(0x4920, 0x4920),
1123 regmap_reg_range(0x4923, 0x4927),
1124 regmap_reg_range(0x4a00, 0x4a03),
1125 regmap_reg_range(0x4a04, 0x4a07),
1126 regmap_reg_range(0x4b00, 0x4b01),
1127 regmap_reg_range(0x4b04, 0x4b04),
1128 regmap_reg_range(0x4c00, 0x4c05),
1129 regmap_reg_range(0x4c08, 0x4c1b),
1130
1131 /* port 5 */
1132 regmap_reg_range(0x5000, 0x5001),
1133 regmap_reg_range(0x5013, 0x5013),
1134 regmap_reg_range(0x5017, 0x5017),
1135 regmap_reg_range(0x501b, 0x501b),
1136 regmap_reg_range(0x501f, 0x5020),
1137 regmap_reg_range(0x5030, 0x5030),
1138 regmap_reg_range(0x5100, 0x5115),
1139 regmap_reg_range(0x511a, 0x511f),
1140 regmap_reg_range(0x5120, 0x512b),
1141 regmap_reg_range(0x5134, 0x513b),
1142 regmap_reg_range(0x513c, 0x513f),
1143 regmap_reg_range(0x5400, 0x5401),
1144 regmap_reg_range(0x5403, 0x5403),
1145 regmap_reg_range(0x5410, 0x5417),
1146 regmap_reg_range(0x5420, 0x5423),
1147 regmap_reg_range(0x5500, 0x5507),
1148 regmap_reg_range(0x5600, 0x5613),
1149 regmap_reg_range(0x5800, 0x580f),
1150 regmap_reg_range(0x5820, 0x5827),
1151 regmap_reg_range(0x5830, 0x5837),
1152 regmap_reg_range(0x5840, 0x584b),
1153 regmap_reg_range(0x5900, 0x5907),
1154 regmap_reg_range(0x5914, 0x591b),
1155 regmap_reg_range(0x5920, 0x5920),
1156 regmap_reg_range(0x5923, 0x5927),
1157 regmap_reg_range(0x5a00, 0x5a03),
1158 regmap_reg_range(0x5a04, 0x5a07),
1159 regmap_reg_range(0x5b00, 0x5b01),
1160 regmap_reg_range(0x5b04, 0x5b04),
1161 regmap_reg_range(0x5c00, 0x5c05),
1162 regmap_reg_range(0x5c08, 0x5c1b),
1163
1164 /* port 6 */
1165 regmap_reg_range(0x6000, 0x6001),
1166 regmap_reg_range(0x6013, 0x6013),
1167 regmap_reg_range(0x6017, 0x6017),
1168 regmap_reg_range(0x601b, 0x601b),
1169 regmap_reg_range(0x601f, 0x6020),
1170 regmap_reg_range(0x6030, 0x6030),
1171 regmap_reg_range(0x6300, 0x6301),
1172 regmap_reg_range(0x6400, 0x6401),
1173 regmap_reg_range(0x6403, 0x6403),
1174 regmap_reg_range(0x6410, 0x6417),
1175 regmap_reg_range(0x6420, 0x6423),
1176 regmap_reg_range(0x6500, 0x6507),
1177 regmap_reg_range(0x6600, 0x6613),
1178 regmap_reg_range(0x6800, 0x680f),
1179 regmap_reg_range(0x6820, 0x6827),
1180 regmap_reg_range(0x6830, 0x6837),
1181 regmap_reg_range(0x6840, 0x684b),
1182 regmap_reg_range(0x6900, 0x6907),
1183 regmap_reg_range(0x6914, 0x691b),
1184 regmap_reg_range(0x6920, 0x6920),
1185 regmap_reg_range(0x6923, 0x6927),
1186 regmap_reg_range(0x6a00, 0x6a03),
1187 regmap_reg_range(0x6a04, 0x6a07),
1188 regmap_reg_range(0x6b00, 0x6b01),
1189 regmap_reg_range(0x6b04, 0x6b04),
1190 regmap_reg_range(0x6c00, 0x6c05),
1191 regmap_reg_range(0x6c08, 0x6c1b),
1192
1193 /* port 7 */
1194 regmap_reg_range(0x7000, 0x7001),
1195 regmap_reg_range(0x7013, 0x7013),
1196 regmap_reg_range(0x7017, 0x7017),
1197 regmap_reg_range(0x701b, 0x701b),
1198 regmap_reg_range(0x701f, 0x7020),
1199 regmap_reg_range(0x7030, 0x7030),
1200 regmap_reg_range(0x7200, 0x7207),
1201 regmap_reg_range(0x7300, 0x7301),
1202 regmap_reg_range(0x7400, 0x7401),
1203 regmap_reg_range(0x7403, 0x7403),
1204 regmap_reg_range(0x7410, 0x7417),
1205 regmap_reg_range(0x7420, 0x7423),
1206 regmap_reg_range(0x7500, 0x7507),
1207 regmap_reg_range(0x7600, 0x7613),
1208 regmap_reg_range(0x7800, 0x780f),
1209 regmap_reg_range(0x7820, 0x7827),
1210 regmap_reg_range(0x7830, 0x7837),
1211 regmap_reg_range(0x7840, 0x784b),
1212 regmap_reg_range(0x7900, 0x7907),
1213 regmap_reg_range(0x7914, 0x791b),
1214 regmap_reg_range(0x7920, 0x7920),
1215 regmap_reg_range(0x7923, 0x7927),
1216 regmap_reg_range(0x7a00, 0x7a03),
1217 regmap_reg_range(0x7a04, 0x7a07),
1218 regmap_reg_range(0x7b00, 0x7b01),
1219 regmap_reg_range(0x7b04, 0x7b04),
1220 regmap_reg_range(0x7c00, 0x7c05),
1221 regmap_reg_range(0x7c08, 0x7c1b),
1222 };
1223
1224 static const struct regmap_access_table ksz9477_register_set = {
1225 .yes_ranges = ksz9477_valid_regs,
1226 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1227 };
1228
1229 static const struct regmap_range ksz9896_valid_regs[] = {
1230 regmap_reg_range(0x0000, 0x0003),
1231 regmap_reg_range(0x0006, 0x0006),
1232 regmap_reg_range(0x0010, 0x001f),
1233 regmap_reg_range(0x0100, 0x0100),
1234 regmap_reg_range(0x0103, 0x0107),
1235 regmap_reg_range(0x010d, 0x010d),
1236 regmap_reg_range(0x0110, 0x0113),
1237 regmap_reg_range(0x0120, 0x0127),
1238 regmap_reg_range(0x0201, 0x0201),
1239 regmap_reg_range(0x0210, 0x0213),
1240 regmap_reg_range(0x0300, 0x0300),
1241 regmap_reg_range(0x0302, 0x030b),
1242 regmap_reg_range(0x0310, 0x031b),
1243 regmap_reg_range(0x0320, 0x032b),
1244 regmap_reg_range(0x0330, 0x0336),
1245 regmap_reg_range(0x0338, 0x033b),
1246 regmap_reg_range(0x033e, 0x033e),
1247 regmap_reg_range(0x0340, 0x035f),
1248 regmap_reg_range(0x0370, 0x0370),
1249 regmap_reg_range(0x0378, 0x0378),
1250 regmap_reg_range(0x037c, 0x037d),
1251 regmap_reg_range(0x0390, 0x0393),
1252 regmap_reg_range(0x0400, 0x040e),
1253 regmap_reg_range(0x0410, 0x042f),
1254
1255 /* port 1 */
1256 regmap_reg_range(0x1000, 0x1001),
1257 regmap_reg_range(0x1013, 0x1013),
1258 regmap_reg_range(0x1017, 0x1017),
1259 regmap_reg_range(0x101b, 0x101b),
1260 regmap_reg_range(0x101f, 0x1020),
1261 regmap_reg_range(0x1030, 0x1030),
1262 regmap_reg_range(0x1100, 0x1115),
1263 regmap_reg_range(0x111a, 0x111f),
1264 regmap_reg_range(0x1120, 0x112b),
1265 regmap_reg_range(0x1134, 0x113b),
1266 regmap_reg_range(0x113c, 0x113f),
1267 regmap_reg_range(0x1400, 0x1401),
1268 regmap_reg_range(0x1403, 0x1403),
1269 regmap_reg_range(0x1410, 0x1417),
1270 regmap_reg_range(0x1420, 0x1423),
1271 regmap_reg_range(0x1500, 0x1507),
1272 regmap_reg_range(0x1600, 0x1612),
1273 regmap_reg_range(0x1800, 0x180f),
1274 regmap_reg_range(0x1820, 0x1827),
1275 regmap_reg_range(0x1830, 0x1837),
1276 regmap_reg_range(0x1840, 0x184b),
1277 regmap_reg_range(0x1900, 0x1907),
1278 regmap_reg_range(0x1914, 0x1915),
1279 regmap_reg_range(0x1a00, 0x1a03),
1280 regmap_reg_range(0x1a04, 0x1a07),
1281 regmap_reg_range(0x1b00, 0x1b01),
1282 regmap_reg_range(0x1b04, 0x1b04),
1283
1284 /* port 2 */
1285 regmap_reg_range(0x2000, 0x2001),
1286 regmap_reg_range(0x2013, 0x2013),
1287 regmap_reg_range(0x2017, 0x2017),
1288 regmap_reg_range(0x201b, 0x201b),
1289 regmap_reg_range(0x201f, 0x2020),
1290 regmap_reg_range(0x2030, 0x2030),
1291 regmap_reg_range(0x2100, 0x2115),
1292 regmap_reg_range(0x211a, 0x211f),
1293 regmap_reg_range(0x2120, 0x212b),
1294 regmap_reg_range(0x2134, 0x213b),
1295 regmap_reg_range(0x213c, 0x213f),
1296 regmap_reg_range(0x2400, 0x2401),
1297 regmap_reg_range(0x2403, 0x2403),
1298 regmap_reg_range(0x2410, 0x2417),
1299 regmap_reg_range(0x2420, 0x2423),
1300 regmap_reg_range(0x2500, 0x2507),
1301 regmap_reg_range(0x2600, 0x2612),
1302 regmap_reg_range(0x2800, 0x280f),
1303 regmap_reg_range(0x2820, 0x2827),
1304 regmap_reg_range(0x2830, 0x2837),
1305 regmap_reg_range(0x2840, 0x284b),
1306 regmap_reg_range(0x2900, 0x2907),
1307 regmap_reg_range(0x2914, 0x2915),
1308 regmap_reg_range(0x2a00, 0x2a03),
1309 regmap_reg_range(0x2a04, 0x2a07),
1310 regmap_reg_range(0x2b00, 0x2b01),
1311 regmap_reg_range(0x2b04, 0x2b04),
1312
1313 /* port 3 */
1314 regmap_reg_range(0x3000, 0x3001),
1315 regmap_reg_range(0x3013, 0x3013),
1316 regmap_reg_range(0x3017, 0x3017),
1317 regmap_reg_range(0x301b, 0x301b),
1318 regmap_reg_range(0x301f, 0x3020),
1319 regmap_reg_range(0x3030, 0x3030),
1320 regmap_reg_range(0x3100, 0x3115),
1321 regmap_reg_range(0x311a, 0x311f),
1322 regmap_reg_range(0x3120, 0x312b),
1323 regmap_reg_range(0x3134, 0x313b),
1324 regmap_reg_range(0x313c, 0x313f),
1325 regmap_reg_range(0x3400, 0x3401),
1326 regmap_reg_range(0x3403, 0x3403),
1327 regmap_reg_range(0x3410, 0x3417),
1328 regmap_reg_range(0x3420, 0x3423),
1329 regmap_reg_range(0x3500, 0x3507),
1330 regmap_reg_range(0x3600, 0x3612),
1331 regmap_reg_range(0x3800, 0x380f),
1332 regmap_reg_range(0x3820, 0x3827),
1333 regmap_reg_range(0x3830, 0x3837),
1334 regmap_reg_range(0x3840, 0x384b),
1335 regmap_reg_range(0x3900, 0x3907),
1336 regmap_reg_range(0x3914, 0x3915),
1337 regmap_reg_range(0x3a00, 0x3a03),
1338 regmap_reg_range(0x3a04, 0x3a07),
1339 regmap_reg_range(0x3b00, 0x3b01),
1340 regmap_reg_range(0x3b04, 0x3b04),
1341
1342 /* port 4 */
1343 regmap_reg_range(0x4000, 0x4001),
1344 regmap_reg_range(0x4013, 0x4013),
1345 regmap_reg_range(0x4017, 0x4017),
1346 regmap_reg_range(0x401b, 0x401b),
1347 regmap_reg_range(0x401f, 0x4020),
1348 regmap_reg_range(0x4030, 0x4030),
1349 regmap_reg_range(0x4100, 0x4115),
1350 regmap_reg_range(0x411a, 0x411f),
1351 regmap_reg_range(0x4120, 0x412b),
1352 regmap_reg_range(0x4134, 0x413b),
1353 regmap_reg_range(0x413c, 0x413f),
1354 regmap_reg_range(0x4400, 0x4401),
1355 regmap_reg_range(0x4403, 0x4403),
1356 regmap_reg_range(0x4410, 0x4417),
1357 regmap_reg_range(0x4420, 0x4423),
1358 regmap_reg_range(0x4500, 0x4507),
1359 regmap_reg_range(0x4600, 0x4612),
1360 regmap_reg_range(0x4800, 0x480f),
1361 regmap_reg_range(0x4820, 0x4827),
1362 regmap_reg_range(0x4830, 0x4837),
1363 regmap_reg_range(0x4840, 0x484b),
1364 regmap_reg_range(0x4900, 0x4907),
1365 regmap_reg_range(0x4914, 0x4915),
1366 regmap_reg_range(0x4a00, 0x4a03),
1367 regmap_reg_range(0x4a04, 0x4a07),
1368 regmap_reg_range(0x4b00, 0x4b01),
1369 regmap_reg_range(0x4b04, 0x4b04),
1370
1371 /* port 5 */
1372 regmap_reg_range(0x5000, 0x5001),
1373 regmap_reg_range(0x5013, 0x5013),
1374 regmap_reg_range(0x5017, 0x5017),
1375 regmap_reg_range(0x501b, 0x501b),
1376 regmap_reg_range(0x501f, 0x5020),
1377 regmap_reg_range(0x5030, 0x5030),
1378 regmap_reg_range(0x5100, 0x5115),
1379 regmap_reg_range(0x511a, 0x511f),
1380 regmap_reg_range(0x5120, 0x512b),
1381 regmap_reg_range(0x5134, 0x513b),
1382 regmap_reg_range(0x513c, 0x513f),
1383 regmap_reg_range(0x5400, 0x5401),
1384 regmap_reg_range(0x5403, 0x5403),
1385 regmap_reg_range(0x5410, 0x5417),
1386 regmap_reg_range(0x5420, 0x5423),
1387 regmap_reg_range(0x5500, 0x5507),
1388 regmap_reg_range(0x5600, 0x5612),
1389 regmap_reg_range(0x5800, 0x580f),
1390 regmap_reg_range(0x5820, 0x5827),
1391 regmap_reg_range(0x5830, 0x5837),
1392 regmap_reg_range(0x5840, 0x584b),
1393 regmap_reg_range(0x5900, 0x5907),
1394 regmap_reg_range(0x5914, 0x5915),
1395 regmap_reg_range(0x5a00, 0x5a03),
1396 regmap_reg_range(0x5a04, 0x5a07),
1397 regmap_reg_range(0x5b00, 0x5b01),
1398 regmap_reg_range(0x5b04, 0x5b04),
1399
1400 /* port 6 */
1401 regmap_reg_range(0x6000, 0x6001),
1402 regmap_reg_range(0x6013, 0x6013),
1403 regmap_reg_range(0x6017, 0x6017),
1404 regmap_reg_range(0x601b, 0x601b),
1405 regmap_reg_range(0x601f, 0x6020),
1406 regmap_reg_range(0x6030, 0x6030),
1407 regmap_reg_range(0x6100, 0x6115),
1408 regmap_reg_range(0x611a, 0x611f),
1409 regmap_reg_range(0x6120, 0x612b),
1410 regmap_reg_range(0x6134, 0x613b),
1411 regmap_reg_range(0x613c, 0x613f),
1412 regmap_reg_range(0x6300, 0x6301),
1413 regmap_reg_range(0x6400, 0x6401),
1414 regmap_reg_range(0x6403, 0x6403),
1415 regmap_reg_range(0x6410, 0x6417),
1416 regmap_reg_range(0x6420, 0x6423),
1417 regmap_reg_range(0x6500, 0x6507),
1418 regmap_reg_range(0x6600, 0x6612),
1419 regmap_reg_range(0x6800, 0x680f),
1420 regmap_reg_range(0x6820, 0x6827),
1421 regmap_reg_range(0x6830, 0x6837),
1422 regmap_reg_range(0x6840, 0x684b),
1423 regmap_reg_range(0x6900, 0x6907),
1424 regmap_reg_range(0x6914, 0x6915),
1425 regmap_reg_range(0x6a00, 0x6a03),
1426 regmap_reg_range(0x6a04, 0x6a07),
1427 regmap_reg_range(0x6b00, 0x6b01),
1428 regmap_reg_range(0x6b04, 0x6b04),
1429 };
1430
1431 static const struct regmap_access_table ksz9896_register_set = {
1432 .yes_ranges = ksz9896_valid_regs,
1433 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1434 };
1435
1436 static const struct regmap_range ksz8873_valid_regs[] = {
1437 regmap_reg_range(0x00, 0x01),
1438 /* global control register */
1439 regmap_reg_range(0x02, 0x0f),
1440
1441 /* port registers */
1442 regmap_reg_range(0x10, 0x1d),
1443 regmap_reg_range(0x1e, 0x1f),
1444 regmap_reg_range(0x20, 0x2d),
1445 regmap_reg_range(0x2e, 0x2f),
1446 regmap_reg_range(0x30, 0x39),
1447 regmap_reg_range(0x3f, 0x3f),
1448
1449 /* advanced control registers */
1450 regmap_reg_range(0x43, 0x43),
1451 regmap_reg_range(0x60, 0x6f),
1452 regmap_reg_range(0x70, 0x75),
1453 regmap_reg_range(0x76, 0x78),
1454 regmap_reg_range(0x79, 0x7a),
1455 regmap_reg_range(0x7b, 0x83),
1456 regmap_reg_range(0x8e, 0x99),
1457 regmap_reg_range(0x9a, 0xa5),
1458 regmap_reg_range(0xa6, 0xa6),
1459 regmap_reg_range(0xa7, 0xaa),
1460 regmap_reg_range(0xab, 0xae),
1461 regmap_reg_range(0xaf, 0xba),
1462 regmap_reg_range(0xbb, 0xbc),
1463 regmap_reg_range(0xbd, 0xbd),
1464 regmap_reg_range(0xc0, 0xc0),
1465 regmap_reg_range(0xc2, 0xc2),
1466 regmap_reg_range(0xc3, 0xc3),
1467 regmap_reg_range(0xc4, 0xc4),
1468 regmap_reg_range(0xc6, 0xc6),
1469 };
1470
1471 static const struct regmap_access_table ksz8873_register_set = {
1472 .yes_ranges = ksz8873_valid_regs,
1473 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1474 };
1475
1476 const struct ksz_chip_data ksz_switch_chips[] = {
1477 [KSZ8463] = {
1478 .chip_id = KSZ8463_CHIP_ID,
1479 .dev_name = "KSZ8463",
1480 .num_vlans = 16,
1481 .num_alus = 0,
1482 .num_statics = 8,
1483 .cpu_ports = 0x4, /* can be configured as cpu port */
1484 .port_cnt = 3,
1485 .num_tx_queues = 4,
1486 .num_ipms = 4,
1487 .ops = &ksz8463_dev_ops,
1488 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1489 .mib_names = ksz88xx_mib_names,
1490 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1491 .reg_mib_cnt = MIB_COUNTER_NUM,
1492 .regs = ksz8463_regs,
1493 .masks = ksz8463_masks,
1494 .shifts = ksz8463_shifts,
1495 .supports_mii = {false, false, true},
1496 .supports_rmii = {false, false, true},
1497 .internal_phy = {true, true, false},
1498 },
1499
1500 [KSZ8563] = {
1501 .chip_id = KSZ8563_CHIP_ID,
1502 .dev_name = "KSZ8563",
1503 .num_vlans = 4096,
1504 .num_alus = 4096,
1505 .num_statics = 16,
1506 .cpu_ports = 0x07, /* can be configured as cpu port */
1507 .port_cnt = 3, /* total port count */
1508 .port_nirqs = 3,
1509 .num_tx_queues = 4,
1510 .num_ipms = 8,
1511 .tc_cbs_supported = true,
1512 .ops = &ksz9477_dev_ops,
1513 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1514 .mib_names = ksz9477_mib_names,
1515 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1516 .reg_mib_cnt = MIB_COUNTER_NUM,
1517 .regs = ksz9477_regs,
1518 .masks = ksz9477_masks,
1519 .shifts = ksz9477_shifts,
1520 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1521 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1522 .supports_mii = {false, false, true},
1523 .supports_rmii = {false, false, true},
1524 .supports_rgmii = {false, false, true},
1525 .internal_phy = {true, true, false},
1526 .gbit_capable = {false, false, true},
1527 .ptp_capable = true,
1528 .wr_table = &ksz8563_register_set,
1529 .rd_table = &ksz8563_register_set,
1530 },
1531
1532 [KSZ8795] = {
1533 .chip_id = KSZ8795_CHIP_ID,
1534 .dev_name = "KSZ8795",
1535 .num_vlans = 4096,
1536 .num_alus = 0,
1537 .num_statics = 32,
1538 .cpu_ports = 0x10, /* can be configured as cpu port */
1539 .port_cnt = 5, /* total cpu and user ports */
1540 .num_tx_queues = 4,
1541 .num_ipms = 4,
1542 .ops = &ksz87xx_dev_ops,
1543 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1544 .ksz87xx_eee_link_erratum = true,
1545 .mib_names = ksz9477_mib_names,
1546 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1547 .reg_mib_cnt = MIB_COUNTER_NUM,
1548 .regs = ksz8795_regs,
1549 .masks = ksz8795_masks,
1550 .shifts = ksz8795_shifts,
1551 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1552 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1553 .supports_mii = {false, false, false, false, true},
1554 .supports_rmii = {false, false, false, false, true},
1555 .supports_rgmii = {false, false, false, false, true},
1556 .internal_phy = {true, true, true, true, false},
1557 },
1558
1559 [KSZ8794] = {
1560 /* WARNING
1561 * =======
1562 * KSZ8794 is similar to KSZ8795, except the port map
1563 * contains a gap between external and CPU ports, the
1564 * port map is NOT continuous. The per-port register
1565 * map is shifted accordingly too, i.e. registers at
1566 * offset 0x40 are NOT used on KSZ8794 and they ARE
1567 * used on KSZ8795 for external port 3.
1568 * external cpu
1569 * KSZ8794 0,1,2 4
1570 * KSZ8795 0,1,2,3 4
1571 * KSZ8765 0,1,2,3 4
1572 * port_cnt is configured as 5, even though it is 4
1573 */
1574 .chip_id = KSZ8794_CHIP_ID,
1575 .dev_name = "KSZ8794",
1576 .num_vlans = 4096,
1577 .num_alus = 0,
1578 .num_statics = 32,
1579 .cpu_ports = 0x10, /* can be configured as cpu port */
1580 .port_cnt = 5, /* total cpu and user ports */
1581 .num_tx_queues = 4,
1582 .num_ipms = 4,
1583 .ops = &ksz87xx_dev_ops,
1584 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1585 .ksz87xx_eee_link_erratum = true,
1586 .mib_names = ksz9477_mib_names,
1587 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1588 .reg_mib_cnt = MIB_COUNTER_NUM,
1589 .regs = ksz8795_regs,
1590 .masks = ksz8795_masks,
1591 .shifts = ksz8795_shifts,
1592 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1593 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1594 .supports_mii = {false, false, false, false, true},
1595 .supports_rmii = {false, false, false, false, true},
1596 .supports_rgmii = {false, false, false, false, true},
1597 .internal_phy = {true, true, true, false, false},
1598 },
1599
1600 [KSZ8765] = {
1601 .chip_id = KSZ8765_CHIP_ID,
1602 .dev_name = "KSZ8765",
1603 .num_vlans = 4096,
1604 .num_alus = 0,
1605 .num_statics = 32,
1606 .cpu_ports = 0x10, /* can be configured as cpu port */
1607 .port_cnt = 5, /* total cpu and user ports */
1608 .num_tx_queues = 4,
1609 .num_ipms = 4,
1610 .ops = &ksz87xx_dev_ops,
1611 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1612 .ksz87xx_eee_link_erratum = true,
1613 .mib_names = ksz9477_mib_names,
1614 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1615 .reg_mib_cnt = MIB_COUNTER_NUM,
1616 .regs = ksz8795_regs,
1617 .masks = ksz8795_masks,
1618 .shifts = ksz8795_shifts,
1619 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1620 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1621 .supports_mii = {false, false, false, false, true},
1622 .supports_rmii = {false, false, false, false, true},
1623 .supports_rgmii = {false, false, false, false, true},
1624 .internal_phy = {true, true, true, true, false},
1625 },
1626
1627 [KSZ88X3] = {
1628 .chip_id = KSZ88X3_CHIP_ID,
1629 .dev_name = "KSZ8863/KSZ8873",
1630 .num_vlans = 16,
1631 .num_alus = 0,
1632 .num_statics = 8,
1633 .cpu_ports = 0x4, /* can be configured as cpu port */
1634 .port_cnt = 3,
1635 .num_tx_queues = 4,
1636 .num_ipms = 4,
1637 .ops = &ksz88xx_dev_ops,
1638 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1639 .mib_names = ksz88xx_mib_names,
1640 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1641 .reg_mib_cnt = MIB_COUNTER_NUM,
1642 .regs = ksz8863_regs,
1643 .masks = ksz8863_masks,
1644 .shifts = ksz8863_shifts,
1645 .supports_mii = {false, false, true},
1646 .supports_rmii = {false, false, true},
1647 .internal_phy = {true, true, false},
1648 .wr_table = &ksz8873_register_set,
1649 .rd_table = &ksz8873_register_set,
1650 },
1651
1652 [KSZ8864] = {
1653 /* WARNING
1654 * =======
1655 * KSZ8864 is similar to KSZ8895, except the first port
1656 * does not exist.
1657 * external cpu
1658 * KSZ8864 1,2,3 4
1659 * KSZ8895 0,1,2,3 4
1660 * port_cnt is configured as 5, even though it is 4
1661 */
1662 .chip_id = KSZ8864_CHIP_ID,
1663 .dev_name = "KSZ8864",
1664 .num_vlans = 4096,
1665 .num_alus = 0,
1666 .num_statics = 32,
1667 .cpu_ports = 0x10, /* can be configured as cpu port */
1668 .port_cnt = 5, /* total cpu and user ports */
1669 .num_tx_queues = 4,
1670 .num_ipms = 4,
1671 .ops = &ksz88xx_dev_ops,
1672 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1673 .mib_names = ksz88xx_mib_names,
1674 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1675 .reg_mib_cnt = MIB_COUNTER_NUM,
1676 .regs = ksz8895_regs,
1677 .masks = ksz8895_masks,
1678 .shifts = ksz8895_shifts,
1679 .supports_mii = {false, false, false, false, true},
1680 .supports_rmii = {false, false, false, false, true},
1681 .internal_phy = {false, true, true, true, false},
1682 },
1683
1684 [KSZ8895] = {
1685 .chip_id = KSZ8895_CHIP_ID,
1686 .dev_name = "KSZ8895",
1687 .num_vlans = 4096,
1688 .num_alus = 0,
1689 .num_statics = 32,
1690 .cpu_ports = 0x10, /* can be configured as cpu port */
1691 .port_cnt = 5, /* total cpu and user ports */
1692 .num_tx_queues = 4,
1693 .num_ipms = 4,
1694 .ops = &ksz88xx_dev_ops,
1695 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1696 .mib_names = ksz88xx_mib_names,
1697 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1698 .reg_mib_cnt = MIB_COUNTER_NUM,
1699 .regs = ksz8895_regs,
1700 .masks = ksz8895_masks,
1701 .shifts = ksz8895_shifts,
1702 .supports_mii = {false, false, false, false, true},
1703 .supports_rmii = {false, false, false, false, true},
1704 .internal_phy = {true, true, true, true, false},
1705 },
1706
1707 [KSZ9477] = {
1708 .chip_id = KSZ9477_CHIP_ID,
1709 .dev_name = "KSZ9477",
1710 .num_vlans = 4096,
1711 .num_alus = 4096,
1712 .num_statics = 16,
1713 .cpu_ports = 0x7F, /* can be configured as cpu port */
1714 .port_cnt = 7, /* total physical port count */
1715 .port_nirqs = 4,
1716 .num_tx_queues = 4,
1717 .num_ipms = 8,
1718 .tc_cbs_supported = true,
1719 .ops = &ksz9477_dev_ops,
1720 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1721 .phy_errata_9477 = true,
1722 .mib_names = ksz9477_mib_names,
1723 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1724 .reg_mib_cnt = MIB_COUNTER_NUM,
1725 .regs = ksz9477_regs,
1726 .masks = ksz9477_masks,
1727 .shifts = ksz9477_shifts,
1728 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1729 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1730 .supports_mii = {false, false, false, false,
1731 false, true, false},
1732 .supports_rmii = {false, false, false, false,
1733 false, true, false},
1734 .supports_rgmii = {false, false, false, false,
1735 false, true, false},
1736 .internal_phy = {true, true, true, true,
1737 true, false, false},
1738 .gbit_capable = {true, true, true, true, true, true, true},
1739 .ptp_capable = true,
1740 .sgmii_port = 7,
1741 .wr_table = &ksz9477_register_set,
1742 .rd_table = &ksz9477_register_set,
1743 },
1744
1745 [KSZ9896] = {
1746 .chip_id = KSZ9896_CHIP_ID,
1747 .dev_name = "KSZ9896",
1748 .num_vlans = 4096,
1749 .num_alus = 4096,
1750 .num_statics = 16,
1751 .cpu_ports = 0x3F, /* can be configured as cpu port */
1752 .port_cnt = 6, /* total physical port count */
1753 .port_nirqs = 2,
1754 .num_tx_queues = 4,
1755 .num_ipms = 8,
1756 .ops = &ksz9477_dev_ops,
1757 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1758 .phy_errata_9477 = true,
1759 .mib_names = ksz9477_mib_names,
1760 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1761 .reg_mib_cnt = MIB_COUNTER_NUM,
1762 .regs = ksz9477_regs,
1763 .masks = ksz9477_masks,
1764 .shifts = ksz9477_shifts,
1765 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1766 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1767 .supports_mii = {false, false, false, false,
1768 false, true},
1769 .supports_rmii = {false, false, false, false,
1770 false, true},
1771 .supports_rgmii = {false, false, false, false,
1772 false, true},
1773 .internal_phy = {true, true, true, true,
1774 true, false},
1775 .gbit_capable = {true, true, true, true, true, true},
1776 .wr_table = &ksz9896_register_set,
1777 .rd_table = &ksz9896_register_set,
1778 },
1779
1780 [KSZ9897] = {
1781 .chip_id = KSZ9897_CHIP_ID,
1782 .dev_name = "KSZ9897",
1783 .num_vlans = 4096,
1784 .num_alus = 4096,
1785 .num_statics = 16,
1786 .cpu_ports = 0x7F, /* can be configured as cpu port */
1787 .port_cnt = 7, /* total physical port count */
1788 .port_nirqs = 2,
1789 .num_tx_queues = 4,
1790 .num_ipms = 8,
1791 .ops = &ksz9477_dev_ops,
1792 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1793 .phy_errata_9477 = true,
1794 .mib_names = ksz9477_mib_names,
1795 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1796 .reg_mib_cnt = MIB_COUNTER_NUM,
1797 .regs = ksz9477_regs,
1798 .masks = ksz9477_masks,
1799 .shifts = ksz9477_shifts,
1800 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1801 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1802 .supports_mii = {false, false, false, false,
1803 false, true, true},
1804 .supports_rmii = {false, false, false, false,
1805 false, true, true},
1806 .supports_rgmii = {false, false, false, false,
1807 false, true, true},
1808 .internal_phy = {true, true, true, true,
1809 true, false, false},
1810 .gbit_capable = {true, true, true, true, true, true, true},
1811 },
1812
1813 [KSZ9893] = {
1814 .chip_id = KSZ9893_CHIP_ID,
1815 .dev_name = "KSZ9893",
1816 .num_vlans = 4096,
1817 .num_alus = 4096,
1818 .num_statics = 16,
1819 .cpu_ports = 0x07, /* can be configured as cpu port */
1820 .port_cnt = 3, /* total port count */
1821 .port_nirqs = 2,
1822 .num_tx_queues = 4,
1823 .num_ipms = 8,
1824 .ops = &ksz9477_dev_ops,
1825 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1826 .mib_names = ksz9477_mib_names,
1827 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1828 .reg_mib_cnt = MIB_COUNTER_NUM,
1829 .regs = ksz9477_regs,
1830 .masks = ksz9477_masks,
1831 .shifts = ksz9477_shifts,
1832 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1833 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1834 .supports_mii = {false, false, true},
1835 .supports_rmii = {false, false, true},
1836 .supports_rgmii = {false, false, true},
1837 .internal_phy = {true, true, false},
1838 .gbit_capable = {true, true, true},
1839 },
1840
1841 [KSZ9563] = {
1842 .chip_id = KSZ9563_CHIP_ID,
1843 .dev_name = "KSZ9563",
1844 .num_vlans = 4096,
1845 .num_alus = 4096,
1846 .num_statics = 16,
1847 .cpu_ports = 0x07, /* can be configured as cpu port */
1848 .port_cnt = 3, /* total port count */
1849 .port_nirqs = 3,
1850 .num_tx_queues = 4,
1851 .num_ipms = 8,
1852 .tc_cbs_supported = true,
1853 .ops = &ksz9477_dev_ops,
1854 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1855 .mib_names = ksz9477_mib_names,
1856 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1857 .reg_mib_cnt = MIB_COUNTER_NUM,
1858 .regs = ksz9477_regs,
1859 .masks = ksz9477_masks,
1860 .shifts = ksz9477_shifts,
1861 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1862 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1863 .supports_mii = {false, false, true},
1864 .supports_rmii = {false, false, true},
1865 .supports_rgmii = {false, false, true},
1866 .internal_phy = {true, true, false},
1867 .gbit_capable = {true, true, true},
1868 .ptp_capable = true,
1869 },
1870
1871 [KSZ8567] = {
1872 .chip_id = KSZ8567_CHIP_ID,
1873 .dev_name = "KSZ8567",
1874 .num_vlans = 4096,
1875 .num_alus = 4096,
1876 .num_statics = 16,
1877 .cpu_ports = 0x7F, /* can be configured as cpu port */
1878 .port_cnt = 7, /* total port count */
1879 .port_nirqs = 3,
1880 .num_tx_queues = 4,
1881 .num_ipms = 8,
1882 .tc_cbs_supported = true,
1883 .ops = &ksz9477_dev_ops,
1884 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1885 .phy_errata_9477 = true,
1886 .mib_names = ksz9477_mib_names,
1887 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1888 .reg_mib_cnt = MIB_COUNTER_NUM,
1889 .regs = ksz9477_regs,
1890 .masks = ksz9477_masks,
1891 .shifts = ksz9477_shifts,
1892 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1893 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1894 .supports_mii = {false, false, false, false,
1895 false, true, true},
1896 .supports_rmii = {false, false, false, false,
1897 false, true, true},
1898 .supports_rgmii = {false, false, false, false,
1899 false, true, true},
1900 .internal_phy = {true, true, true, true,
1901 true, false, false},
1902 .gbit_capable = {false, false, false, false, false,
1903 true, true},
1904 .ptp_capable = true,
1905 },
1906
1907 [KSZ9567] = {
1908 .chip_id = KSZ9567_CHIP_ID,
1909 .dev_name = "KSZ9567",
1910 .num_vlans = 4096,
1911 .num_alus = 4096,
1912 .num_statics = 16,
1913 .cpu_ports = 0x7F, /* can be configured as cpu port */
1914 .port_cnt = 7, /* total physical port count */
1915 .port_nirqs = 3,
1916 .num_tx_queues = 4,
1917 .num_ipms = 8,
1918 .tc_cbs_supported = true,
1919 .ops = &ksz9477_dev_ops,
1920 .mib_names = ksz9477_mib_names,
1921 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1922 .reg_mib_cnt = MIB_COUNTER_NUM,
1923 .regs = ksz9477_regs,
1924 .masks = ksz9477_masks,
1925 .shifts = ksz9477_shifts,
1926 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1927 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1928 .supports_mii = {false, false, false, false,
1929 false, true, true},
1930 .supports_rmii = {false, false, false, false,
1931 false, true, true},
1932 .supports_rgmii = {false, false, false, false,
1933 false, true, true},
1934 .internal_phy = {true, true, true, true,
1935 true, false, false},
1936 .gbit_capable = {true, true, true, true, true, true, true},
1937 .ptp_capable = true,
1938 },
1939
1940 [LAN9370] = {
1941 .chip_id = LAN9370_CHIP_ID,
1942 .dev_name = "LAN9370",
1943 .num_vlans = 4096,
1944 .num_alus = 1024,
1945 .num_statics = 256,
1946 .cpu_ports = 0x10, /* can be configured as cpu port */
1947 .port_cnt = 5, /* total physical port count */
1948 .port_nirqs = 6,
1949 .num_tx_queues = 8,
1950 .num_ipms = 8,
1951 .tc_cbs_supported = true,
1952 .phy_side_mdio_supported = true,
1953 .ops = &lan937x_dev_ops,
1954 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1955 .mib_names = ksz9477_mib_names,
1956 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1957 .reg_mib_cnt = MIB_COUNTER_NUM,
1958 .regs = ksz9477_regs,
1959 .masks = lan937x_masks,
1960 .shifts = lan937x_shifts,
1961 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1962 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1963 .supports_mii = {false, false, false, false, true},
1964 .supports_rmii = {false, false, false, false, true},
1965 .supports_rgmii = {false, false, false, false, true},
1966 .internal_phy = {true, true, true, true, false},
1967 .ptp_capable = true,
1968 },
1969
1970 [LAN9371] = {
1971 .chip_id = LAN9371_CHIP_ID,
1972 .dev_name = "LAN9371",
1973 .num_vlans = 4096,
1974 .num_alus = 1024,
1975 .num_statics = 256,
1976 .cpu_ports = 0x30, /* can be configured as cpu port */
1977 .port_cnt = 6, /* total physical port count */
1978 .port_nirqs = 6,
1979 .num_tx_queues = 8,
1980 .num_ipms = 8,
1981 .tc_cbs_supported = true,
1982 .phy_side_mdio_supported = true,
1983 .ops = &lan937x_dev_ops,
1984 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1985 .mib_names = ksz9477_mib_names,
1986 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1987 .reg_mib_cnt = MIB_COUNTER_NUM,
1988 .regs = ksz9477_regs,
1989 .masks = lan937x_masks,
1990 .shifts = lan937x_shifts,
1991 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1992 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1993 .supports_mii = {false, false, false, false, true, true},
1994 .supports_rmii = {false, false, false, false, true, true},
1995 .supports_rgmii = {false, false, false, false, true, true},
1996 .internal_phy = {true, true, true, true, false, false},
1997 .ptp_capable = true,
1998 },
1999
2000 [LAN9372] = {
2001 .chip_id = LAN9372_CHIP_ID,
2002 .dev_name = "LAN9372",
2003 .num_vlans = 4096,
2004 .num_alus = 1024,
2005 .num_statics = 256,
2006 .cpu_ports = 0x30, /* can be configured as cpu port */
2007 .port_cnt = 8, /* total physical port count */
2008 .port_nirqs = 6,
2009 .num_tx_queues = 8,
2010 .num_ipms = 8,
2011 .tc_cbs_supported = true,
2012 .phy_side_mdio_supported = true,
2013 .ops = &lan937x_dev_ops,
2014 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2015 .mib_names = ksz9477_mib_names,
2016 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2017 .reg_mib_cnt = MIB_COUNTER_NUM,
2018 .regs = ksz9477_regs,
2019 .masks = lan937x_masks,
2020 .shifts = lan937x_shifts,
2021 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2022 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2023 .supports_mii = {false, false, false, false,
2024 true, true, false, false},
2025 .supports_rmii = {false, false, false, false,
2026 true, true, false, false},
2027 .supports_rgmii = {false, false, false, false,
2028 true, true, false, false},
2029 .internal_phy = {true, true, true, true,
2030 false, false, true, true},
2031 .ptp_capable = true,
2032 },
2033
2034 [LAN9373] = {
2035 .chip_id = LAN9373_CHIP_ID,
2036 .dev_name = "LAN9373",
2037 .num_vlans = 4096,
2038 .num_alus = 1024,
2039 .num_statics = 256,
2040 .cpu_ports = 0x38, /* can be configured as cpu port */
2041 .port_cnt = 5, /* total physical port count */
2042 .port_nirqs = 6,
2043 .num_tx_queues = 8,
2044 .num_ipms = 8,
2045 .tc_cbs_supported = true,
2046 .phy_side_mdio_supported = true,
2047 .ops = &lan937x_dev_ops,
2048 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2049 .mib_names = ksz9477_mib_names,
2050 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2051 .reg_mib_cnt = MIB_COUNTER_NUM,
2052 .regs = ksz9477_regs,
2053 .masks = lan937x_masks,
2054 .shifts = lan937x_shifts,
2055 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2056 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2057 .supports_mii = {false, false, false, false,
2058 true, true, false, false},
2059 .supports_rmii = {false, false, false, false,
2060 true, true, false, false},
2061 .supports_rgmii = {false, false, false, false,
2062 true, true, false, false},
2063 .internal_phy = {true, true, true, false,
2064 false, false, true, true},
2065 .ptp_capable = true,
2066 },
2067
2068 [LAN9374] = {
2069 .chip_id = LAN9374_CHIP_ID,
2070 .dev_name = "LAN9374",
2071 .num_vlans = 4096,
2072 .num_alus = 1024,
2073 .num_statics = 256,
2074 .cpu_ports = 0x30, /* can be configured as cpu port */
2075 .port_cnt = 8, /* total physical port count */
2076 .port_nirqs = 6,
2077 .num_tx_queues = 8,
2078 .num_ipms = 8,
2079 .tc_cbs_supported = true,
2080 .phy_side_mdio_supported = true,
2081 .ops = &lan937x_dev_ops,
2082 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2083 .mib_names = ksz9477_mib_names,
2084 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2085 .reg_mib_cnt = MIB_COUNTER_NUM,
2086 .regs = ksz9477_regs,
2087 .masks = lan937x_masks,
2088 .shifts = lan937x_shifts,
2089 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2090 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2091 .supports_mii = {false, false, false, false,
2092 true, true, false, false},
2093 .supports_rmii = {false, false, false, false,
2094 true, true, false, false},
2095 .supports_rgmii = {false, false, false, false,
2096 true, true, false, false},
2097 .internal_phy = {true, true, true, true,
2098 false, false, true, true},
2099 .ptp_capable = true,
2100 },
2101
2102 [LAN9646] = {
2103 .chip_id = LAN9646_CHIP_ID,
2104 .dev_name = "LAN9646",
2105 .num_vlans = 4096,
2106 .num_alus = 4096,
2107 .num_statics = 16,
2108 .cpu_ports = 0x7F, /* can be configured as cpu port */
2109 .port_cnt = 7, /* total physical port count */
2110 .port_nirqs = 4,
2111 .num_tx_queues = 4,
2112 .num_ipms = 8,
2113 .ops = &ksz9477_dev_ops,
2114 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
2115 .phy_errata_9477 = true,
2116 .mib_names = ksz9477_mib_names,
2117 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2118 .reg_mib_cnt = MIB_COUNTER_NUM,
2119 .regs = ksz9477_regs,
2120 .masks = ksz9477_masks,
2121 .shifts = ksz9477_shifts,
2122 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2123 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2124 .supports_mii = {false, false, false, false,
2125 false, true, true},
2126 .supports_rmii = {false, false, false, false,
2127 false, true, true},
2128 .supports_rgmii = {false, false, false, false,
2129 false, true, true},
2130 .internal_phy = {true, true, true, true,
2131 true, false, false},
2132 .gbit_capable = {true, true, true, true, true, true, true},
2133 .sgmii_port = 7,
2134 .wr_table = &ksz9477_register_set,
2135 .rd_table = &ksz9477_register_set,
2136 },
2137 };
2138 EXPORT_SYMBOL_GPL(ksz_switch_chips);
2139
ksz_lookup_info(unsigned int prod_num)2140 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
2141 {
2142 int i;
2143
2144 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
2145 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
2146
2147 if (chip->chip_id == prod_num)
2148 return chip;
2149 }
2150
2151 return NULL;
2152 }
2153
ksz_check_device_id(struct ksz_device * dev)2154 static int ksz_check_device_id(struct ksz_device *dev)
2155 {
2156 const struct ksz_chip_data *expected_chip_data;
2157 u32 expected_chip_id;
2158
2159 if (dev->pdata) {
2160 expected_chip_id = dev->pdata->chip_id;
2161 expected_chip_data = ksz_lookup_info(expected_chip_id);
2162 if (WARN_ON(!expected_chip_data))
2163 return -ENODEV;
2164 } else {
2165 expected_chip_data = of_device_get_match_data(dev->dev);
2166 expected_chip_id = expected_chip_data->chip_id;
2167 }
2168
2169 if (expected_chip_id != dev->chip_id) {
2170 dev_err(dev->dev,
2171 "Device tree specifies chip %s but found %s, please fix it!\n",
2172 expected_chip_data->dev_name, dev->info->dev_name);
2173 return -ENODEV;
2174 }
2175
2176 return 0;
2177 }
2178
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2179 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
2180 struct phylink_config *config)
2181 {
2182 struct ksz_device *dev = ds->priv;
2183
2184 if (dev->info->supports_mii[port])
2185 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
2186
2187 if (dev->info->supports_rmii[port])
2188 __set_bit(PHY_INTERFACE_MODE_RMII,
2189 config->supported_interfaces);
2190
2191 if (dev->info->supports_rgmii[port])
2192 phy_interface_set_rgmii(config->supported_interfaces);
2193
2194 if (dev->info->internal_phy[port]) {
2195 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2196 config->supported_interfaces);
2197 /* Compatibility for phylib's default interface type when the
2198 * phy-mode property is absent
2199 */
2200 __set_bit(PHY_INTERFACE_MODE_GMII,
2201 config->supported_interfaces);
2202 }
2203
2204 if (dev->dev_ops->get_caps)
2205 dev->dev_ops->get_caps(dev, port, config);
2206
2207 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) {
2208 memcpy(config->lpi_interfaces, config->supported_interfaces,
2209 sizeof(config->lpi_interfaces));
2210
2211 config->lpi_capabilities = MAC_100FD;
2212 if (dev->info->gbit_capable[port])
2213 config->lpi_capabilities |= MAC_1000FD;
2214
2215 /* EEE is fully operational */
2216 config->eee_enabled_default = true;
2217 }
2218 }
2219
ksz_r_mib_stats64(struct ksz_device * dev,int port)2220 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2221 {
2222 struct ethtool_pause_stats *pstats;
2223 struct rtnl_link_stats64 *stats;
2224 struct ksz_stats_raw *raw;
2225 struct ksz_port_mib *mib;
2226 int ret;
2227
2228 mib = &dev->ports[port].mib;
2229 stats = &mib->stats64;
2230 pstats = &mib->pause_stats;
2231 raw = (struct ksz_stats_raw *)mib->counters;
2232
2233 spin_lock(&mib->stats64_lock);
2234
2235 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2236 raw->rx_pause;
2237 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2238 raw->tx_pause;
2239
2240 /* HW counters are counting bytes + FCS which is not acceptable
2241 * for rtnl_link_stats64 interface
2242 */
2243 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2244 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2245
2246 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2247 raw->rx_oversize;
2248
2249 stats->rx_crc_errors = raw->rx_crc_err;
2250 stats->rx_frame_errors = raw->rx_align_err;
2251 stats->rx_dropped = raw->rx_discards;
2252 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2253 stats->rx_frame_errors + stats->rx_dropped;
2254
2255 stats->tx_window_errors = raw->tx_late_col;
2256 stats->tx_fifo_errors = raw->tx_discards;
2257 stats->tx_aborted_errors = raw->tx_exc_col;
2258 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2259 stats->tx_aborted_errors;
2260
2261 stats->multicast = raw->rx_mcast;
2262 stats->collisions = raw->tx_total_col;
2263
2264 pstats->tx_pause_frames = raw->tx_pause;
2265 pstats->rx_pause_frames = raw->rx_pause;
2266
2267 spin_unlock(&mib->stats64_lock);
2268
2269 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) {
2270 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col);
2271 if (ret)
2272 dev_err(dev->dev, "Failed to monitor transmission halt\n");
2273 }
2274 }
2275
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)2276 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2277 {
2278 struct ethtool_pause_stats *pstats;
2279 struct rtnl_link_stats64 *stats;
2280 struct ksz88xx_stats_raw *raw;
2281 struct ksz_port_mib *mib;
2282
2283 mib = &dev->ports[port].mib;
2284 stats = &mib->stats64;
2285 pstats = &mib->pause_stats;
2286 raw = (struct ksz88xx_stats_raw *)mib->counters;
2287
2288 spin_lock(&mib->stats64_lock);
2289
2290 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2291 raw->rx_pause;
2292 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2293 raw->tx_pause;
2294
2295 /* HW counters are counting bytes + FCS which is not acceptable
2296 * for rtnl_link_stats64 interface
2297 */
2298 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2299 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2300
2301 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2302 raw->rx_oversize;
2303
2304 stats->rx_crc_errors = raw->rx_crc_err;
2305 stats->rx_frame_errors = raw->rx_align_err;
2306 stats->rx_dropped = raw->rx_discards;
2307 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2308 stats->rx_frame_errors + stats->rx_dropped;
2309
2310 stats->tx_window_errors = raw->tx_late_col;
2311 stats->tx_fifo_errors = raw->tx_discards;
2312 stats->tx_aborted_errors = raw->tx_exc_col;
2313 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2314 stats->tx_aborted_errors;
2315
2316 stats->multicast = raw->rx_mcast;
2317 stats->collisions = raw->tx_total_col;
2318
2319 pstats->tx_pause_frames = raw->tx_pause;
2320 pstats->rx_pause_frames = raw->rx_pause;
2321
2322 spin_unlock(&mib->stats64_lock);
2323 }
2324
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)2325 static void ksz_get_stats64(struct dsa_switch *ds, int port,
2326 struct rtnl_link_stats64 *s)
2327 {
2328 struct ksz_device *dev = ds->priv;
2329 struct ksz_port_mib *mib;
2330
2331 mib = &dev->ports[port].mib;
2332
2333 spin_lock(&mib->stats64_lock);
2334 memcpy(s, &mib->stats64, sizeof(*s));
2335 spin_unlock(&mib->stats64_lock);
2336 }
2337
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)2338 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2339 struct ethtool_pause_stats *pause_stats)
2340 {
2341 struct ksz_device *dev = ds->priv;
2342 struct ksz_port_mib *mib;
2343
2344 mib = &dev->ports[port].mib;
2345
2346 spin_lock(&mib->stats64_lock);
2347 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2348 spin_unlock(&mib->stats64_lock);
2349 }
2350
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)2351 static void ksz_get_strings(struct dsa_switch *ds, int port,
2352 u32 stringset, uint8_t *buf)
2353 {
2354 struct ksz_device *dev = ds->priv;
2355 int i;
2356
2357 if (stringset != ETH_SS_STATS)
2358 return;
2359
2360 for (i = 0; i < dev->info->mib_cnt; i++)
2361 ethtool_puts(&buf, dev->info->mib_names[i].string);
2362 }
2363
2364 /**
2365 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
2366 * isolation settings.
2367 * @dev: A pointer to the struct ksz_device representing the device.
2368 * @port: The port number to adjust.
2369 *
2370 * This function dynamically adjusts the port membership configuration for a
2371 * specified port and other device ports, based on Spanning Tree Protocol (STP)
2372 * states and port isolation settings. Each port, including the CPU port, has a
2373 * membership register, represented as a bitfield, where each bit corresponds
2374 * to a port number. A set bit indicates permission to forward frames to that
2375 * port. This function iterates over all ports, updating the membership register
2376 * to reflect current forwarding permissions:
2377 *
2378 * 1. Forwards frames only to ports that are part of the same bridge group and
2379 * in the BR_STATE_FORWARDING state.
2380 * 2. Takes into account the isolation status of ports; ports in the
2381 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2382 * frames to each other, even if they are in the same bridge group.
2383 * 3. Ensures that the CPU port is included in the membership based on its
2384 * upstream port configuration, allowing for management and control traffic
2385 * to flow as required.
2386 */
ksz_update_port_member(struct ksz_device * dev,int port)2387 static void ksz_update_port_member(struct ksz_device *dev, int port)
2388 {
2389 struct ksz_port *p = &dev->ports[port];
2390 struct dsa_switch *ds = dev->ds;
2391 u8 port_member = 0, cpu_port;
2392 const struct dsa_port *dp;
2393 int i, j;
2394
2395 if (!dsa_is_user_port(ds, port))
2396 return;
2397
2398 dp = dsa_to_port(ds, port);
2399 cpu_port = BIT(dsa_upstream_port(ds, port));
2400
2401 for (i = 0; i < ds->num_ports; i++) {
2402 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2403 struct ksz_port *other_p = &dev->ports[i];
2404 u8 val = 0;
2405
2406 if (!dsa_is_user_port(ds, i))
2407 continue;
2408 if (port == i)
2409 continue;
2410 if (!dsa_port_bridge_same(dp, other_dp))
2411 continue;
2412 if (other_p->stp_state != BR_STATE_FORWARDING)
2413 continue;
2414
2415 /* At this point we know that "port" and "other" port [i] are in
2416 * the same bridge group and that "other" port [i] is in
2417 * forwarding stp state. If "port" is also in forwarding stp
2418 * state, we can allow forwarding from port [port] to port [i].
2419 * Except if both ports are isolated.
2420 */
2421 if (p->stp_state == BR_STATE_FORWARDING &&
2422 !(p->isolated && other_p->isolated)) {
2423 val |= BIT(port);
2424 port_member |= BIT(i);
2425 }
2426
2427 /* Retain port [i]'s relationship to other ports than [port] */
2428 for (j = 0; j < ds->num_ports; j++) {
2429 const struct dsa_port *third_dp;
2430 struct ksz_port *third_p;
2431
2432 if (j == i)
2433 continue;
2434 if (j == port)
2435 continue;
2436 if (!dsa_is_user_port(ds, j))
2437 continue;
2438 third_p = &dev->ports[j];
2439 if (third_p->stp_state != BR_STATE_FORWARDING)
2440 continue;
2441
2442 third_dp = dsa_to_port(ds, j);
2443
2444 /* Now we updating relation of the "other" port [i] to
2445 * the "third" port [j]. We already know that "other"
2446 * port [i] is in forwarding stp state and that "third"
2447 * port [j] is in forwarding stp state too.
2448 * We need to check if "other" port [i] and "third" port
2449 * [j] are in the same bridge group and not isolated
2450 * before allowing forwarding from port [i] to port [j].
2451 */
2452 if (dsa_port_bridge_same(other_dp, third_dp) &&
2453 !(other_p->isolated && third_p->isolated))
2454 val |= BIT(j);
2455 }
2456
2457 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2458 }
2459
2460 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2461 }
2462
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)2463 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2464 {
2465 struct ksz_device *dev = bus->priv;
2466 u16 val;
2467 int ret;
2468
2469 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2470 if (ret < 0)
2471 return ret;
2472
2473 return val;
2474 }
2475
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2476 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2477 u16 val)
2478 {
2479 struct ksz_device *dev = bus->priv;
2480
2481 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2482 }
2483
2484 /**
2485 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2486 * @bus: MDIO bus structure.
2487 * @addr: PHY address on the parent MDIO bus.
2488 * @regnum: Register number to read.
2489 *
2490 * This function provides a direct read operation on the parent MDIO bus for
2491 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2492 * to retrieve data from the PHY registers at the specified address and register
2493 * number.
2494 *
2495 * Return: Value of the PHY register, or a negative error code on failure.
2496 */
ksz_parent_mdio_read(struct mii_bus * bus,int addr,int regnum)2497 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2498 {
2499 struct ksz_device *dev = bus->priv;
2500
2501 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum);
2502 }
2503
2504 /**
2505 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2506 * @bus: MDIO bus structure.
2507 * @addr: PHY address on the parent MDIO bus.
2508 * @regnum: Register number to write to.
2509 * @val: Value to write to the PHY register.
2510 *
2511 * This function provides a direct write operation on the parent MDIO bus for
2512 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2513 * to modify the PHY register values at the specified address.
2514 *
2515 * Return: 0 on success, or a negative error code on failure.
2516 */
ksz_parent_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2517 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2518 u16 val)
2519 {
2520 struct ksz_device *dev = bus->priv;
2521
2522 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val);
2523 }
2524
2525 /**
2526 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2527 * @dev: Pointer to device structure.
2528 * @addr: PHY address to map to a port.
2529 *
2530 * This function finds the corresponding switch port for a given PHY address by
2531 * iterating over all user ports on the device. It checks if a port's PHY
2532 * address in `phy_addr_map` matches the specified address and if the port
2533 * contains an internal PHY. If a match is found, the index of the port is
2534 * returned.
2535 *
2536 * Return: Port index on success, or -EINVAL if no matching port is found.
2537 */
ksz_phy_addr_to_port(struct ksz_device * dev,int addr)2538 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2539 {
2540 struct dsa_switch *ds = dev->ds;
2541 struct dsa_port *dp;
2542
2543 dsa_switch_for_each_user_port(dp, ds) {
2544 if (dev->info->internal_phy[dp->index] &&
2545 dev->phy_addr_map[dp->index] == addr)
2546 return dp->index;
2547 }
2548
2549 return -EINVAL;
2550 }
2551
2552 /**
2553 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2554 * @dev: Pointer to the KSZ device structure.
2555 *
2556 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2557 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2558 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2559 *
2560 * Return: 0 on success, or a negative error code on failure.
2561 */
ksz_irq_phy_setup(struct ksz_device * dev)2562 static int ksz_irq_phy_setup(struct ksz_device *dev)
2563 {
2564 struct dsa_switch *ds = dev->ds;
2565 int phy, port;
2566 int irq;
2567 int ret;
2568
2569 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2570 if (BIT(phy) & ds->phys_mii_mask) {
2571 port = ksz_phy_addr_to_port(dev, phy);
2572 if (port < 0) {
2573 ret = port;
2574 goto out;
2575 }
2576
2577 irq = irq_find_mapping(dev->ports[port].pirq.domain,
2578 PORT_SRC_PHY_INT);
2579 if (irq < 0) {
2580 ret = irq;
2581 goto out;
2582 }
2583 ds->user_mii_bus->irq[phy] = irq;
2584 }
2585 }
2586 return 0;
2587 out:
2588 while (phy--)
2589 if (BIT(phy) & ds->phys_mii_mask)
2590 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2591
2592 return ret;
2593 }
2594
2595 /**
2596 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2597 * @dev: Pointer to the KSZ device structure.
2598 *
2599 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2600 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2601 */
ksz_irq_phy_free(struct ksz_device * dev)2602 static void ksz_irq_phy_free(struct ksz_device *dev)
2603 {
2604 struct dsa_switch *ds = dev->ds;
2605 int phy;
2606
2607 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2608 if (BIT(phy) & ds->phys_mii_mask)
2609 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2610 }
2611
2612 /**
2613 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2614 * @dev: pointer to the KSZ device structure
2615 * @bus: pointer to the MII bus structure
2616 * @mdio_np: pointer to the MDIO node in the device tree
2617 *
2618 * This function parses and validates PHY configurations for each user port
2619 * defined in the device tree for a KSZ switch device. It verifies that the
2620 * `phy-handle` properties are correctly set and that the internal PHYs match
2621 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2622 * all validations pass. Logs error messages for any mismatches or missing data.
2623 *
2624 * Return: 0 on success, or a negative error code on failure.
2625 */
ksz_parse_dt_phy_config(struct ksz_device * dev,struct mii_bus * bus,struct device_node * mdio_np)2626 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2627 struct device_node *mdio_np)
2628 {
2629 struct device_node *phy_node, *phy_parent_node;
2630 bool phys_are_valid = true;
2631 struct dsa_port *dp;
2632 u32 phy_addr;
2633 int ret;
2634
2635 dsa_switch_for_each_user_port(dp, dev->ds) {
2636 if (!dev->info->internal_phy[dp->index])
2637 continue;
2638
2639 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0);
2640 if (!phy_node) {
2641 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2642 dp->index);
2643 phys_are_valid = false;
2644 continue;
2645 }
2646
2647 phy_parent_node = of_get_parent(phy_node);
2648 if (!phy_parent_node) {
2649 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2650 dp->index);
2651 phys_are_valid = false;
2652 } else if (phy_parent_node != mdio_np) {
2653 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2654 dp->index, mdio_np, phy_parent_node);
2655 phys_are_valid = false;
2656 } else {
2657 ret = of_property_read_u32(phy_node, "reg", &phy_addr);
2658 if (ret < 0) {
2659 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2660 dp->index, ret);
2661 phys_are_valid = false;
2662 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2663 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2664 dp->index, dev->phy_addr_map[dp->index],
2665 phy_addr);
2666 phys_are_valid = false;
2667 } else {
2668 bus->phy_mask |= BIT(phy_addr);
2669 }
2670 }
2671
2672 of_node_put(phy_node);
2673 of_node_put(phy_parent_node);
2674 }
2675
2676 if (!phys_are_valid)
2677 return -EINVAL;
2678
2679 return 0;
2680 }
2681
2682 /**
2683 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2684 * @dev: Pointer to the KSZ device structure.
2685 *
2686 * This function sets up and registers an MDIO bus for the KSZ switch device,
2687 * allowing access to its internal PHYs. If the device supports side MDIO,
2688 * the function will configure the external MDIO controller specified by the
2689 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2690 * Otherwise, SPI or I2C access is set up for PHY access.
2691 *
2692 * Return: 0 on success, or a negative error code on failure.
2693 */
ksz_mdio_register(struct ksz_device * dev)2694 static int ksz_mdio_register(struct ksz_device *dev)
2695 {
2696 struct device_node *parent_bus_node;
2697 struct mii_bus *parent_bus = NULL;
2698 struct dsa_switch *ds = dev->ds;
2699 struct device_node *mdio_np;
2700 struct mii_bus *bus;
2701 int ret, i;
2702
2703 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2704 if (!mdio_np)
2705 return 0;
2706
2707 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0);
2708 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2709 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2710 ret = -EINVAL;
2711
2712 goto put_mdio_node;
2713 } else if (parent_bus_node) {
2714 parent_bus = of_mdio_find_bus(parent_bus_node);
2715 if (!parent_bus) {
2716 ret = -EPROBE_DEFER;
2717
2718 goto put_mdio_node;
2719 }
2720
2721 dev->parent_mdio_bus = parent_bus;
2722 }
2723
2724 bus = devm_mdiobus_alloc(ds->dev);
2725 if (!bus) {
2726 ret = -ENOMEM;
2727 goto put_mdio_node;
2728 }
2729
2730 if (dev->dev_ops->mdio_bus_preinit) {
2731 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2732 if (ret)
2733 goto put_mdio_node;
2734 }
2735
2736 if (dev->dev_ops->create_phy_addr_map) {
2737 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2738 if (ret)
2739 goto put_mdio_node;
2740 } else {
2741 for (i = 0; i < dev->info->port_cnt; i++)
2742 dev->phy_addr_map[i] = i;
2743 }
2744
2745 bus->priv = dev;
2746 if (parent_bus) {
2747 bus->read = ksz_parent_mdio_read;
2748 bus->write = ksz_parent_mdio_write;
2749 bus->name = "KSZ side MDIO";
2750 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d",
2751 ds->index);
2752 } else {
2753 bus->read = ksz_sw_mdio_read;
2754 bus->write = ksz_sw_mdio_write;
2755 bus->name = "ksz user smi";
2756 if (ds->dst->index != 0) {
2757 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index);
2758 } else {
2759 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2760 }
2761 }
2762
2763 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2764 if (ret)
2765 goto put_mdio_node;
2766
2767 ds->phys_mii_mask = bus->phy_mask;
2768 bus->parent = ds->dev;
2769
2770 ds->user_mii_bus = bus;
2771
2772 if (dev->irq > 0) {
2773 ret = ksz_irq_phy_setup(dev);
2774 if (ret)
2775 goto put_mdio_node;
2776 }
2777
2778 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2779 if (ret) {
2780 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2781 bus->id);
2782 if (dev->irq > 0)
2783 ksz_irq_phy_free(dev);
2784 }
2785
2786 put_mdio_node:
2787 of_node_put(mdio_np);
2788 of_node_put(parent_bus_node);
2789
2790 return ret;
2791 }
2792
ksz_irq_mask(struct irq_data * d)2793 static void ksz_irq_mask(struct irq_data *d)
2794 {
2795 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2796
2797 kirq->masked |= BIT(d->hwirq);
2798 }
2799
ksz_irq_unmask(struct irq_data * d)2800 static void ksz_irq_unmask(struct irq_data *d)
2801 {
2802 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2803
2804 kirq->masked &= ~BIT(d->hwirq);
2805 }
2806
ksz_irq_bus_lock(struct irq_data * d)2807 static void ksz_irq_bus_lock(struct irq_data *d)
2808 {
2809 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2810
2811 mutex_lock(&kirq->dev->lock_irq);
2812 }
2813
ksz_irq_bus_sync_unlock(struct irq_data * d)2814 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2815 {
2816 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2817 struct ksz_device *dev = kirq->dev;
2818 int ret;
2819
2820 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2821 if (ret)
2822 dev_err(dev->dev, "failed to change IRQ mask\n");
2823
2824 mutex_unlock(&dev->lock_irq);
2825 }
2826
2827 static const struct irq_chip ksz_irq_chip = {
2828 .name = "ksz-irq",
2829 .irq_mask = ksz_irq_mask,
2830 .irq_unmask = ksz_irq_unmask,
2831 .irq_bus_lock = ksz_irq_bus_lock,
2832 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2833 };
2834
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2835 static int ksz_irq_domain_map(struct irq_domain *d,
2836 unsigned int irq, irq_hw_number_t hwirq)
2837 {
2838 irq_set_chip_data(irq, d->host_data);
2839 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2840 irq_set_noprobe(irq);
2841
2842 return 0;
2843 }
2844
2845 static const struct irq_domain_ops ksz_irq_domain_ops = {
2846 .map = ksz_irq_domain_map,
2847 .xlate = irq_domain_xlate_twocell,
2848 };
2849
ksz_irq_free(struct ksz_irq * kirq)2850 static void ksz_irq_free(struct ksz_irq *kirq)
2851 {
2852 int irq, virq;
2853
2854 free_irq(kirq->irq_num, kirq);
2855
2856 for (irq = 0; irq < kirq->nirqs; irq++) {
2857 virq = irq_find_mapping(kirq->domain, irq);
2858 irq_dispose_mapping(virq);
2859 }
2860
2861 irq_domain_remove(kirq->domain);
2862 }
2863
ksz_irq_thread_fn(int irq,void * dev_id)2864 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2865 {
2866 struct ksz_irq *kirq = dev_id;
2867 unsigned int nhandled = 0;
2868 struct ksz_device *dev;
2869 unsigned int sub_irq;
2870 u8 data;
2871 int ret;
2872 u8 n;
2873
2874 dev = kirq->dev;
2875
2876 /* Read interrupt status register */
2877 ret = ksz_read8(dev, kirq->reg_status, &data);
2878 if (ret)
2879 goto out;
2880
2881 for (n = 0; n < kirq->nirqs; ++n) {
2882 if (data & BIT(n)) {
2883 sub_irq = irq_find_mapping(kirq->domain, n);
2884 handle_nested_irq(sub_irq);
2885 ++nhandled;
2886 }
2887 }
2888 out:
2889 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2890 }
2891
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2892 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2893 {
2894 int ret, n;
2895
2896 kirq->dev = dev;
2897 kirq->masked = ~0;
2898
2899 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0,
2900 &ksz_irq_domain_ops, kirq);
2901 if (!kirq->domain)
2902 return -ENOMEM;
2903
2904 for (n = 0; n < kirq->nirqs; n++)
2905 irq_create_mapping(kirq->domain, n);
2906
2907 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2908 IRQF_ONESHOT, kirq->name, kirq);
2909 if (ret)
2910 goto out;
2911
2912 return 0;
2913
2914 out:
2915 ksz_irq_free(kirq);
2916
2917 return ret;
2918 }
2919
ksz_girq_setup(struct ksz_device * dev)2920 static int ksz_girq_setup(struct ksz_device *dev)
2921 {
2922 struct ksz_irq *girq = &dev->girq;
2923
2924 girq->nirqs = dev->info->port_cnt;
2925 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2926 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2927 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2928
2929 girq->irq_num = dev->irq;
2930
2931 return ksz_irq_common_setup(dev, girq);
2932 }
2933
ksz_pirq_setup(struct ksz_device * dev,u8 p)2934 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2935 {
2936 struct ksz_irq *pirq = &dev->ports[p].pirq;
2937
2938 pirq->nirqs = dev->info->port_nirqs;
2939 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2940 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2941 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2942
2943 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2944 if (pirq->irq_num < 0)
2945 return pirq->irq_num;
2946
2947 return ksz_irq_common_setup(dev, pirq);
2948 }
2949
2950 static int ksz_parse_drive_strength(struct ksz_device *dev);
2951
ksz_setup(struct dsa_switch * ds)2952 static int ksz_setup(struct dsa_switch *ds)
2953 {
2954 struct ksz_device *dev = ds->priv;
2955 u16 storm_mask, storm_rate;
2956 struct dsa_port *dp;
2957 struct ksz_port *p;
2958 const u16 *regs;
2959 int ret;
2960
2961 regs = dev->info->regs;
2962
2963 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2964 dev->info->num_vlans, GFP_KERNEL);
2965 if (!dev->vlan_cache)
2966 return -ENOMEM;
2967
2968 ret = dev->dev_ops->reset(dev);
2969 if (ret) {
2970 dev_err(ds->dev, "failed to reset switch\n");
2971 return ret;
2972 }
2973
2974 ret = ksz_parse_drive_strength(dev);
2975 if (ret)
2976 return ret;
2977
2978 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) {
2979 ret = dev->dev_ops->pcs_create(dev);
2980 if (ret)
2981 return ret;
2982 }
2983
2984 /* set broadcast storm protection 10% rate */
2985 storm_mask = BROADCAST_STORM_RATE;
2986 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
2987 if (ksz_is_ksz8463(dev)) {
2988 storm_mask = swab16(storm_mask);
2989 storm_rate = swab16(storm_rate);
2990 }
2991 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2992 storm_mask, storm_rate);
2993
2994 dev->dev_ops->config_cpu_port(ds);
2995
2996 dev->dev_ops->enable_stp_addr(dev);
2997
2998 ds->num_tx_queues = dev->info->num_tx_queues;
2999
3000 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
3001 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
3002
3003 ksz_init_mib_timer(dev);
3004
3005 ds->configure_vlan_while_not_filtering = false;
3006 ds->dscp_prio_mapping_is_global = true;
3007
3008 if (dev->dev_ops->setup) {
3009 ret = dev->dev_ops->setup(ds);
3010 if (ret)
3011 return ret;
3012 }
3013
3014 /* Start with learning disabled on standalone user ports, and enabled
3015 * on the CPU port. In lack of other finer mechanisms, learning on the
3016 * CPU port will avoid flooding bridge local addresses on the network
3017 * in some cases.
3018 */
3019 p = &dev->ports[dev->cpu_port];
3020 p->learning = true;
3021
3022 if (dev->irq > 0) {
3023 ret = ksz_girq_setup(dev);
3024 if (ret)
3025 return ret;
3026
3027 dsa_switch_for_each_user_port(dp, dev->ds) {
3028 ret = ksz_pirq_setup(dev, dp->index);
3029 if (ret)
3030 goto out_girq;
3031
3032 if (dev->info->ptp_capable) {
3033 ret = ksz_ptp_irq_setup(ds, dp->index);
3034 if (ret)
3035 goto out_pirq;
3036 }
3037 }
3038 }
3039
3040 if (dev->info->ptp_capable) {
3041 ret = ksz_ptp_clock_register(ds);
3042 if (ret) {
3043 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
3044 ret);
3045 goto out_ptpirq;
3046 }
3047 }
3048
3049 ret = ksz_mdio_register(dev);
3050 if (ret < 0) {
3051 dev_err(dev->dev, "failed to register the mdio");
3052 goto out_ptp_clock_unregister;
3053 }
3054
3055 ret = ksz_dcb_init(dev);
3056 if (ret)
3057 goto out_ptp_clock_unregister;
3058
3059 /* start switch */
3060 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
3061 SW_START, SW_START);
3062
3063 return 0;
3064
3065 out_ptp_clock_unregister:
3066 if (dev->info->ptp_capable)
3067 ksz_ptp_clock_unregister(ds);
3068 out_ptpirq:
3069 if (dev->irq > 0 && dev->info->ptp_capable)
3070 dsa_switch_for_each_user_port(dp, dev->ds)
3071 ksz_ptp_irq_free(ds, dp->index);
3072 out_pirq:
3073 if (dev->irq > 0)
3074 dsa_switch_for_each_user_port(dp, dev->ds)
3075 ksz_irq_free(&dev->ports[dp->index].pirq);
3076 out_girq:
3077 if (dev->irq > 0)
3078 ksz_irq_free(&dev->girq);
3079
3080 return ret;
3081 }
3082
ksz_teardown(struct dsa_switch * ds)3083 static void ksz_teardown(struct dsa_switch *ds)
3084 {
3085 struct ksz_device *dev = ds->priv;
3086 struct dsa_port *dp;
3087
3088 if (dev->info->ptp_capable)
3089 ksz_ptp_clock_unregister(ds);
3090
3091 if (dev->irq > 0) {
3092 dsa_switch_for_each_user_port(dp, dev->ds) {
3093 if (dev->info->ptp_capable)
3094 ksz_ptp_irq_free(ds, dp->index);
3095
3096 ksz_irq_free(&dev->ports[dp->index].pirq);
3097 }
3098
3099 ksz_irq_free(&dev->girq);
3100 }
3101
3102 if (dev->dev_ops->teardown)
3103 dev->dev_ops->teardown(ds);
3104 }
3105
port_r_cnt(struct ksz_device * dev,int port)3106 static void port_r_cnt(struct ksz_device *dev, int port)
3107 {
3108 struct ksz_port_mib *mib = &dev->ports[port].mib;
3109 u64 *dropped;
3110
3111 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
3112 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
3113 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
3114 &mib->counters[mib->cnt_ptr]);
3115 ++mib->cnt_ptr;
3116 }
3117
3118 /* last one in storage */
3119 dropped = &mib->counters[dev->info->mib_cnt];
3120
3121 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
3122 while (mib->cnt_ptr < dev->info->mib_cnt) {
3123 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
3124 dropped, &mib->counters[mib->cnt_ptr]);
3125 ++mib->cnt_ptr;
3126 }
3127 mib->cnt_ptr = 0;
3128 }
3129
ksz_mib_read_work(struct work_struct * work)3130 static void ksz_mib_read_work(struct work_struct *work)
3131 {
3132 struct ksz_device *dev = container_of(work, struct ksz_device,
3133 mib_read.work);
3134 struct ksz_port_mib *mib;
3135 struct ksz_port *p;
3136 int i;
3137
3138 for (i = 0; i < dev->info->port_cnt; i++) {
3139 if (dsa_is_unused_port(dev->ds, i))
3140 continue;
3141
3142 p = &dev->ports[i];
3143 mib = &p->mib;
3144 mutex_lock(&mib->cnt_mutex);
3145
3146 /* Only read MIB counters when the port is told to do.
3147 * If not, read only dropped counters when link is not up.
3148 */
3149 if (!p->read) {
3150 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
3151
3152 if (!netif_carrier_ok(dp->user))
3153 mib->cnt_ptr = dev->info->reg_mib_cnt;
3154 }
3155 port_r_cnt(dev, i);
3156 p->read = false;
3157
3158 if (dev->dev_ops->r_mib_stat64)
3159 dev->dev_ops->r_mib_stat64(dev, i);
3160
3161 mutex_unlock(&mib->cnt_mutex);
3162 }
3163
3164 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
3165 }
3166
ksz_init_mib_timer(struct ksz_device * dev)3167 void ksz_init_mib_timer(struct ksz_device *dev)
3168 {
3169 int i;
3170
3171 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
3172
3173 for (i = 0; i < dev->info->port_cnt; i++) {
3174 struct ksz_port_mib *mib = &dev->ports[i].mib;
3175
3176 dev->dev_ops->port_init_cnt(dev, i);
3177
3178 mib->cnt_ptr = 0;
3179 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
3180 }
3181 }
3182
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)3183 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
3184 {
3185 struct ksz_device *dev = ds->priv;
3186 u16 val = 0xffff;
3187 int ret;
3188
3189 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
3190 if (ret)
3191 return ret;
3192
3193 return val;
3194 }
3195
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)3196 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
3197 {
3198 struct ksz_device *dev = ds->priv;
3199 int ret;
3200
3201 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
3202 if (ret)
3203 return ret;
3204
3205 return 0;
3206 }
3207
ksz_get_phy_flags(struct dsa_switch * ds,int port)3208 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
3209 {
3210 struct ksz_device *dev = ds->priv;
3211
3212 switch (dev->chip_id) {
3213 case KSZ88X3_CHIP_ID:
3214 /* Silicon Errata Sheet (DS80000830A):
3215 * Port 1 does not work with LinkMD Cable-Testing.
3216 * Port 1 does not respond to received PAUSE control frames.
3217 */
3218 if (!port)
3219 return MICREL_KSZ8_P1_ERRATA;
3220 break;
3221 }
3222
3223 return 0;
3224 }
3225
ksz_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)3226 static void ksz_phylink_mac_link_down(struct phylink_config *config,
3227 unsigned int mode,
3228 phy_interface_t interface)
3229 {
3230 struct dsa_port *dp = dsa_phylink_to_port(config);
3231 struct ksz_device *dev = dp->ds->priv;
3232
3233 /* Read all MIB counters when the link is going down. */
3234 dev->ports[dp->index].read = true;
3235 /* timer started */
3236 if (dev->mib_read_interval)
3237 schedule_delayed_work(&dev->mib_read, 0);
3238 }
3239
ksz_sset_count(struct dsa_switch * ds,int port,int sset)3240 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3241 {
3242 struct ksz_device *dev = ds->priv;
3243
3244 if (sset != ETH_SS_STATS)
3245 return 0;
3246
3247 return dev->info->mib_cnt;
3248 }
3249
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)3250 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3251 uint64_t *buf)
3252 {
3253 const struct dsa_port *dp = dsa_to_port(ds, port);
3254 struct ksz_device *dev = ds->priv;
3255 struct ksz_port_mib *mib;
3256
3257 mib = &dev->ports[port].mib;
3258 mutex_lock(&mib->cnt_mutex);
3259
3260 /* Only read dropped counters if no link. */
3261 if (!netif_carrier_ok(dp->user))
3262 mib->cnt_ptr = dev->info->reg_mib_cnt;
3263 port_r_cnt(dev, port);
3264 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3265 mutex_unlock(&mib->cnt_mutex);
3266 }
3267
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)3268 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3269 struct dsa_bridge bridge,
3270 bool *tx_fwd_offload,
3271 struct netlink_ext_ack *extack)
3272 {
3273 /* port_stp_state_set() will be called after to put the port in
3274 * appropriate state so there is no need to do anything.
3275 */
3276
3277 return 0;
3278 }
3279
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)3280 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3281 struct dsa_bridge bridge)
3282 {
3283 /* port_stp_state_set() will be called after to put the port in
3284 * forwarding state so there is no need to do anything.
3285 */
3286 }
3287
ksz_port_fast_age(struct dsa_switch * ds,int port)3288 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3289 {
3290 struct ksz_device *dev = ds->priv;
3291
3292 dev->dev_ops->flush_dyn_mac_table(dev, port);
3293 }
3294
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)3295 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3296 {
3297 struct ksz_device *dev = ds->priv;
3298
3299 if (!dev->dev_ops->set_ageing_time)
3300 return -EOPNOTSUPP;
3301
3302 return dev->dev_ops->set_ageing_time(dev, msecs);
3303 }
3304
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3305 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3306 const unsigned char *addr, u16 vid,
3307 struct dsa_db db)
3308 {
3309 struct ksz_device *dev = ds->priv;
3310
3311 if (!dev->dev_ops->fdb_add)
3312 return -EOPNOTSUPP;
3313
3314 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3315 }
3316
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3317 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3318 const unsigned char *addr,
3319 u16 vid, struct dsa_db db)
3320 {
3321 struct ksz_device *dev = ds->priv;
3322
3323 if (!dev->dev_ops->fdb_del)
3324 return -EOPNOTSUPP;
3325
3326 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3327 }
3328
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)3329 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3330 dsa_fdb_dump_cb_t *cb, void *data)
3331 {
3332 struct ksz_device *dev = ds->priv;
3333
3334 if (!dev->dev_ops->fdb_dump)
3335 return -EOPNOTSUPP;
3336
3337 return dev->dev_ops->fdb_dump(dev, port, cb, data);
3338 }
3339
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3340 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3341 const struct switchdev_obj_port_mdb *mdb,
3342 struct dsa_db db)
3343 {
3344 struct ksz_device *dev = ds->priv;
3345
3346 if (!dev->dev_ops->mdb_add)
3347 return -EOPNOTSUPP;
3348
3349 return dev->dev_ops->mdb_add(dev, port, mdb, db);
3350 }
3351
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3352 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3353 const struct switchdev_obj_port_mdb *mdb,
3354 struct dsa_db db)
3355 {
3356 struct ksz_device *dev = ds->priv;
3357
3358 if (!dev->dev_ops->mdb_del)
3359 return -EOPNOTSUPP;
3360
3361 return dev->dev_ops->mdb_del(dev, port, mdb, db);
3362 }
3363
ksz9477_set_default_prio_queue_mapping(struct ksz_device * dev,int port)3364 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3365 int port)
3366 {
3367 u32 queue_map = 0;
3368 int ipm;
3369
3370 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3371 int queue;
3372
3373 /* Traffic Type (TT) is corresponding to the Internal Priority
3374 * Map (IPM) in the switch. Traffic Class (TC) is
3375 * corresponding to the queue in the switch.
3376 */
3377 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
3378 if (queue < 0)
3379 return queue;
3380
3381 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3382 }
3383
3384 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3385 }
3386
ksz_port_setup(struct dsa_switch * ds,int port)3387 static int ksz_port_setup(struct dsa_switch *ds, int port)
3388 {
3389 struct ksz_device *dev = ds->priv;
3390 int ret;
3391
3392 if (!dsa_is_user_port(ds, port))
3393 return 0;
3394
3395 /* setup user port */
3396 dev->dev_ops->port_setup(dev, port, false);
3397
3398 if (!is_ksz8(dev)) {
3399 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3400 if (ret)
3401 return ret;
3402 }
3403
3404 /* port_stp_state_set() will be called after to enable the port so
3405 * there is no need to do anything.
3406 */
3407
3408 return ksz_dcb_init_port(dev, port);
3409 }
3410
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)3411 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3412 {
3413 struct ksz_device *dev = ds->priv;
3414 struct ksz_port *p;
3415 const u16 *regs;
3416 u8 data;
3417
3418 regs = dev->info->regs;
3419
3420 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
3421 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3422
3423 p = &dev->ports[port];
3424
3425 switch (state) {
3426 case BR_STATE_DISABLED:
3427 data |= PORT_LEARN_DISABLE;
3428 break;
3429 case BR_STATE_LISTENING:
3430 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3431 break;
3432 case BR_STATE_LEARNING:
3433 data |= PORT_RX_ENABLE;
3434 if (!p->learning)
3435 data |= PORT_LEARN_DISABLE;
3436 break;
3437 case BR_STATE_FORWARDING:
3438 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3439 if (!p->learning)
3440 data |= PORT_LEARN_DISABLE;
3441 break;
3442 case BR_STATE_BLOCKING:
3443 data |= PORT_LEARN_DISABLE;
3444 break;
3445 default:
3446 dev_err(ds->dev, "invalid STP state: %d\n", state);
3447 return;
3448 }
3449
3450 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
3451
3452 p->stp_state = state;
3453
3454 ksz_update_port_member(dev, port);
3455 }
3456
ksz_port_teardown(struct dsa_switch * ds,int port)3457 static void ksz_port_teardown(struct dsa_switch *ds, int port)
3458 {
3459 struct ksz_device *dev = ds->priv;
3460
3461 switch (dev->chip_id) {
3462 case KSZ8563_CHIP_ID:
3463 case KSZ8567_CHIP_ID:
3464 case KSZ9477_CHIP_ID:
3465 case KSZ9563_CHIP_ID:
3466 case KSZ9567_CHIP_ID:
3467 case KSZ9893_CHIP_ID:
3468 case KSZ9896_CHIP_ID:
3469 case KSZ9897_CHIP_ID:
3470 case LAN9646_CHIP_ID:
3471 if (dsa_is_user_port(ds, port))
3472 ksz9477_port_acl_free(dev, port);
3473 }
3474 }
3475
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3476 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3477 struct switchdev_brport_flags flags,
3478 struct netlink_ext_ack *extack)
3479 {
3480 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3481 return -EINVAL;
3482
3483 return 0;
3484 }
3485
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3486 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3487 struct switchdev_brport_flags flags,
3488 struct netlink_ext_ack *extack)
3489 {
3490 struct ksz_device *dev = ds->priv;
3491 struct ksz_port *p = &dev->ports[port];
3492
3493 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3494 if (flags.mask & BR_LEARNING)
3495 p->learning = !!(flags.val & BR_LEARNING);
3496
3497 if (flags.mask & BR_ISOLATED)
3498 p->isolated = !!(flags.val & BR_ISOLATED);
3499
3500 /* Make the change take effect immediately */
3501 ksz_port_stp_state_set(ds, port, p->stp_state);
3502 }
3503
3504 return 0;
3505 }
3506
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)3507 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3508 int port,
3509 enum dsa_tag_protocol mp)
3510 {
3511 struct ksz_device *dev = ds->priv;
3512 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3513
3514 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3515 proto = DSA_TAG_PROTO_KSZ8795;
3516
3517 if (dev->chip_id == KSZ88X3_CHIP_ID ||
3518 dev->chip_id == KSZ8463_CHIP_ID ||
3519 dev->chip_id == KSZ8563_CHIP_ID ||
3520 dev->chip_id == KSZ9893_CHIP_ID ||
3521 dev->chip_id == KSZ9563_CHIP_ID)
3522 proto = DSA_TAG_PROTO_KSZ9893;
3523
3524 if (dev->chip_id == KSZ8567_CHIP_ID ||
3525 dev->chip_id == KSZ9477_CHIP_ID ||
3526 dev->chip_id == KSZ9896_CHIP_ID ||
3527 dev->chip_id == KSZ9897_CHIP_ID ||
3528 dev->chip_id == KSZ9567_CHIP_ID ||
3529 dev->chip_id == LAN9646_CHIP_ID)
3530 proto = DSA_TAG_PROTO_KSZ9477;
3531
3532 if (is_lan937x(dev))
3533 proto = DSA_TAG_PROTO_LAN937X;
3534
3535 return proto;
3536 }
3537
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)3538 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3539 enum dsa_tag_protocol proto)
3540 {
3541 struct ksz_tagger_data *tagger_data;
3542
3543 switch (proto) {
3544 case DSA_TAG_PROTO_KSZ8795:
3545 return 0;
3546 case DSA_TAG_PROTO_KSZ9893:
3547 case DSA_TAG_PROTO_KSZ9477:
3548 case DSA_TAG_PROTO_LAN937X:
3549 tagger_data = ksz_tagger_data(ds);
3550 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3551 return 0;
3552 default:
3553 return -EPROTONOSUPPORT;
3554 }
3555 }
3556
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)3557 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3558 bool flag, struct netlink_ext_ack *extack)
3559 {
3560 struct ksz_device *dev = ds->priv;
3561
3562 if (!dev->dev_ops->vlan_filtering)
3563 return -EOPNOTSUPP;
3564
3565 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3566 }
3567
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)3568 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3569 const struct switchdev_obj_port_vlan *vlan,
3570 struct netlink_ext_ack *extack)
3571 {
3572 struct ksz_device *dev = ds->priv;
3573
3574 if (!dev->dev_ops->vlan_add)
3575 return -EOPNOTSUPP;
3576
3577 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3578 }
3579
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)3580 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3581 const struct switchdev_obj_port_vlan *vlan)
3582 {
3583 struct ksz_device *dev = ds->priv;
3584
3585 if (!dev->dev_ops->vlan_del)
3586 return -EOPNOTSUPP;
3587
3588 return dev->dev_ops->vlan_del(dev, port, vlan);
3589 }
3590
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)3591 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3592 struct dsa_mall_mirror_tc_entry *mirror,
3593 bool ingress, struct netlink_ext_ack *extack)
3594 {
3595 struct ksz_device *dev = ds->priv;
3596
3597 if (!dev->dev_ops->mirror_add)
3598 return -EOPNOTSUPP;
3599
3600 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3601 }
3602
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)3603 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3604 struct dsa_mall_mirror_tc_entry *mirror)
3605 {
3606 struct ksz_device *dev = ds->priv;
3607
3608 if (dev->dev_ops->mirror_del)
3609 dev->dev_ops->mirror_del(dev, port, mirror);
3610 }
3611
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)3612 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3613 {
3614 struct ksz_device *dev = ds->priv;
3615
3616 if (!dev->dev_ops->change_mtu)
3617 return -EOPNOTSUPP;
3618
3619 return dev->dev_ops->change_mtu(dev, port, mtu);
3620 }
3621
ksz_max_mtu(struct dsa_switch * ds,int port)3622 static int ksz_max_mtu(struct dsa_switch *ds, int port)
3623 {
3624 struct ksz_device *dev = ds->priv;
3625
3626 switch (dev->chip_id) {
3627 case KSZ8795_CHIP_ID:
3628 case KSZ8794_CHIP_ID:
3629 case KSZ8765_CHIP_ID:
3630 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3631 case KSZ8463_CHIP_ID:
3632 case KSZ88X3_CHIP_ID:
3633 case KSZ8864_CHIP_ID:
3634 case KSZ8895_CHIP_ID:
3635 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3636 case KSZ8563_CHIP_ID:
3637 case KSZ8567_CHIP_ID:
3638 case KSZ9477_CHIP_ID:
3639 case KSZ9563_CHIP_ID:
3640 case KSZ9567_CHIP_ID:
3641 case KSZ9893_CHIP_ID:
3642 case KSZ9896_CHIP_ID:
3643 case KSZ9897_CHIP_ID:
3644 case LAN9370_CHIP_ID:
3645 case LAN9371_CHIP_ID:
3646 case LAN9372_CHIP_ID:
3647 case LAN9373_CHIP_ID:
3648 case LAN9374_CHIP_ID:
3649 case LAN9646_CHIP_ID:
3650 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3651 }
3652
3653 return -EOPNOTSUPP;
3654 }
3655
3656 /**
3657 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a
3658 * port
3659 * @ds: Pointer to the DSA switch structure
3660 * @port: Port number to check
3661 *
3662 * This function also documents devices where EEE was initially advertised but
3663 * later withdrawn due to reliability issues, as described in official errata
3664 * documents. These devices are explicitly listed to record known limitations,
3665 * even if there is no technical necessity for runtime checks.
3666 *
3667 * Returns: true if the internal PHY on the given port supports fully
3668 * operational EEE, false otherwise.
3669 */
ksz_support_eee(struct dsa_switch * ds,int port)3670 static bool ksz_support_eee(struct dsa_switch *ds, int port)
3671 {
3672 struct ksz_device *dev = ds->priv;
3673
3674 if (!dev->info->internal_phy[port])
3675 return false;
3676
3677 switch (dev->chip_id) {
3678 case KSZ8563_CHIP_ID:
3679 case KSZ9563_CHIP_ID:
3680 case KSZ9893_CHIP_ID:
3681 return true;
3682 case KSZ8567_CHIP_ID:
3683 /* KSZ8567R Errata DS80000752C Module 4 */
3684 case KSZ8765_CHIP_ID:
3685 case KSZ8794_CHIP_ID:
3686 case KSZ8795_CHIP_ID:
3687 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
3688 case KSZ9477_CHIP_ID:
3689 /* KSZ9477S Errata DS80000754A Module 4 */
3690 case KSZ9567_CHIP_ID:
3691 /* KSZ9567S Errata DS80000756A Module 4 */
3692 case KSZ9896_CHIP_ID:
3693 /* KSZ9896C Errata DS80000757A Module 3 */
3694 case KSZ9897_CHIP_ID:
3695 case LAN9646_CHIP_ID:
3696 /* KSZ9897R Errata DS80000758C Module 4 */
3697 /* Energy Efficient Ethernet (EEE) feature select must be
3698 * manually disabled
3699 * The EEE feature is enabled by default, but it is not fully
3700 * operational. It must be manually disabled through register
3701 * controls. If not disabled, the PHY ports can auto-negotiate
3702 * to enable EEE, and this feature can cause link drops when
3703 * linked to another device supporting EEE.
3704 *
3705 * The same item appears in the errata for all switches above.
3706 */
3707 break;
3708 }
3709
3710 return false;
3711 }
3712
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)3713 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3714 struct ethtool_keee *e)
3715 {
3716 struct ksz_device *dev = ds->priv;
3717
3718 if (!e->tx_lpi_enabled) {
3719 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3720 return -EINVAL;
3721 }
3722
3723 if (e->tx_lpi_timer) {
3724 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3725 return -EINVAL;
3726 }
3727
3728 return 0;
3729 }
3730
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)3731 static void ksz_set_xmii(struct ksz_device *dev, int port,
3732 phy_interface_t interface)
3733 {
3734 const u8 *bitval = dev->info->xmii_ctrl1;
3735 struct ksz_port *p = &dev->ports[port];
3736 const u16 *regs = dev->info->regs;
3737 u8 data8;
3738
3739 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3740
3741 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3742 P_RGMII_ID_EG_ENABLE);
3743
3744 switch (interface) {
3745 case PHY_INTERFACE_MODE_MII:
3746 data8 |= bitval[P_MII_SEL];
3747 break;
3748 case PHY_INTERFACE_MODE_RMII:
3749 data8 |= bitval[P_RMII_SEL];
3750 break;
3751 case PHY_INTERFACE_MODE_GMII:
3752 data8 |= bitval[P_GMII_SEL];
3753 break;
3754 case PHY_INTERFACE_MODE_RGMII:
3755 case PHY_INTERFACE_MODE_RGMII_ID:
3756 case PHY_INTERFACE_MODE_RGMII_TXID:
3757 case PHY_INTERFACE_MODE_RGMII_RXID:
3758 data8 |= bitval[P_RGMII_SEL];
3759 /* On KSZ9893, disable RGMII in-band status support */
3760 if (dev->chip_id == KSZ9893_CHIP_ID ||
3761 dev->chip_id == KSZ8563_CHIP_ID ||
3762 dev->chip_id == KSZ9563_CHIP_ID ||
3763 is_lan937x(dev))
3764 data8 &= ~P_MII_MAC_MODE;
3765 break;
3766 default:
3767 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3768 phy_modes(interface), port);
3769 return;
3770 }
3771
3772 if (p->rgmii_tx_val)
3773 data8 |= P_RGMII_ID_EG_ENABLE;
3774
3775 if (p->rgmii_rx_val)
3776 data8 |= P_RGMII_ID_IG_ENABLE;
3777
3778 /* Write the updated value */
3779 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3780 }
3781
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)3782 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3783 {
3784 const u8 *bitval = dev->info->xmii_ctrl1;
3785 const u16 *regs = dev->info->regs;
3786 phy_interface_t interface;
3787 u8 data8;
3788 u8 val;
3789
3790 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3791
3792 val = FIELD_GET(P_MII_SEL_M, data8);
3793
3794 if (val == bitval[P_MII_SEL]) {
3795 if (gbit)
3796 interface = PHY_INTERFACE_MODE_GMII;
3797 else
3798 interface = PHY_INTERFACE_MODE_MII;
3799 } else if (val == bitval[P_RMII_SEL]) {
3800 interface = PHY_INTERFACE_MODE_RMII;
3801 } else {
3802 interface = PHY_INTERFACE_MODE_RGMII;
3803 if (data8 & P_RGMII_ID_EG_ENABLE)
3804 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3805 if (data8 & P_RGMII_ID_IG_ENABLE) {
3806 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3807 if (data8 & P_RGMII_ID_EG_ENABLE)
3808 interface = PHY_INTERFACE_MODE_RGMII_ID;
3809 }
3810 }
3811
3812 return interface;
3813 }
3814
ksz88x3_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3815 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3816 unsigned int mode,
3817 const struct phylink_link_state *state)
3818 {
3819 struct dsa_port *dp = dsa_phylink_to_port(config);
3820 struct ksz_device *dev = dp->ds->priv;
3821
3822 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3823 }
3824
ksz_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3825 static void ksz_phylink_mac_config(struct phylink_config *config,
3826 unsigned int mode,
3827 const struct phylink_link_state *state)
3828 {
3829 struct dsa_port *dp = dsa_phylink_to_port(config);
3830 struct ksz_device *dev = dp->ds->priv;
3831 int port = dp->index;
3832
3833 /* Internal PHYs */
3834 if (dev->info->internal_phy[port])
3835 return;
3836
3837 /* No need to configure XMII control register when using SGMII. */
3838 if (ksz_is_sgmii_port(dev, port))
3839 return;
3840
3841 if (phylink_autoneg_inband(mode)) {
3842 dev_err(dev->dev, "In-band AN not supported!\n");
3843 return;
3844 }
3845
3846 ksz_set_xmii(dev, port, state->interface);
3847
3848 if (dev->dev_ops->setup_rgmii_delay)
3849 dev->dev_ops->setup_rgmii_delay(dev, port);
3850 }
3851
ksz_get_gbit(struct ksz_device * dev,int port)3852 bool ksz_get_gbit(struct ksz_device *dev, int port)
3853 {
3854 const u8 *bitval = dev->info->xmii_ctrl1;
3855 const u16 *regs = dev->info->regs;
3856 bool gbit = false;
3857 u8 data8;
3858 bool val;
3859
3860 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3861
3862 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3863
3864 if (val == bitval[P_GMII_1GBIT])
3865 gbit = true;
3866
3867 return gbit;
3868 }
3869
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)3870 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3871 {
3872 const u8 *bitval = dev->info->xmii_ctrl1;
3873 const u16 *regs = dev->info->regs;
3874 u8 data8;
3875
3876 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3877
3878 data8 &= ~P_GMII_1GBIT_M;
3879
3880 if (gbit)
3881 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3882 else
3883 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3884
3885 /* Write the updated value */
3886 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3887 }
3888
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)3889 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3890 {
3891 const u8 *bitval = dev->info->xmii_ctrl0;
3892 const u16 *regs = dev->info->regs;
3893 u8 data8;
3894
3895 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3896
3897 data8 &= ~P_MII_100MBIT_M;
3898
3899 if (speed == SPEED_100)
3900 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3901 else
3902 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3903
3904 /* Write the updated value */
3905 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3906 }
3907
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)3908 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3909 {
3910 if (speed == SPEED_1000)
3911 ksz_set_gbit(dev, port, true);
3912 else
3913 ksz_set_gbit(dev, port, false);
3914
3915 if (speed == SPEED_100 || speed == SPEED_10)
3916 ksz_set_100_10mbit(dev, port, speed);
3917 }
3918
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)3919 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3920 bool tx_pause, bool rx_pause)
3921 {
3922 const u8 *bitval = dev->info->xmii_ctrl0;
3923 const u32 *masks = dev->info->masks;
3924 const u16 *regs = dev->info->regs;
3925 u8 mask;
3926 u8 val;
3927
3928 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3929 masks[P_MII_RX_FLOW_CTRL];
3930
3931 if (duplex == DUPLEX_FULL)
3932 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3933 else
3934 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3935
3936 if (tx_pause)
3937 val |= masks[P_MII_TX_FLOW_CTRL];
3938
3939 if (rx_pause)
3940 val |= masks[P_MII_RX_FLOW_CTRL];
3941
3942 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3943 }
3944
ksz9477_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)3945 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3946 struct phy_device *phydev,
3947 unsigned int mode,
3948 phy_interface_t interface,
3949 int speed, int duplex, bool tx_pause,
3950 bool rx_pause)
3951 {
3952 struct dsa_port *dp = dsa_phylink_to_port(config);
3953 struct ksz_device *dev = dp->ds->priv;
3954 int port = dp->index;
3955 struct ksz_port *p;
3956
3957 p = &dev->ports[port];
3958
3959 /* Internal PHYs */
3960 if (dev->info->internal_phy[port])
3961 return;
3962
3963 p->phydev.speed = speed;
3964
3965 ksz_port_set_xmii_speed(dev, port, speed);
3966
3967 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3968 }
3969
ksz_switch_detect(struct ksz_device * dev)3970 static int ksz_switch_detect(struct ksz_device *dev)
3971 {
3972 u8 id1, id2, id4;
3973 u16 id16;
3974 u32 id32;
3975 int ret;
3976
3977 /* read chip id */
3978 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3979 if (ret)
3980 return ret;
3981
3982 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3983 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3984
3985 switch (id1) {
3986 case KSZ84_FAMILY_ID:
3987 dev->chip_id = KSZ8463_CHIP_ID;
3988 break;
3989 case KSZ87_FAMILY_ID:
3990 if (id2 == KSZ87_CHIP_ID_95) {
3991 u8 val;
3992
3993 dev->chip_id = KSZ8795_CHIP_ID;
3994
3995 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3996 if (val & KSZ8_PORT_FIBER_MODE)
3997 dev->chip_id = KSZ8765_CHIP_ID;
3998 } else if (id2 == KSZ87_CHIP_ID_94) {
3999 dev->chip_id = KSZ8794_CHIP_ID;
4000 } else {
4001 return -ENODEV;
4002 }
4003 break;
4004 case KSZ88_FAMILY_ID:
4005 if (id2 == KSZ88_CHIP_ID_63)
4006 dev->chip_id = KSZ88X3_CHIP_ID;
4007 else
4008 return -ENODEV;
4009 break;
4010 case KSZ8895_FAMILY_ID:
4011 if (id2 == KSZ8895_CHIP_ID_95 ||
4012 id2 == KSZ8895_CHIP_ID_95R)
4013 dev->chip_id = KSZ8895_CHIP_ID;
4014 else
4015 return -ENODEV;
4016 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4);
4017 if (ret)
4018 return ret;
4019 if (id4 & SW_KSZ8864)
4020 dev->chip_id = KSZ8864_CHIP_ID;
4021 break;
4022 default:
4023 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
4024 if (ret)
4025 return ret;
4026
4027 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
4028 id32 &= ~0xFF;
4029
4030 switch (id32) {
4031 case KSZ9477_CHIP_ID:
4032 case KSZ9896_CHIP_ID:
4033 case KSZ9897_CHIP_ID:
4034 case KSZ9567_CHIP_ID:
4035 case KSZ8567_CHIP_ID:
4036 case LAN9370_CHIP_ID:
4037 case LAN9371_CHIP_ID:
4038 case LAN9372_CHIP_ID:
4039 case LAN9373_CHIP_ID:
4040 case LAN9374_CHIP_ID:
4041
4042 /* LAN9646 does not have its own chip id. */
4043 if (dev->chip_id != LAN9646_CHIP_ID)
4044 dev->chip_id = id32;
4045 break;
4046 case KSZ9893_CHIP_ID:
4047 ret = ksz_read8(dev, REG_CHIP_ID4,
4048 &id4);
4049 if (ret)
4050 return ret;
4051
4052 if (id4 == SKU_ID_KSZ8563)
4053 dev->chip_id = KSZ8563_CHIP_ID;
4054 else if (id4 == SKU_ID_KSZ9563)
4055 dev->chip_id = KSZ9563_CHIP_ID;
4056 else
4057 dev->chip_id = KSZ9893_CHIP_ID;
4058
4059 break;
4060 default:
4061 dev_err(dev->dev,
4062 "unsupported switch detected %x)\n", id32);
4063 return -ENODEV;
4064 }
4065 }
4066 return 0;
4067 }
4068
ksz_cls_flower_add(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)4069 static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
4070 struct flow_cls_offload *cls, bool ingress)
4071 {
4072 struct ksz_device *dev = ds->priv;
4073
4074 switch (dev->chip_id) {
4075 case KSZ8563_CHIP_ID:
4076 case KSZ8567_CHIP_ID:
4077 case KSZ9477_CHIP_ID:
4078 case KSZ9563_CHIP_ID:
4079 case KSZ9567_CHIP_ID:
4080 case KSZ9893_CHIP_ID:
4081 case KSZ9896_CHIP_ID:
4082 case KSZ9897_CHIP_ID:
4083 case LAN9646_CHIP_ID:
4084 return ksz9477_cls_flower_add(ds, port, cls, ingress);
4085 }
4086
4087 return -EOPNOTSUPP;
4088 }
4089
ksz_cls_flower_del(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)4090 static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
4091 struct flow_cls_offload *cls, bool ingress)
4092 {
4093 struct ksz_device *dev = ds->priv;
4094
4095 switch (dev->chip_id) {
4096 case KSZ8563_CHIP_ID:
4097 case KSZ8567_CHIP_ID:
4098 case KSZ9477_CHIP_ID:
4099 case KSZ9563_CHIP_ID:
4100 case KSZ9567_CHIP_ID:
4101 case KSZ9893_CHIP_ID:
4102 case KSZ9896_CHIP_ID:
4103 case KSZ9897_CHIP_ID:
4104 case LAN9646_CHIP_ID:
4105 return ksz9477_cls_flower_del(ds, port, cls, ingress);
4106 }
4107
4108 return -EOPNOTSUPP;
4109 }
4110
4111 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
4112 * is converted to Hex-decimal using the successive multiplication method. On
4113 * every step, integer part is taken and decimal part is carry forwarded.
4114 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)4115 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
4116 {
4117 u32 cinc = 0;
4118 u32 txrate;
4119 u32 rate;
4120 u8 temp;
4121 u8 i;
4122
4123 txrate = idle_slope - send_slope;
4124
4125 if (!txrate)
4126 return -EINVAL;
4127
4128 rate = idle_slope;
4129
4130 /* 24 bit register */
4131 for (i = 0; i < 6; i++) {
4132 rate = rate * 16;
4133
4134 temp = rate / txrate;
4135
4136 rate %= txrate;
4137
4138 cinc = ((cinc << 4) | temp);
4139 }
4140
4141 *bw = cinc;
4142
4143 return 0;
4144 }
4145
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)4146 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
4147 u8 shaper)
4148 {
4149 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
4150 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
4151 FIELD_PREP(MTI_SHAPING_M, shaper));
4152 }
4153
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)4154 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
4155 struct tc_cbs_qopt_offload *qopt)
4156 {
4157 struct ksz_device *dev = ds->priv;
4158 int ret;
4159 u32 bw;
4160
4161 if (!dev->info->tc_cbs_supported)
4162 return -EOPNOTSUPP;
4163
4164 if (qopt->queue > dev->info->num_tx_queues)
4165 return -EINVAL;
4166
4167 /* Queue Selection */
4168 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
4169 if (ret)
4170 return ret;
4171
4172 if (!qopt->enable)
4173 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4174 MTI_SHAPING_OFF);
4175
4176 /* High Credit */
4177 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
4178 qopt->hicredit);
4179 if (ret)
4180 return ret;
4181
4182 /* Low Credit */
4183 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
4184 qopt->locredit);
4185 if (ret)
4186 return ret;
4187
4188 /* Credit Increment Register */
4189 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
4190 if (ret)
4191 return ret;
4192
4193 if (dev->dev_ops->tc_cbs_set_cinc) {
4194 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
4195 if (ret)
4196 return ret;
4197 }
4198
4199 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4200 MTI_SHAPING_SRP);
4201 }
4202
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)4203 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
4204 {
4205 int queue, ret;
4206
4207 /* Configuration will not take effect until the last Port Queue X
4208 * Egress Limit Control Register is written.
4209 */
4210 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4211 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
4212 KSZ9477_OUT_RATE_NO_LIMIT);
4213 if (ret)
4214 return ret;
4215 }
4216
4217 return 0;
4218 }
4219
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)4220 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
4221 int band)
4222 {
4223 /* Compared to queues, bands prioritize packets differently. In strict
4224 * priority mode, the lowest priority is assigned to Queue 0 while the
4225 * highest priority is given to Band 0.
4226 */
4227 return p->bands - 1 - band;
4228 }
4229
ksz8463_tc_ctrl(int port,int queue)4230 static u8 ksz8463_tc_ctrl(int port, int queue)
4231 {
4232 u8 reg;
4233
4234 reg = 0xC8 + port * 4;
4235 reg += ((3 - queue) / 2) * 2;
4236 reg++;
4237 reg -= (queue & 1);
4238 return reg;
4239 }
4240
4241 /**
4242 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection)
4243 * for a port on KSZ88x3 switch
4244 * @dev: Pointer to the KSZ switch device structure
4245 * @port: Port number to configure
4246 * @p: Pointer to offload replace parameters describing ETS bands and mapping
4247 *
4248 * The KSZ88x3 supports two scheduling modes: Strict Priority and
4249 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior:
4250 * - No configurable queue-to-priority mapping
4251 * - No weight adjustment in WFQ mode
4252 *
4253 * This function configures the switch to use strict priority mode by
4254 * clearing the WFQ enable bit for all queues associated with ETS bands.
4255 * If strict priority is not explicitly requested, the switch will default
4256 * to WFQ mode.
4257 *
4258 * Return: 0 on success, or a negative error code on failure
4259 */
ksz88x3_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4260 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port,
4261 struct tc_ets_qopt_offload_replace_params *p)
4262 {
4263 int ret, band;
4264
4265 /* Only strict priority mode is supported for now.
4266 * WFQ is implicitly enabled when strict mode is disabled.
4267 */
4268 for (band = 0; band < p->bands; band++) {
4269 int queue = ksz_ets_band_to_queue(p, band);
4270 u8 reg;
4271
4272 /* Calculate TXQ Split Control register address for this
4273 * port/queue
4274 */
4275 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4276 if (ksz_is_ksz8463(dev))
4277 reg = ksz8463_tc_ctrl(port, queue);
4278
4279 /* Clear WFQ enable bit to select strict priority scheduling */
4280 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0);
4281 if (ret)
4282 return ret;
4283 }
4284
4285 return 0;
4286 }
4287
4288 /**
4289 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config
4290 * for a port on KSZ88x3 switch
4291 * @dev: Pointer to the KSZ switch device structure
4292 * @port: Port number to reset
4293 *
4294 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or
4295 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or
4296 * queue mapping. This function resets the port’s scheduling mode to
4297 * the default, which is WFQ, by enabling the WFQ bit for all queues.
4298 *
4299 * Return: 0 on success, or a negative error code on failure
4300 */
ksz88x3_tc_ets_del(struct ksz_device * dev,int port)4301 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port)
4302 {
4303 int ret, queue;
4304
4305 /* Iterate over all transmit queues for this port */
4306 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4307 u8 reg;
4308
4309 /* Calculate TXQ Split Control register address for this
4310 * port/queue
4311 */
4312 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4313 if (ksz_is_ksz8463(dev))
4314 reg = ksz8463_tc_ctrl(port, queue);
4315
4316 /* Set WFQ enable bit to revert back to default scheduling
4317 * mode
4318 */
4319 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE,
4320 KSZ8873_TXQ_WFQ_ENABLE);
4321 if (ret)
4322 return ret;
4323 }
4324
4325 return 0;
4326 }
4327
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)4328 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4329 {
4330 int ret;
4331
4332 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4333 if (ret)
4334 return ret;
4335
4336 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4337 MTI_SHAPING_OFF);
4338 }
4339
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)4340 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4341 int weight)
4342 {
4343 int ret;
4344
4345 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4346 if (ret)
4347 return ret;
4348
4349 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4350 MTI_SHAPING_OFF);
4351 if (ret)
4352 return ret;
4353
4354 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
4355 }
4356
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4357 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4358 struct tc_ets_qopt_offload_replace_params *p)
4359 {
4360 int ret, band, tc_prio;
4361 u32 queue_map = 0;
4362
4363 /* In order to ensure proper prioritization, it is necessary to set the
4364 * rate limit for the related queue to zero. Otherwise strict priority
4365 * or WRR mode will not work. This is a hardware limitation.
4366 */
4367 ret = ksz_disable_egress_rate_limit(dev, port);
4368 if (ret)
4369 return ret;
4370
4371 /* Configure queue scheduling mode for all bands. Currently only strict
4372 * prio mode is supported.
4373 */
4374 for (band = 0; band < p->bands; band++) {
4375 int queue = ksz_ets_band_to_queue(p, band);
4376
4377 ret = ksz_queue_set_strict(dev, port, queue);
4378 if (ret)
4379 return ret;
4380 }
4381
4382 /* Configure the mapping between traffic classes and queues. Note:
4383 * priomap variable support 16 traffic classes, but the chip can handle
4384 * only 8 classes.
4385 */
4386 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4387 int queue;
4388
4389 if (tc_prio >= dev->info->num_ipms)
4390 break;
4391
4392 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
4393 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4394 }
4395
4396 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
4397 }
4398
ksz_tc_ets_del(struct ksz_device * dev,int port)4399 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4400 {
4401 int ret, queue;
4402
4403 /* To restore the default chip configuration, set all queues to use the
4404 * WRR scheduler with a weight of 1.
4405 */
4406 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4407 ret = ksz_queue_set_wrr(dev, port, queue,
4408 KSZ9477_DEFAULT_WRR_WEIGHT);
4409
4410 if (ret)
4411 return ret;
4412 }
4413
4414 /* Revert the queue mapping for TC-priority to its default setting on
4415 * the chip.
4416 */
4417 return ksz9477_set_default_prio_queue_mapping(dev, port);
4418 }
4419
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4420 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4421 struct tc_ets_qopt_offload_replace_params *p)
4422 {
4423 int band;
4424
4425 /* Since it is not feasible to share one port among multiple qdisc,
4426 * the user must configure all available queues appropriately.
4427 */
4428 if (p->bands != dev->info->num_tx_queues) {
4429 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4430 dev->info->num_tx_queues);
4431 return -EOPNOTSUPP;
4432 }
4433
4434 for (band = 0; band < p->bands; ++band) {
4435 /* The KSZ switches utilize a weighted round robin configuration
4436 * where a certain number of packets can be transmitted from a
4437 * queue before the next queue is serviced. For more information
4438 * on this, refer to section 5.2.8.4 of the KSZ8565R
4439 * documentation on the Port Transmit Queue Control 1 Register.
4440 * However, the current ETS Qdisc implementation (as of February
4441 * 2023) assigns a weight to each queue based on the number of
4442 * bytes or extrapolated bandwidth in percentages. Since this
4443 * differs from the KSZ switches' method and we don't want to
4444 * fake support by converting bytes to packets, it is better to
4445 * return an error instead.
4446 */
4447 if (p->quanta[band]) {
4448 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4449 return -EOPNOTSUPP;
4450 }
4451 }
4452
4453 return 0;
4454 }
4455
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)4456 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4457 struct tc_ets_qopt_offload *qopt)
4458 {
4459 struct ksz_device *dev = ds->priv;
4460 int ret;
4461
4462 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)))
4463 return -EOPNOTSUPP;
4464
4465 if (qopt->parent != TC_H_ROOT) {
4466 dev_err(dev->dev, "Parent should be \"root\"\n");
4467 return -EOPNOTSUPP;
4468 }
4469
4470 switch (qopt->command) {
4471 case TC_ETS_REPLACE:
4472 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
4473 if (ret)
4474 return ret;
4475
4476 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4477 return ksz88x3_tc_ets_add(dev, port,
4478 &qopt->replace_params);
4479 else
4480 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
4481 case TC_ETS_DESTROY:
4482 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4483 return ksz88x3_tc_ets_del(dev, port);
4484 else
4485 return ksz_tc_ets_del(dev, port);
4486 case TC_ETS_STATS:
4487 case TC_ETS_GRAFT:
4488 return -EOPNOTSUPP;
4489 }
4490
4491 return -EOPNOTSUPP;
4492 }
4493
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)4494 static int ksz_setup_tc(struct dsa_switch *ds, int port,
4495 enum tc_setup_type type, void *type_data)
4496 {
4497 switch (type) {
4498 case TC_SETUP_QDISC_CBS:
4499 return ksz_setup_tc_cbs(ds, port, type_data);
4500 case TC_SETUP_QDISC_ETS:
4501 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
4502 default:
4503 return -EOPNOTSUPP;
4504 }
4505 }
4506
4507 /**
4508 * ksz_handle_wake_reason - Handle wake reason on a specified port.
4509 * @dev: The device structure.
4510 * @port: The port number.
4511 *
4512 * This function reads the PME (Power Management Event) status register of a
4513 * specified port to determine the wake reason. If there is no wake event, it
4514 * returns early. Otherwise, it logs the wake reason which could be due to a
4515 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4516 * is then cleared to acknowledge the handling of the wake event.
4517 *
4518 * Return: 0 on success, or an error code on failure.
4519 */
ksz_handle_wake_reason(struct ksz_device * dev,int port)4520 int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4521 {
4522 const struct ksz_dev_ops *ops = dev->dev_ops;
4523 const u16 *regs = dev->info->regs;
4524 u8 pme_status;
4525 int ret;
4526
4527 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4528 &pme_status);
4529 if (ret)
4530 return ret;
4531
4532 if (!pme_status)
4533 return 0;
4534
4535 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4536 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4537 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4538 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4539
4540 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4541 pme_status);
4542 }
4543
4544 /**
4545 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4546 * @ds: The dsa_switch structure.
4547 * @port: The port number.
4548 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4549 *
4550 * This function checks the device PME wakeup_source flag and chip_id.
4551 * If enabled and supported, it sets the supported and active WoL
4552 * flags.
4553 */
ksz_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4554 static void ksz_get_wol(struct dsa_switch *ds, int port,
4555 struct ethtool_wolinfo *wol)
4556 {
4557 struct ksz_device *dev = ds->priv;
4558 const u16 *regs = dev->info->regs;
4559 u8 pme_ctrl;
4560 int ret;
4561
4562 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4563 return;
4564
4565 if (!dev->wakeup_source)
4566 return;
4567
4568 wol->supported = WAKE_PHY;
4569
4570 /* Check if the current MAC address on this port can be set
4571 * as global for WAKE_MAGIC support. The result may vary
4572 * dynamically based on other ports configurations.
4573 */
4574 if (ksz_is_port_mac_global_usable(dev->ds, port))
4575 wol->supported |= WAKE_MAGIC;
4576
4577 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4578 &pme_ctrl);
4579 if (ret)
4580 return;
4581
4582 if (pme_ctrl & PME_WOL_MAGICPKT)
4583 wol->wolopts |= WAKE_MAGIC;
4584 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4585 wol->wolopts |= WAKE_PHY;
4586 }
4587
4588 /**
4589 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4590 * @ds: The dsa_switch structure.
4591 * @port: The port number.
4592 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4593 *
4594 * This function configures Wake-on-LAN (WoL) settings for a specified
4595 * port. It validates the provided WoL options, checks if PME is
4596 * enabled and supported, clears any previous wake reasons, and sets
4597 * the Magic Packet flag in the port's PME control register if
4598 * specified.
4599 *
4600 * Return: 0 on success, or other error codes on failure.
4601 */
ksz_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4602 static int ksz_set_wol(struct dsa_switch *ds, int port,
4603 struct ethtool_wolinfo *wol)
4604 {
4605 u8 pme_ctrl = 0, pme_ctrl_old = 0;
4606 struct ksz_device *dev = ds->priv;
4607 const u16 *regs = dev->info->regs;
4608 bool magic_switched_off;
4609 bool magic_switched_on;
4610 int ret;
4611
4612 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4613 return -EINVAL;
4614
4615 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4616 return -EOPNOTSUPP;
4617
4618 if (!dev->wakeup_source)
4619 return -EOPNOTSUPP;
4620
4621 ret = ksz_handle_wake_reason(dev, port);
4622 if (ret)
4623 return ret;
4624
4625 if (wol->wolopts & WAKE_MAGIC)
4626 pme_ctrl |= PME_WOL_MAGICPKT;
4627 if (wol->wolopts & WAKE_PHY)
4628 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4629
4630 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4631 &pme_ctrl_old);
4632 if (ret)
4633 return ret;
4634
4635 if (pme_ctrl_old == pme_ctrl)
4636 return 0;
4637
4638 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4639 !(pme_ctrl & PME_WOL_MAGICPKT);
4640 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4641 (pme_ctrl & PME_WOL_MAGICPKT);
4642
4643 /* To keep reference count of MAC address, we should do this
4644 * operation only on change of WOL settings.
4645 */
4646 if (magic_switched_on) {
4647 ret = ksz_switch_macaddr_get(dev->ds, port, NULL);
4648 if (ret)
4649 return ret;
4650 } else if (magic_switched_off) {
4651 ksz_switch_macaddr_put(dev->ds);
4652 }
4653
4654 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4655 pme_ctrl);
4656 if (ret) {
4657 if (magic_switched_on)
4658 ksz_switch_macaddr_put(dev->ds);
4659 return ret;
4660 }
4661
4662 return 0;
4663 }
4664
4665 /**
4666 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4667 * considering Wake-on-LAN (WoL) settings.
4668 * @dev: The switch device structure.
4669 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4670 * enabled on any port.
4671 *
4672 * This function prepares the switch device for a safe shutdown while taking
4673 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4674 * the wol_enabled flag accordingly to reflect whether WoL is active on any
4675 * port.
4676 */
ksz_wol_pre_shutdown(struct ksz_device * dev,bool * wol_enabled)4677 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4678 {
4679 const struct ksz_dev_ops *ops = dev->dev_ops;
4680 const u16 *regs = dev->info->regs;
4681 u8 pme_pin_en = PME_ENABLE;
4682 struct dsa_port *dp;
4683 int ret;
4684
4685 *wol_enabled = false;
4686
4687 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4688 return;
4689
4690 if (!dev->wakeup_source)
4691 return;
4692
4693 dsa_switch_for_each_user_port(dp, dev->ds) {
4694 u8 pme_ctrl = 0;
4695
4696 ret = ops->pme_pread8(dev, dp->index,
4697 regs[REG_PORT_PME_CTRL], &pme_ctrl);
4698 if (!ret && pme_ctrl)
4699 *wol_enabled = true;
4700
4701 /* make sure there are no pending wake events which would
4702 * prevent the device from going to sleep/shutdown.
4703 */
4704 ksz_handle_wake_reason(dev, dp->index);
4705 }
4706
4707 /* Now we are save to enable PME pin. */
4708 if (*wol_enabled) {
4709 if (dev->pme_active_high)
4710 pme_pin_en |= PME_POLARITY;
4711 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4712 if (ksz_is_ksz87xx(dev))
4713 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4714 }
4715 }
4716
ksz_port_set_mac_address(struct dsa_switch * ds,int port,const unsigned char * addr)4717 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4718 const unsigned char *addr)
4719 {
4720 struct dsa_port *dp = dsa_to_port(ds, port);
4721 struct ethtool_wolinfo wol;
4722
4723 if (dp->hsr_dev) {
4724 dev_err(ds->dev,
4725 "Cannot change MAC address on port %d with active HSR offload\n",
4726 port);
4727 return -EBUSY;
4728 }
4729
4730 /* Need to initialize variable as the code to fill in settings may
4731 * not be executed.
4732 */
4733 wol.wolopts = 0;
4734
4735 ksz_get_wol(ds, dp->index, &wol);
4736 if (wol.wolopts & WAKE_MAGIC) {
4737 dev_err(ds->dev,
4738 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4739 port);
4740 return -EBUSY;
4741 }
4742
4743 return 0;
4744 }
4745
4746 /**
4747 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4748 * can be used as a global address.
4749 * @ds: Pointer to the DSA switch structure.
4750 * @port: The port number on which the MAC address is to be checked.
4751 *
4752 * This function examines the MAC address set on the specified port and
4753 * determines if it can be used as a global address for the switch.
4754 *
4755 * Return: true if the port's MAC address can be used as a global address, false
4756 * otherwise.
4757 */
ksz_is_port_mac_global_usable(struct dsa_switch * ds,int port)4758 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4759 {
4760 struct net_device *user = dsa_to_port(ds, port)->user;
4761 const unsigned char *addr = user->dev_addr;
4762 struct ksz_switch_macaddr *switch_macaddr;
4763 struct ksz_device *dev = ds->priv;
4764
4765 ASSERT_RTNL();
4766
4767 switch_macaddr = dev->switch_macaddr;
4768 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
4769 return false;
4770
4771 return true;
4772 }
4773
4774 /**
4775 * ksz_switch_macaddr_get - Program the switch's MAC address register.
4776 * @ds: DSA switch instance.
4777 * @port: Port number.
4778 * @extack: Netlink extended acknowledgment.
4779 *
4780 * This function programs the switch's MAC address register with the MAC address
4781 * of the requesting user port. This single address is used by the switch for
4782 * multiple features like HSR self-address filtering and WoL. Other user ports
4783 * can share ownership of this address as long as their MAC address is the same.
4784 * The MAC addresses of user ports must not change while they have ownership of
4785 * the switch MAC address.
4786 *
4787 * Return: 0 on success, or other error codes on failure.
4788 */
ksz_switch_macaddr_get(struct dsa_switch * ds,int port,struct netlink_ext_ack * extack)4789 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4790 struct netlink_ext_ack *extack)
4791 {
4792 struct net_device *user = dsa_to_port(ds, port)->user;
4793 const unsigned char *addr = user->dev_addr;
4794 struct ksz_switch_macaddr *switch_macaddr;
4795 struct ksz_device *dev = ds->priv;
4796 const u16 *regs = dev->info->regs;
4797 int i, ret;
4798
4799 /* Make sure concurrent MAC address changes are blocked */
4800 ASSERT_RTNL();
4801
4802 switch_macaddr = dev->switch_macaddr;
4803 if (switch_macaddr) {
4804 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
4805 NL_SET_ERR_MSG_FMT_MOD(extack,
4806 "Switch already configured for MAC address %pM",
4807 switch_macaddr->addr);
4808 return -EBUSY;
4809 }
4810
4811 refcount_inc(&switch_macaddr->refcount);
4812 return 0;
4813 }
4814
4815 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4816 if (!switch_macaddr)
4817 return -ENOMEM;
4818
4819 ether_addr_copy(switch_macaddr->addr, addr);
4820 refcount_set(&switch_macaddr->refcount, 1);
4821 dev->switch_macaddr = switch_macaddr;
4822
4823 /* Program the switch MAC address to hardware */
4824 for (i = 0; i < ETH_ALEN; i++) {
4825 if (ksz_is_ksz8463(dev)) {
4826 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1];
4827
4828 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i,
4829 addr16);
4830 i++;
4831 } else {
4832 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i,
4833 addr[i]);
4834 }
4835 if (ret)
4836 goto macaddr_drop;
4837 }
4838
4839 return 0;
4840
4841 macaddr_drop:
4842 dev->switch_macaddr = NULL;
4843 refcount_set(&switch_macaddr->refcount, 0);
4844 kfree(switch_macaddr);
4845
4846 return ret;
4847 }
4848
ksz_switch_macaddr_put(struct dsa_switch * ds)4849 void ksz_switch_macaddr_put(struct dsa_switch *ds)
4850 {
4851 struct ksz_switch_macaddr *switch_macaddr;
4852 struct ksz_device *dev = ds->priv;
4853 const u16 *regs = dev->info->regs;
4854 int i;
4855
4856 /* Make sure concurrent MAC address changes are blocked */
4857 ASSERT_RTNL();
4858
4859 switch_macaddr = dev->switch_macaddr;
4860 if (!refcount_dec_and_test(&switch_macaddr->refcount))
4861 return;
4862
4863 for (i = 0; i < ETH_ALEN; i++)
4864 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
4865
4866 dev->switch_macaddr = NULL;
4867 kfree(switch_macaddr);
4868 }
4869
ksz_hsr_join(struct dsa_switch * ds,int port,struct net_device * hsr,struct netlink_ext_ack * extack)4870 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4871 struct netlink_ext_ack *extack)
4872 {
4873 struct ksz_device *dev = ds->priv;
4874 enum hsr_version ver;
4875 int ret;
4876
4877 ret = hsr_get_version(hsr, &ver);
4878 if (ret)
4879 return ret;
4880
4881 if (dev->chip_id != KSZ9477_CHIP_ID) {
4882 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4883 return -EOPNOTSUPP;
4884 }
4885
4886 /* KSZ9477 can support HW offloading of only 1 HSR device */
4887 if (dev->hsr_dev && hsr != dev->hsr_dev) {
4888 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4889 return -EOPNOTSUPP;
4890 }
4891
4892 /* KSZ9477 only supports HSR v0 and v1 */
4893 if (!(ver == HSR_V0 || ver == HSR_V1)) {
4894 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4895 return -EOPNOTSUPP;
4896 }
4897
4898 /* KSZ9477 can only perform HSR offloading for up to two ports */
4899 if (hweight8(dev->hsr_ports) >= 2) {
4900 NL_SET_ERR_MSG_MOD(extack,
4901 "Cannot offload more than two ports - using software HSR");
4902 return -EOPNOTSUPP;
4903 }
4904
4905 /* Self MAC address filtering, to avoid frames traversing
4906 * the HSR ring more than once.
4907 */
4908 ret = ksz_switch_macaddr_get(ds, port, extack);
4909 if (ret)
4910 return ret;
4911
4912 ksz9477_hsr_join(ds, port, hsr);
4913 dev->hsr_dev = hsr;
4914 dev->hsr_ports |= BIT(port);
4915
4916 return 0;
4917 }
4918
ksz_hsr_leave(struct dsa_switch * ds,int port,struct net_device * hsr)4919 static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4920 struct net_device *hsr)
4921 {
4922 struct ksz_device *dev = ds->priv;
4923
4924 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4925
4926 ksz9477_hsr_leave(ds, port, hsr);
4927 dev->hsr_ports &= ~BIT(port);
4928 if (!dev->hsr_ports)
4929 dev->hsr_dev = NULL;
4930
4931 ksz_switch_macaddr_put(ds);
4932
4933 return 0;
4934 }
4935
ksz_suspend(struct dsa_switch * ds)4936 static int ksz_suspend(struct dsa_switch *ds)
4937 {
4938 struct ksz_device *dev = ds->priv;
4939
4940 cancel_delayed_work_sync(&dev->mib_read);
4941 return 0;
4942 }
4943
ksz_resume(struct dsa_switch * ds)4944 static int ksz_resume(struct dsa_switch *ds)
4945 {
4946 struct ksz_device *dev = ds->priv;
4947
4948 if (dev->mib_read_interval)
4949 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
4950 return 0;
4951 }
4952
4953 static const struct dsa_switch_ops ksz_switch_ops = {
4954 .get_tag_protocol = ksz_get_tag_protocol,
4955 .connect_tag_protocol = ksz_connect_tag_protocol,
4956 .get_phy_flags = ksz_get_phy_flags,
4957 .setup = ksz_setup,
4958 .teardown = ksz_teardown,
4959 .phy_read = ksz_phy_read16,
4960 .phy_write = ksz_phy_write16,
4961 .phylink_get_caps = ksz_phylink_get_caps,
4962 .port_setup = ksz_port_setup,
4963 .set_ageing_time = ksz_set_ageing_time,
4964 .get_strings = ksz_get_strings,
4965 .get_ethtool_stats = ksz_get_ethtool_stats,
4966 .get_sset_count = ksz_sset_count,
4967 .port_bridge_join = ksz_port_bridge_join,
4968 .port_bridge_leave = ksz_port_bridge_leave,
4969 .port_hsr_join = ksz_hsr_join,
4970 .port_hsr_leave = ksz_hsr_leave,
4971 .port_set_mac_address = ksz_port_set_mac_address,
4972 .port_stp_state_set = ksz_port_stp_state_set,
4973 .port_teardown = ksz_port_teardown,
4974 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4975 .port_bridge_flags = ksz_port_bridge_flags,
4976 .port_fast_age = ksz_port_fast_age,
4977 .port_vlan_filtering = ksz_port_vlan_filtering,
4978 .port_vlan_add = ksz_port_vlan_add,
4979 .port_vlan_del = ksz_port_vlan_del,
4980 .port_fdb_dump = ksz_port_fdb_dump,
4981 .port_fdb_add = ksz_port_fdb_add,
4982 .port_fdb_del = ksz_port_fdb_del,
4983 .port_mdb_add = ksz_port_mdb_add,
4984 .port_mdb_del = ksz_port_mdb_del,
4985 .port_mirror_add = ksz_port_mirror_add,
4986 .port_mirror_del = ksz_port_mirror_del,
4987 .get_stats64 = ksz_get_stats64,
4988 .get_pause_stats = ksz_get_pause_stats,
4989 .port_change_mtu = ksz_change_mtu,
4990 .port_max_mtu = ksz_max_mtu,
4991 .get_wol = ksz_get_wol,
4992 .set_wol = ksz_set_wol,
4993 .suspend = ksz_suspend,
4994 .resume = ksz_resume,
4995 .get_ts_info = ksz_get_ts_info,
4996 .port_hwtstamp_get = ksz_hwtstamp_get,
4997 .port_hwtstamp_set = ksz_hwtstamp_set,
4998 .port_txtstamp = ksz_port_txtstamp,
4999 .port_rxtstamp = ksz_port_rxtstamp,
5000 .cls_flower_add = ksz_cls_flower_add,
5001 .cls_flower_del = ksz_cls_flower_del,
5002 .port_setup_tc = ksz_setup_tc,
5003 .support_eee = ksz_support_eee,
5004 .set_mac_eee = ksz_set_mac_eee,
5005 .port_get_default_prio = ksz_port_get_default_prio,
5006 .port_set_default_prio = ksz_port_set_default_prio,
5007 .port_get_dscp_prio = ksz_port_get_dscp_prio,
5008 .port_add_dscp_prio = ksz_port_add_dscp_prio,
5009 .port_del_dscp_prio = ksz_port_del_dscp_prio,
5010 .port_get_apptrust = ksz_port_get_apptrust,
5011 .port_set_apptrust = ksz_port_set_apptrust,
5012 };
5013
ksz_switch_alloc(struct device * base,void * priv)5014 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
5015 {
5016 struct dsa_switch *ds;
5017 struct ksz_device *swdev;
5018
5019 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
5020 if (!ds)
5021 return NULL;
5022
5023 ds->dev = base;
5024 ds->num_ports = DSA_MAX_PORTS;
5025 ds->ops = &ksz_switch_ops;
5026
5027 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
5028 if (!swdev)
5029 return NULL;
5030
5031 ds->priv = swdev;
5032 swdev->dev = base;
5033
5034 swdev->ds = ds;
5035 swdev->priv = priv;
5036
5037 return swdev;
5038 }
5039 EXPORT_SYMBOL(ksz_switch_alloc);
5040
5041 /**
5042 * ksz_switch_shutdown - Shutdown routine for the switch device.
5043 * @dev: The switch device structure.
5044 *
5045 * This function is responsible for initiating a shutdown sequence for the
5046 * switch device. It invokes the reset operation defined in the device
5047 * operations, if available, to reset the switch. Subsequently, it calls the
5048 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
5049 * switch.
5050 */
ksz_switch_shutdown(struct ksz_device * dev)5051 void ksz_switch_shutdown(struct ksz_device *dev)
5052 {
5053 bool wol_enabled = false;
5054
5055 ksz_wol_pre_shutdown(dev, &wol_enabled);
5056
5057 if (dev->dev_ops->reset && !wol_enabled)
5058 dev->dev_ops->reset(dev);
5059
5060 dsa_switch_shutdown(dev->ds);
5061 }
5062 EXPORT_SYMBOL(ksz_switch_shutdown);
5063
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)5064 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
5065 struct device_node *port_dn)
5066 {
5067 phy_interface_t phy_mode = dev->ports[port_num].interface;
5068 int rx_delay = -1, tx_delay = -1;
5069
5070 if (!phy_interface_mode_is_rgmii(phy_mode))
5071 return;
5072
5073 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
5074 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
5075
5076 if (rx_delay == -1 && tx_delay == -1) {
5077 dev_warn(dev->dev,
5078 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
5079 "please update device tree to specify \"rx-internal-delay-ps\" and "
5080 "\"tx-internal-delay-ps\"",
5081 port_num);
5082
5083 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
5084 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5085 rx_delay = 2000;
5086
5087 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
5088 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5089 tx_delay = 2000;
5090 }
5091
5092 if (rx_delay < 0)
5093 rx_delay = 0;
5094 if (tx_delay < 0)
5095 tx_delay = 0;
5096
5097 dev->ports[port_num].rgmii_rx_val = rx_delay;
5098 dev->ports[port_num].rgmii_tx_val = tx_delay;
5099 }
5100
5101 /**
5102 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
5103 * register value.
5104 * @array: The array of drive strength values to search.
5105 * @array_size: The size of the array.
5106 * @microamp: The drive strength value in microamp to be converted.
5107 *
5108 * This function searches the array of drive strength values for the given
5109 * microamp value and returns the corresponding register value for that drive.
5110 *
5111 * Returns: If found, the corresponding register value for that drive strength
5112 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
5113 */
ksz_drive_strength_to_reg(const struct ksz_drive_strength * array,size_t array_size,int microamp)5114 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
5115 size_t array_size, int microamp)
5116 {
5117 int i;
5118
5119 for (i = 0; i < array_size; i++) {
5120 if (array[i].microamp == microamp)
5121 return array[i].reg_val;
5122 }
5123
5124 return -EINVAL;
5125 }
5126
5127 /**
5128 * ksz_drive_strength_error() - Report invalid drive strength value
5129 * @dev: ksz device
5130 * @array: The array of drive strength values to search.
5131 * @array_size: The size of the array.
5132 * @microamp: Invalid drive strength value in microamp
5133 *
5134 * This function logs an error message when an unsupported drive strength value
5135 * is detected. It lists out all the supported drive strength values for
5136 * reference in the error message.
5137 */
ksz_drive_strength_error(struct ksz_device * dev,const struct ksz_drive_strength * array,size_t array_size,int microamp)5138 static void ksz_drive_strength_error(struct ksz_device *dev,
5139 const struct ksz_drive_strength *array,
5140 size_t array_size, int microamp)
5141 {
5142 char supported_values[100];
5143 size_t remaining_size;
5144 int added_len;
5145 char *ptr;
5146 int i;
5147
5148 remaining_size = sizeof(supported_values);
5149 ptr = supported_values;
5150
5151 for (i = 0; i < array_size; i++) {
5152 added_len = snprintf(ptr, remaining_size,
5153 i == 0 ? "%d" : ", %d", array[i].microamp);
5154
5155 if (added_len >= remaining_size)
5156 break;
5157
5158 ptr += added_len;
5159 remaining_size -= added_len;
5160 }
5161
5162 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
5163 microamp, supported_values);
5164 }
5165
5166 /**
5167 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
5168 * chip variants.
5169 * @dev: ksz device
5170 * @props: Array of drive strength properties to be applied
5171 * @num_props: Number of properties in the array
5172 *
5173 * This function configures the drive strength for various KSZ9477 chip variants
5174 * based on the provided properties. It handles chip-specific nuances and
5175 * ensures only valid drive strengths are written to the respective chip.
5176 *
5177 * Return: 0 on successful configuration, a negative error code on failure.
5178 */
ksz9477_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)5179 static int ksz9477_drive_strength_write(struct ksz_device *dev,
5180 struct ksz_driver_strength_prop *props,
5181 int num_props)
5182 {
5183 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
5184 int i, ret, reg;
5185 u8 mask = 0;
5186 u8 val = 0;
5187
5188 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
5189 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5190 props[KSZ_DRIVER_STRENGTH_IO].name);
5191
5192 if (dev->chip_id == KSZ8795_CHIP_ID ||
5193 dev->chip_id == KSZ8794_CHIP_ID ||
5194 dev->chip_id == KSZ8765_CHIP_ID)
5195 reg = KSZ8795_REG_SW_CTRL_20;
5196 else
5197 reg = KSZ9477_REG_SW_IO_STRENGTH;
5198
5199 for (i = 0; i < num_props; i++) {
5200 if (props[i].value == -1)
5201 continue;
5202
5203 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
5204 array_size, props[i].value);
5205 if (ret < 0) {
5206 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
5207 array_size, props[i].value);
5208 return ret;
5209 }
5210
5211 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
5212 val |= ret << props[i].offset;
5213 }
5214
5215 return ksz_rmw8(dev, reg, mask, val);
5216 }
5217
5218 /**
5219 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
5220 * KSZ8863 compatible chip variants.
5221 * @dev: ksz device
5222 * @props: Array of drive strength properties to be set
5223 * @num_props: Number of properties in the array
5224 *
5225 * This function applies the specified drive strength settings to KSZ88X3 chip
5226 * variants (KSZ8873, KSZ8863).
5227 * It ensures the configurations align with what the chip variant supports and
5228 * warns or errors out on unsupported settings.
5229 *
5230 * Return: 0 on success, error code otherwise
5231 */
ksz88x3_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)5232 static int ksz88x3_drive_strength_write(struct ksz_device *dev,
5233 struct ksz_driver_strength_prop *props,
5234 int num_props)
5235 {
5236 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
5237 int microamp;
5238 int i, ret;
5239
5240 for (i = 0; i < num_props; i++) {
5241 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
5242 continue;
5243
5244 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5245 props[i].name);
5246 }
5247
5248 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
5249 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size,
5250 microamp);
5251 if (ret < 0) {
5252 ksz_drive_strength_error(dev, ksz88x3_drive_strengths,
5253 array_size, microamp);
5254 return ret;
5255 }
5256
5257 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
5258 KSZ8873_DRIVE_STRENGTH_16MA, ret);
5259 }
5260
5261 /**
5262 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
5263 * from device tree properties.
5264 * @dev: ksz device
5265 *
5266 * This function reads the specified drive strength properties from the
5267 * device tree, validates against the supported chip variants, and sets
5268 * them accordingly. An error should be critical here, as the drive strength
5269 * settings are crucial for EMI compliance.
5270 *
5271 * Return: 0 on success, error code otherwise
5272 */
ksz_parse_drive_strength(struct ksz_device * dev)5273 static int ksz_parse_drive_strength(struct ksz_device *dev)
5274 {
5275 struct ksz_driver_strength_prop of_props[] = {
5276 [KSZ_DRIVER_STRENGTH_HI] = {
5277 .name = "microchip,hi-drive-strength-microamp",
5278 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
5279 .value = -1,
5280 },
5281 [KSZ_DRIVER_STRENGTH_LO] = {
5282 .name = "microchip,lo-drive-strength-microamp",
5283 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
5284 .value = -1,
5285 },
5286 [KSZ_DRIVER_STRENGTH_IO] = {
5287 .name = "microchip,io-drive-strength-microamp",
5288 .offset = 0, /* don't care */
5289 .value = -1,
5290 },
5291 };
5292 struct device_node *np = dev->dev->of_node;
5293 bool have_any_prop = false;
5294 int i, ret;
5295
5296 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5297 ret = of_property_read_u32(np, of_props[i].name,
5298 &of_props[i].value);
5299 if (ret && ret != -EINVAL)
5300 dev_warn(dev->dev, "Failed to read %s\n",
5301 of_props[i].name);
5302 if (ret)
5303 continue;
5304
5305 have_any_prop = true;
5306 }
5307
5308 if (!have_any_prop)
5309 return 0;
5310
5311 switch (dev->chip_id) {
5312 case KSZ88X3_CHIP_ID:
5313 return ksz88x3_drive_strength_write(dev, of_props,
5314 ARRAY_SIZE(of_props));
5315 case KSZ8795_CHIP_ID:
5316 case KSZ8794_CHIP_ID:
5317 case KSZ8765_CHIP_ID:
5318 case KSZ8563_CHIP_ID:
5319 case KSZ8567_CHIP_ID:
5320 case KSZ9477_CHIP_ID:
5321 case KSZ9563_CHIP_ID:
5322 case KSZ9567_CHIP_ID:
5323 case KSZ9893_CHIP_ID:
5324 case KSZ9896_CHIP_ID:
5325 case KSZ9897_CHIP_ID:
5326 case LAN9646_CHIP_ID:
5327 return ksz9477_drive_strength_write(dev, of_props,
5328 ARRAY_SIZE(of_props));
5329 default:
5330 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5331 if (of_props[i].value == -1)
5332 continue;
5333
5334 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5335 of_props[i].name);
5336 }
5337 }
5338
5339 return 0;
5340 }
5341
ksz_switch_register(struct ksz_device * dev)5342 int ksz_switch_register(struct ksz_device *dev)
5343 {
5344 const struct ksz_chip_data *info;
5345 struct device_node *ports;
5346 phy_interface_t interface;
5347 unsigned int port_num;
5348 int ret;
5349 int i;
5350
5351 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
5352 GPIOD_OUT_LOW);
5353 if (IS_ERR(dev->reset_gpio))
5354 return PTR_ERR(dev->reset_gpio);
5355
5356 if (dev->reset_gpio) {
5357 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5358 usleep_range(10000, 12000);
5359 gpiod_set_value_cansleep(dev->reset_gpio, 0);
5360 msleep(100);
5361 }
5362
5363 mutex_init(&dev->dev_mutex);
5364 mutex_init(&dev->regmap_mutex);
5365 mutex_init(&dev->alu_mutex);
5366 mutex_init(&dev->vlan_mutex);
5367
5368 ret = ksz_switch_detect(dev);
5369 if (ret)
5370 return ret;
5371
5372 info = ksz_lookup_info(dev->chip_id);
5373 if (!info)
5374 return -ENODEV;
5375
5376 /* Update the compatible info with the probed one */
5377 dev->info = info;
5378
5379 dev_info(dev->dev, "found switch: %s, rev %i\n",
5380 dev->info->dev_name, dev->chip_rev);
5381
5382 ret = ksz_check_device_id(dev);
5383 if (ret)
5384 return ret;
5385
5386 dev->dev_ops = dev->info->ops;
5387
5388 ret = dev->dev_ops->init(dev);
5389 if (ret)
5390 return ret;
5391
5392 dev->ports = devm_kzalloc(dev->dev,
5393 dev->info->port_cnt * sizeof(struct ksz_port),
5394 GFP_KERNEL);
5395 if (!dev->ports)
5396 return -ENOMEM;
5397
5398 for (i = 0; i < dev->info->port_cnt; i++) {
5399 spin_lock_init(&dev->ports[i].mib.stats64_lock);
5400 mutex_init(&dev->ports[i].mib.cnt_mutex);
5401 dev->ports[i].mib.counters =
5402 devm_kzalloc(dev->dev,
5403 sizeof(u64) * (dev->info->mib_cnt + 1),
5404 GFP_KERNEL);
5405 if (!dev->ports[i].mib.counters)
5406 return -ENOMEM;
5407
5408 dev->ports[i].ksz_dev = dev;
5409 dev->ports[i].num = i;
5410 }
5411
5412 /* set the real number of ports */
5413 dev->ds->num_ports = dev->info->port_cnt;
5414
5415 /* set the phylink ops */
5416 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5417
5418 /* Host port interface will be self detected, or specifically set in
5419 * device tree.
5420 */
5421 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5422 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5423 if (dev->dev->of_node) {
5424 ret = of_get_phy_mode(dev->dev->of_node, &interface);
5425 if (ret == 0)
5426 dev->compat_interface = interface;
5427 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
5428 if (!ports)
5429 ports = of_get_child_by_name(dev->dev->of_node, "ports");
5430 if (ports) {
5431 for_each_available_child_of_node_scoped(ports, port) {
5432 if (of_property_read_u32(port, "reg",
5433 &port_num))
5434 continue;
5435 if (!(dev->port_mask & BIT(port_num))) {
5436 of_node_put(ports);
5437 return -EINVAL;
5438 }
5439 of_get_phy_mode(port,
5440 &dev->ports[port_num].interface);
5441
5442 ksz_parse_rgmii_delay(dev, port_num, port);
5443 dev->ports[port_num].fiber =
5444 of_property_read_bool(port,
5445 "micrel,fiber-mode");
5446 }
5447 of_node_put(ports);
5448 }
5449 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
5450 "microchip,synclko-125");
5451 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
5452 "microchip,synclko-disable");
5453 if (dev->synclko_125 && dev->synclko_disable) {
5454 dev_err(dev->dev, "inconsistent synclko settings\n");
5455 return -EINVAL;
5456 }
5457
5458 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
5459 "wakeup-source");
5460 dev->pme_active_high = of_property_read_bool(dev->dev->of_node,
5461 "microchip,pme-active-high");
5462 }
5463
5464 ret = dsa_register_switch(dev->ds);
5465 if (ret) {
5466 dev->dev_ops->exit(dev);
5467 return ret;
5468 }
5469
5470 /* Read MIB counters every 30 seconds to avoid overflow. */
5471 dev->mib_read_interval = msecs_to_jiffies(5000);
5472
5473 /* Start the MIB timer. */
5474 schedule_delayed_work(&dev->mib_read, 0);
5475
5476 return ret;
5477 }
5478 EXPORT_SYMBOL(ksz_switch_register);
5479
ksz_switch_remove(struct ksz_device * dev)5480 void ksz_switch_remove(struct ksz_device *dev)
5481 {
5482 /* timer started */
5483 if (dev->mib_read_interval) {
5484 dev->mib_read_interval = 0;
5485 cancel_delayed_work_sync(&dev->mib_read);
5486 }
5487
5488 dev->dev_ops->exit(dev);
5489 dsa_unregister_switch(dev->ds);
5490
5491 if (dev->reset_gpio)
5492 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5493
5494 }
5495 EXPORT_SYMBOL(ksz_switch_remove);
5496
5497 #ifdef CONFIG_PM_SLEEP
ksz_switch_suspend(struct device * dev)5498 int ksz_switch_suspend(struct device *dev)
5499 {
5500 struct ksz_device *priv = dev_get_drvdata(dev);
5501
5502 return dsa_switch_suspend(priv->ds);
5503 }
5504 EXPORT_SYMBOL(ksz_switch_suspend);
5505
ksz_switch_resume(struct device * dev)5506 int ksz_switch_resume(struct device *dev)
5507 {
5508 struct ksz_device *priv = dev_get_drvdata(dev);
5509
5510 return dsa_switch_resume(priv->ds);
5511 }
5512 EXPORT_SYMBOL(ksz_switch_resume);
5513 #endif
5514
5515 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5516 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5517 MODULE_LICENSE("GPL");
5518