| /qemu/target/tricore/ |
| H A D | helper.c | 153 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
162 #define FIELD_GETTER(NAME, REG, FIELD) \ argument
168 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ argument
177 #define FIELD_SETTER(NAME, REG, FIELD) \ argument
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| H A D | translate.c | 340 #define R(ADDRESS, REG, FEATURE) \ argument
346 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) argument
347 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) argument
363 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, argument
365 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ argument
375 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) argument
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| /qemu/tests/tcg/i386/ |
| H A D | test-i386-adcox.c | 10 #define REG uint64_t macro
12 #define REG uint32_t macro
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| H A D | test-mmx.c | 128 #define REG(F) \ macro
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| H A D | test-avx.c | 124 #define REG(F) \ macro
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| /qemu/tests/qtest/ |
| H A D | tpm-util.h | 20 #define TIS_REG(LOCTY, REG) \ argument
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| /qemu/target/hexagon/ |
| H A D | macros.h | 200 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ argument
427 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) argument
428 #define fEA_RRs(REG, REG2, SCALE) \ argument
434 #define fEA_IRs(IMM, REG, SCALE) \ argument
440 #define fEA_RI(REG, IMM) \ argument
444 #define fEA_RRs(REG, REG2, SCALE) \ argument
448 #define fEA_IRs(IMM, REG, SCALE) \ argument
456 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) argument
457 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) argument
458 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) argument
[all …]
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| /qemu/linux-headers/asm-loongarch/ |
| H A D | kvm.h | 92 #define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT)) argument
93 #define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG) argument
94 #define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG) argument
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| /qemu/target/loongarch/ |
| H A D | cpu.h | 55 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) argument
56 #define SET_FP_CAUSE(REG, V) \ argument
60 #define UPDATE_FP_CAUSE(REG, V) \ argument
65 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) argument
66 #define SET_FP_ENABLES(REG, V) \ argument
71 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) argument
72 #define SET_FP_FLAGS(REG, V) \ argument
77 #define UPDATE_FP_FLAGS(REG, V) \ argument
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| H A D | disas.c | 39 #define CSR_NAME(REG) \ argument
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| /qemu/tests/tcg/s390x/ |
| H A D | ex-relative-long.c | 27 #define REG 0x1234567887654321 macro
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| /qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 70 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
72 #define fGETQBIT(REG, BITNO) fGETQBITS(REG, 1, 1, BITNO) argument
96 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
102 #define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL) argument
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| /qemu/target/arm/ |
| H A D | cpregs.h | 648 #define DO_BIT(REG, BITNAME) \ argument
652 #define DO_REV_BIT(REG, BITNAME) \ argument
662 #define DO_TLBINXS_BIT(REG, BITNAME) \ argument
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| /qemu/hw/net/ |
| H A D | npcm7xx_emc.c | 59 #define REG(name) case REG_ ## name: return #name; in emc_reg_name() macro
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| /qemu/hw/ipack/ |
| H A D | tpci200.c | 56 #define IP_N_FROM_REG(REG) ((REG) / 2 - 1) argument
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| /qemu/target/sh4/ |
| H A D | translate.c | 354 #define REG(x) cpu_gregs[(x) ^ ctx->gbank] macro
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| /qemu/target/i386/kvm/ |
| H A D | tdx.c | 1151 #define COPY_REG(REG) \ in tdx_handle_report_fatal_error() argument
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| /qemu/tests/qtest/libqos/ |
| H A D | ahci.c | 1261 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) in ahci_command_wait() argument
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| /qemu/target/avr/ |
| H A D | translate.c | 75 #define REG(x) (cpu_r[x]) macro
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| /qemu/target/m68k/ |
| H A D | translate.c | 55 #define REG(insn, pos) (((insn) >> (pos)) & 7) macro
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