1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * ARM CoreSight Architecture PMU driver.
4 * Copyright (c) 2022-2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
5 *
6 */
7
8 #ifndef __ARM_CSPMU_H__
9 #define __ARM_CSPMU_H__
10
11 #include <linux/acpi.h>
12 #include <linux/bitfield.h>
13 #include <linux/cpumask.h>
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/perf_event.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
20
21 #define to_arm_cspmu(p) (container_of(p, struct arm_cspmu, pmu))
22
23 #define ARM_CSPMU_EXT_ATTR(_name, _func, _config) \
24 (&((struct dev_ext_attribute[]){ \
25 { \
26 .attr = __ATTR(_name, 0444, _func, NULL), \
27 .var = (void *)_config \
28 } \
29 })[0].attr.attr)
30
31 #define ARM_CSPMU_FORMAT_ATTR(_name, _config) \
32 ARM_CSPMU_EXT_ATTR(_name, device_show_string, _config)
33
34 #define ARM_CSPMU_EVENT_ATTR(_name, _config) \
35 PMU_EVENT_ATTR_ID(_name, arm_cspmu_sysfs_event_show, _config)
36
37
38 /* Default event id mask */
39 #define ARM_CSPMU_EVENT_MASK GENMASK_ULL(63, 0)
40
41 /* Default filter value mask */
42 #define ARM_CSPMU_FILTER_MASK GENMASK_ULL(63, 0)
43
44 /* Default event format */
45 #define ARM_CSPMU_FORMAT_EVENT_ATTR \
46 ARM_CSPMU_FORMAT_ATTR(event, "config:0-32")
47
48 /* Default filter format */
49 #define ARM_CSPMU_FORMAT_FILTER_ATTR \
50 ARM_CSPMU_FORMAT_ATTR(filter, "config1:0-31")
51 #define ARM_CSPMU_FORMAT_FILTER2_ATTR \
52 ARM_CSPMU_FORMAT_ATTR(filter2, "config2:0-31")
53
54 /*
55 * This is the default event number for cycle count, if supported, since the
56 * ARM Coresight PMU specification does not define a standard event code
57 * for cycle count.
58 */
59 #define ARM_CSPMU_EVT_CYCLES_DEFAULT (0x1ULL << 32)
60
61 /*
62 * The ARM Coresight PMU supports up to 256 event counters.
63 * If the counters are larger-than 32-bits, then the PMU includes at
64 * most 128 counters.
65 */
66 #define ARM_CSPMU_MAX_HW_CNTRS 256
67
68 /* The cycle counter, if implemented, is located at counter[31]. */
69 #define ARM_CSPMU_CYCLE_CNTR_IDX 31
70
71 /*
72 * CoreSight PMU Arch register offsets.
73 */
74 #define PMEVCNTR_LO 0x0
75 #define PMEVCNTR_HI 0x4
76 #define PMEVTYPER 0x400
77 #define PMCCFILTR 0x47C
78 #define PMEVFILT2R 0x800
79 #define PMEVFILTR 0xA00
80 #define PMCNTENSET 0xC00
81 #define PMCNTENCLR 0xC20
82 #define PMINTENSET 0xC40
83 #define PMINTENCLR 0xC60
84 #define PMOVSCLR 0xC80
85 #define PMOVSSET 0xCC0
86 #define PMIMPDEF 0xD80
87 #define PMCFGR 0xE00
88 #define PMCR 0xE04
89 #define PMIIDR 0xE08
90 #define PMPIDR0 0xFE0
91 #define PMPIDR1 0xFE4
92 #define PMPIDR2 0xFE8
93 #define PMPIDR3 0xFEC
94 #define PMPIDR4 0xFD0
95
96 /* PMCFGR register field */
97 #define PMCFGR_NCG GENMASK(31, 28)
98 #define PMCFGR_HDBG BIT(24)
99 #define PMCFGR_TRO BIT(23)
100 #define PMCFGR_SS BIT(22)
101 #define PMCFGR_FZO BIT(21)
102 #define PMCFGR_MSI BIT(20)
103 #define PMCFGR_UEN BIT(19)
104 #define PMCFGR_NA BIT(17)
105 #define PMCFGR_EX BIT(16)
106 #define PMCFGR_CCD BIT(15)
107 #define PMCFGR_CC BIT(14)
108 #define PMCFGR_SIZE GENMASK(13, 8)
109 #define PMCFGR_N GENMASK(7, 0)
110
111 /* PMCR register field */
112 #define PMCR_TRO BIT(11)
113 #define PMCR_HDBG BIT(10)
114 #define PMCR_FZO BIT(9)
115 #define PMCR_NA BIT(8)
116 #define PMCR_DP BIT(5)
117 #define PMCR_X BIT(4)
118 #define PMCR_D BIT(3)
119 #define PMCR_C BIT(2)
120 #define PMCR_P BIT(1)
121 #define PMCR_E BIT(0)
122
123 /* PMIIDR register field */
124 #define PMIIDR_IMPLEMENTER GENMASK(11, 0)
125 #define PMIIDR_IMPLEMENTER_DES_0 GENMASK(3, 0)
126 #define PMIIDR_IMPLEMENTER_DES_1 GENMASK(6, 4)
127 #define PMIIDR_IMPLEMENTER_DES_2 GENMASK(11, 8)
128 #define PMIIDR_REVISION GENMASK(15, 12)
129 #define PMIIDR_VARIANT GENMASK(19, 16)
130 #define PMIIDR_PRODUCTID GENMASK(31, 20)
131 #define PMIIDR_PRODUCTID_PART_0 GENMASK(27, 20)
132 #define PMIIDR_PRODUCTID_PART_1 GENMASK(31, 28)
133
134 /* PMPIDR0 register field */
135 #define PMPIDR0_PART_0 GENMASK(7, 0)
136
137 /* PMPIDR1 register field */
138 #define PMPIDR1_DES_0 GENMASK(7, 4)
139 #define PMPIDR1_PART_1 GENMASK(3, 0)
140
141 /* PMPIDR2 register field */
142 #define PMPIDR2_REVISION GENMASK(7, 4)
143 #define PMPIDR2_DES_1 GENMASK(2, 0)
144
145 /* PMPIDR3 register field */
146 #define PMPIDR3_REVAND GENMASK(7, 4)
147 #define PMPIDR3_CMOD GENMASK(3, 0)
148
149 /* PMPIDR4 register field */
150 #define PMPIDR4_SIZE GENMASK(7, 4)
151 #define PMPIDR4_DES_2 GENMASK(3, 0)
152
153 /* JEDEC-assigned JEP106 identification code */
154 #define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
155 #define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
156
157 struct arm_cspmu;
158
159 /* This tracks the events assigned to each counter in the PMU. */
160 struct arm_cspmu_hw_events {
161 /* The events that are active on the PMU for a given logical index. */
162 struct perf_event **events;
163
164 /*
165 * Each bit indicates a logical counter is being used (or not) for an
166 * event. If cycle counter is supported and there is a gap between
167 * regular and cycle counter, the last logical counter is mapped to
168 * cycle counter. Otherwise, logical and physical have 1-to-1 mapping.
169 */
170 DECLARE_BITMAP(used_ctrs, ARM_CSPMU_MAX_HW_CNTRS);
171 };
172
173 /* Contains ops to query vendor/implementer specific attribute. */
174 struct arm_cspmu_impl_ops {
175 /* Get event attributes */
176 struct attribute **(*get_event_attrs)(const struct arm_cspmu *cspmu);
177 /* Get format attributes */
178 struct attribute **(*get_format_attrs)(const struct arm_cspmu *cspmu);
179 /* Get string identifier */
180 const char *(*get_identifier)(const struct arm_cspmu *cspmu);
181 /* Get PMU name to register to core perf */
182 const char *(*get_name)(const struct arm_cspmu *cspmu);
183 /* Check if the event corresponds to cycle count event */
184 bool (*is_cycle_counter_event)(const struct perf_event *event);
185 /* Decode event type/id from configs */
186 u32 (*event_type)(const struct perf_event *event);
187 /* Set/reset event filters */
188 void (*set_cc_filter)(struct arm_cspmu *cspmu,
189 const struct perf_event *event);
190 void (*set_ev_filter)(struct arm_cspmu *cspmu,
191 const struct perf_event *event);
192 void (*reset_ev_filter)(struct arm_cspmu *cspmu,
193 const struct perf_event *event);
194 /* Implementation specific event validation */
195 int (*validate_event)(struct arm_cspmu *cspmu,
196 struct perf_event *event);
197 /* Hide/show unsupported events */
198 umode_t (*event_attr_is_visible)(struct kobject *kobj,
199 struct attribute *attr, int unused);
200 };
201
202 /* Vendor/implementer registration parameter. */
203 struct arm_cspmu_impl_match {
204 /* Backend module. */
205 struct module *module;
206 const char *module_name;
207 /* PMIIDR value/mask. */
208 u32 pmiidr_val;
209 u32 pmiidr_mask;
210 /* Callback to vendor backend to init arm_cspmu_impl::ops. */
211 int (*impl_init_ops)(struct arm_cspmu *cspmu);
212 };
213
214 /* Vendor/implementer descriptor. */
215 struct arm_cspmu_impl {
216 u32 pmiidr;
217 struct module *module;
218 struct arm_cspmu_impl_match *match;
219 struct arm_cspmu_impl_ops ops;
220 void *ctx;
221 };
222
223 /* Coresight PMU descriptor. */
224 struct arm_cspmu {
225 struct pmu pmu;
226 struct device *dev;
227 const char *name;
228 const char *identifier;
229 void __iomem *base0;
230 void __iomem *base1;
231 cpumask_t associated_cpus;
232 cpumask_t active_cpu;
233 struct hlist_node cpuhp_node;
234 int irq;
235
236 bool has_atomic_dword;
237 u32 pmcfgr;
238 u32 num_logical_ctrs;
239 u32 num_set_clr_reg;
240 int cycle_counter_logical_idx;
241
242 struct arm_cspmu_hw_events hw_events;
243 const struct attribute_group *attr_groups[5];
244
245 struct arm_cspmu_impl impl;
246 };
247
248 /* Default function to show event attribute in sysfs. */
249 ssize_t arm_cspmu_sysfs_event_show(struct device *dev,
250 struct device_attribute *attr,
251 char *buf);
252
253 /* Register vendor backend. */
254 int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match);
255
256 /* Unregister vendor backend. */
257 void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match);
258
259 #if defined(CONFIG_ACPI) && defined(CONFIG_ARM64)
260 /**
261 * Get ACPI device associated with the PMU.
262 * The caller is responsible for calling acpi_dev_put() on the returned device.
263 */
264 struct acpi_device *arm_cspmu_acpi_dev_get(const struct arm_cspmu *cspmu);
265 #else
266 static inline struct acpi_device *
arm_cspmu_acpi_dev_get(const struct arm_cspmu * cspmu)267 arm_cspmu_acpi_dev_get(const struct arm_cspmu *cspmu)
268 {
269 return NULL;
270 }
271 #endif
272
273 #endif /* __ARM_CSPMU_H__ */
274