1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * Copyright (c) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef HW_LOONGARCH_PIC_COMMON_H 8 #define HW_LOONGARCH_PIC_COMMON_H 9 10 #include "hw/pci-host/ls7a.h" 11 #include "hw/sysbus.h" 12 13 #define PCH_PIC_INT_ID 0x00 14 #define PCH_PIC_INT_ID_VAL 0x7 15 #define PCH_PIC_INT_ID_VER 0x1 16 #define PCH_PIC_INT_MASK 0x20 17 #define PCH_PIC_HTMSI_EN 0x40 18 #define PCH_PIC_INT_EDGE 0x60 19 #define PCH_PIC_INT_CLEAR 0x80 20 #define PCH_PIC_AUTO_CTRL0 0xc0 21 #define PCH_PIC_AUTO_CTRL1 0xe0 22 #define PCH_PIC_ROUTE_ENTRY 0x100 23 #define PCH_PIC_ROUTE_ENTRY_END 0x13f 24 #define PCH_PIC_HTMSI_VEC 0x200 25 #define PCH_PIC_HTMSI_VEC_END 0x23f 26 #define PCH_PIC_INT_REQUEST 0x380 27 #define PCH_PIC_INT_STATUS 0x3a0 28 #define PCH_PIC_INT_POL 0x3e0 29 30 #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" 31 OBJECT_DECLARE_TYPE(LoongArchPICCommonState, 32 LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) 33 34 union LoongArchPIC_ID { 35 struct { 36 uint8_t _reserved_0[3]; 37 uint8_t id; 38 uint8_t version; 39 uint8_t _reserved_1; 40 uint8_t irq_num; 41 uint8_t _reserved_2; 42 } QEMU_PACKED desc; 43 uint64_t data; 44 }; 45 46 struct LoongArchPICCommonState { 47 SysBusDevice parent_obj; 48 49 qemu_irq parent_irq[64]; 50 union LoongArchPIC_ID id; /* 0x00 interrupt ID register */ 51 uint64_t int_mask; /* 0x020 interrupt mask register */ 52 uint64_t htmsi_en; /* 0x040 1=msi */ 53 uint64_t intedge; /* 0x060 edge=1 level=0 */ 54 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */ 55 uint64_t auto_crtl0; /* 0x0c0 */ 56 uint64_t auto_crtl1; /* 0x0e0 */ 57 uint64_t last_intirr; /* edge detection */ 58 uint64_t intirr; /* 0x380 interrupt request register */ 59 uint64_t intisr; /* 0x3a0 interrupt service register */ 60 /* 61 * 0x3e0 interrupt level polarity selection 62 * register 0 for high level trigger 63 */ 64 uint64_t int_polarity; 65 66 uint8_t route_entry[64]; /* 0x100 - 0x138 */ 67 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */ 68 69 MemoryRegion iomem; 70 unsigned int irq_num; 71 }; 72 73 struct LoongArchPICCommonClass { 74 SysBusDeviceClass parent_class; 75 76 DeviceRealize parent_realize; 77 ResettablePhases parent_phases; 78 int (*pre_save)(LoongArchPICCommonState *s); 79 int (*post_load)(LoongArchPICCommonState *s, int version_id); 80 }; 81 #endif /* HW_LOONGARCH_PIC_COMMON_H */ 82