1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * QEMU interface: 23 * + QOM property "num-cpu": number of CPUs to support 24 * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs) 25 * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC 26 * + QOM property "has-security-extensions": set true if the GIC should 27 * implement the security extensions 28 * + QOM property "has-virtualization-extensions": set true if the GIC should 29 * implement the virtualization extensions 30 * + QOM property "first-cpu-index": index of the first cpu attached to the 31 * GIC (default 0). The CPUs connected to the GIC are assumed to be 32 * first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1. 33 * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32) 34 * [0..P-1] SPIs 35 * [P..P+31] PPIs for CPU 0 36 * [P+32..P+63] PPIs for CPU 1 37 * ... 38 * + sysbus IRQs: (in order; number will vary depending on number of cores) 39 * - IRQ for CPU 0 40 * - IRQ for CPU 1 41 * ... 42 * - FIQ for CPU 0 43 * - FIQ for CPU 1 44 * ... 45 * - VIRQ for CPU 0 (exists even if virt extensions not present) 46 * - VIRQ for CPU 1 (exists even if virt extensions not present) 47 * ... 48 * - VFIQ for CPU 0 (exists even if virt extensions not present) 49 * - VFIQ for CPU 1 (exists even if virt extensions not present) 50 * ... 51 * - maintenance IRQ for CPU i/f 0 (only if virt extensions present) 52 * - maintenance IRQ for CPU i/f 1 (only if virt extensions present) 53 * + sysbus MMIO regions: (in order; numbers will vary depending on 54 * whether virtualization extensions are present and on number of cores) 55 * - distributor registers (GICD*) 56 * - CPU interface for the accessing core (GICC*) 57 * - virtual interface control registers (GICH*) (only if virt extns present) 58 * - virtual CPU interface for the accessing core (GICV*) (only if virt) 59 * - CPU 0 CPU interface registers 60 * - CPU 1 CPU interface registers 61 * ... 62 * - CPU 0 virtual interface control registers (only if virt extns present) 63 * - CPU 1 virtual interface control registers (only if virt extns present) 64 * ... 65 */ 66 67 #ifndef HW_ARM_GIC_H 68 #define HW_ARM_GIC_H 69 70 #include "arm_gic_common.h" 71 #include "qom/object.h" 72 73 /* Number of SGI target-list bits */ 74 #define GIC_TARGETLIST_BITS 8 75 #define GIC_MAX_PRIORITY_BITS 8 76 #define GIC_MIN_PRIORITY_BITS 4 77 78 #define TYPE_ARM_GIC "arm_gic" 79 typedef struct ARMGICClass ARMGICClass; 80 /* This is reusing the GICState typedef from TYPE_ARM_GIC_COMMON */ 81 DECLARE_OBJ_CHECKERS(GICState, ARMGICClass, 82 ARM_GIC, TYPE_ARM_GIC) 83 84 struct ARMGICClass { 85 /*< private >*/ 86 ARMGICCommonClass parent_class; 87 /*< public >*/ 88 89 DeviceRealize parent_realize; 90 }; 91 92 const char *gic_class_name(void); 93 94 #endif 95