1 /* HPPA cores and system support chips. */ 2 /* Be aware: QEMU and seabios-hppa repositories share this file as-is. */ 3 4 #ifndef HW_HPPA_HPPA_HARDWARE_H 5 #define HW_HPPA_HPPA_HARDWARE_H 6 7 #define FIRMWARE_START 0xf0000000 8 #define FIRMWARE_END 0xf0800000 9 #define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ 10 11 #define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ 12 13 #define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ 14 15 #define DEVICE_HPA_LEN 0x00100000 16 17 #define GSC_HPA 0xffc00000 18 #define DINO_HPA 0xfff80000 19 #define DINO_UART_HPA 0xfff83000 20 #define DINO_UART_BASE 0xfff83800 21 #define DINO_SCSI_HPA 0xfff8c000 22 #define LASI_HPA 0xffd00000 23 #define LASI_UART_HPA 0xffd05000 24 #define LASI_SCSI_HPA 0xffd06000 25 #define LASI_LAN_HPA 0xffd07000 26 #define LASI_RTC_HPA 0xffd09000 27 #define LASI_LPT_HPA 0xffd02000 28 #define LASI_AUDIO_HPA 0xffd04000 29 #define LASI_PS2KBD_HPA 0xffd08000 30 #define LASI_PS2MOU_HPA 0xffd08100 31 #define LASI_GFX_HPA 0xf8000000 32 #define ARTIST_FB_ADDR 0xf9000000 33 #define CPU_HPA 0xfffb0000 34 #define MEMORY_HPA 0xfffff000 35 36 #define IDE_HPA 0xf9000000 /* Boot disc controller */ 37 #define ASTRO_HPA 0xfed00000 38 #define ELROY0_HPA 0xfed30000 39 #define ELROY2_HPA 0xfed32000 40 #define ELROY8_HPA 0xfed38000 41 #define ELROYc_HPA 0xfed3c000 42 #define ASTRO_MEMORY_HPA 0xfed10200 43 44 #define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ 45 46 /* offsets to DINO HPA: */ 47 #define DINO_PCI_ADDR 0x064 48 #define DINO_CONFIG_DATA 0x068 49 #define DINO_IO_DATA 0x06c 50 51 #define PORT_PCI_CMD hppa_port_pci_cmd 52 #define PORT_PCI_DATA hppa_port_pci_data 53 54 #define FW_CFG_IO_BASE 0xfffa0000 55 56 #define PORT_SERIAL1 (LASI_UART_HPA + 0x800) 57 #define PORT_SERIAL2 (DINO_UART_HPA + 0x800) 58 59 #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ 60 #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ 61 62 #define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ 63 #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ 64 #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ 65 66 #define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ 67 68 /* ASTRO Memory and I/O regions */ 69 #define ASTRO_BASE_HPA 0xfffed00000 70 #define ELROY0_BASE_HPA 0xfffed30000 /* ELROY0_HPA */ 71 72 #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 73 74 #define LMMIO_DIRECT0_BASE 0x300 75 #define LMMIO_DIRECT0_MASK 0x308 76 #define LMMIO_DIRECT0_ROUTE 0x310 77 78 /* space register hashing */ 79 #define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ 80 #define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ 81 82 #endif 83