/qemu/target/hexagon/ |
H A D | translate.h | 29 typedef struct DisasContext { struct 30 DisasContextBase base; argument 31 Packet *pkt; 32 Insn *insn; 33 uint32_t next_PC; 34 uint32_t mem_idx; 35 uint32_t num_packets; 36 uint32_t num_insns; 37 uint32_t num_hvx_insns; 38 int reg_log[REG_WRITES_MAX]; [all …]
|
/qemu/target/arm/tcg/ |
H A D | translate.h | 24 typedef struct DisasContext { struct 25 DisasContextBase base; argument 26 const ARMISARegisters *isar; 29 target_ulong pc_curr; 43 target_ulong pc_save; 44 target_ulong page_start; 45 uint32_t insn; 47 int condjmp; 49 DisasLabel condlabel; 51 int condexec_mask; [all …]
|
/qemu/target/mips/tcg/ |
H A D | translate.h | 19 typedef struct DisasContext { struct 20 DisasContextBase base; argument 21 target_ulong saved_pc; 22 target_ulong page_start; 23 uint32_t opcode; 24 uint64_t insn_flags; 25 int32_t CP0_Config0; 26 int32_t CP0_Config1; 27 int32_t CP0_Config2; 28 int32_t CP0_Config3; [all …]
|
/qemu/target/loongarch/ |
H A D | translate.h | 41 typedef struct DisasContext { struct 42 DisasContextBase base; argument 53 } DisasContext; argument
|
H A D | disas.c | 17 } DisasContext; typedef
|
/qemu/target/riscv/ |
H A D | translate.c | 56 typedef struct DisasContext { struct 57 DisasContextBase base; argument 58 target_ulong cur_insn_len; 59 target_ulong pc_save; 60 target_ulong priv_ver; 61 RISCVMXL misa_mxl_max; 62 RISCVMXL xl; 63 RISCVMXL address_xl; 64 uint32_t misa_ext; 65 uint32_t opcode; [all …]
|
/qemu/target/i386/tcg/ |
H A D | translate.c | 85 typedef struct DisasContext { struct 86 DisasContextBase base; argument 88 target_ulong pc; /* pc = eip + cs_base */ 89 target_ulong cs_base; /* base of CS segment */ 90 target_ulong pc_save; 92 MemOp aflag; 93 MemOp dflag; 95 int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ 96 uint8_t prefix; 98 bool has_modrm; [all …]
|
/qemu/target/sh4/ |
H A D | translate.c | 36 typedef struct DisasContext { struct 37 DisasContextBase base; argument 50 } DisasContext; argument
|
/qemu/target/alpha/ |
H A D | translate.c | 45 typedef struct DisasContext DisasContext; typedef 46 struct DisasContext { struct 47 DisasContextBase base; argument 50 MemOp unalign; 52 uint64_t palbr; 54 uint32_t tbflags; 55 int mem_idx; 58 bool pcrel; 61 int implver; 62 int amask; [all …]
|
/qemu/target/openrisc/ |
H A D | disas.c | 25 typedef disassemble_info DisasContext; typedef
|
H A D | translate.c | 45 typedef struct DisasContext { struct 46 DisasContextBase base; argument 60 } DisasContext; argument
|
/qemu/target/ppc/ |
H A D | translate.c | 169 struct DisasContext { struct 170 DisasContextBase base; argument 171 target_ulong cia; /* current instruction address */ 172 uint32_t opcode; 174 bool pr, hv, dr, le_mode; 175 bool lazy_tlb_flush; 176 bool need_access_type; 177 int mem_idx; 178 int access_type; 180 MemOp default_tcg_memop_mask; [all …]
|
H A D | cpu.h | 294 typedef struct DisasContext DisasContext; typedef
|
/qemu/target/microblaze/ |
H A D | translate.c | 62 typedef struct DisasContext { struct 63 DisasContextBase base; argument 77 } DisasContext; argument
|
/qemu/target/avr/ |
H A D | translate.c | 81 typedef struct DisasContext DisasContext; typedef 84 struct DisasContext { struct 85 DisasContextBase base; argument 87 CPUAVRState *env; 88 CPUState *cs; 90 target_long npc; 91 uint32_t opcode; 94 int memidx; 120 TCGv skip_var0; 121 TCGv skip_var1; [all …]
|
H A D | disas.c | 28 } DisasContext; typedef
|
/qemu/target/xtensa/ |
H A D | translate.c | 52 struct DisasContext { struct 53 DisasContextBase base; argument 54 const XtensaConfig *config; 55 uint32_t pc; 56 int cring; 57 int ring; 58 uint32_t lbeg_off; 59 uint32_t lend; 61 bool sar_5bit; 62 bool sar_m32_5bit; [all …]
|
H A D | cpu.h | 369 typedef struct DisasContext DisasContext; typedef
|
/qemu/target/hppa/ |
H A D | translate.c | 65 typedef struct DisasContext { struct 66 DisasContextBase base; argument 67 CPUState *cs; 70 DisasIAQE iaq_f, iaq_b; 72 DisasIAQE iaq_j, *iaq_n; 97 } DisasContext; argument
|
/qemu/target/rx/ |
H A D | disas.c | 24 typedef struct DisasContext { struct 30 } DisasContext; argument
|
H A D | translate.c | 35 typedef struct DisasContext { struct 36 DisasContextBase base; argument 40 } DisasContext; typedef
|
/qemu/target/sparc/ |
H A D | translate.c | 166 typedef struct DisasContext { struct 167 DisasContextBase base; argument 168 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ 169 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */ 194 } DisasContext; argument 2849 TCGv (*func)(DisasContext *, TCGv)) in do_rd_special() argument 3255 void (*func)(DisasContext *, TCGv)) in do_wr_special() 5461 void (*func)(DisasContext *, DisasCompare *, int, int)) in do_fmovr() 5485 void (*func)(DisasContext *, DisasCompare *, int, int)) in do_fmovcc() 5507 void (*func)(DisasContext *, DisasCompare *, int, int)) in do_fmovfcc()
|
/qemu/target/m68k/ |
H A D | translate.c | 112 typedef struct DisasContext { struct 113 DisasContextBase base; argument 124 } DisasContext; argument
|
/qemu/target/tricore/ |
H A D | translate.c | 73 typedef struct DisasContext { struct 74 DisasContextBase base; argument 82 } DisasContext; argument
|
/qemu/target/s390x/tcg/ |
H A D | translate.c | 52 typedef struct DisasContext DisasContext; typedef 139 struct DisasContext { struct 140 DisasContextBase base; argument 141 const DisasInsn *insn; 142 DisasFields fields; 143 uint64_t ex_value; 170 static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) in pc_to_link_info() argument
|