| /qemu/target/hexagon/ |
| H A D | macros.h | 195 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) argument
197 #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) argument
278 #define fADDSAT64(DST, A, B) \ argument
395 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) argument
396 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) argument
397 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) argument
398 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) argument
399 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) argument
400 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) argument
401 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) argument
[all …]
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| H A D | opcodes.c | 29 #define VEC_DESCR(A, B, C) DESCR(A, B, C) argument
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| /qemu/tests/tcg/ppc64/ |
| H A D | bcdsub.c | 19 #define BCDSUB(T, A, B, PS) \ argument
23 #define BCDSUB(T, A, B, PS) "bcdsub. " #T ", " #A ", " #B ", " #PS "\n\t" argument
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| /qemu/target/loongarch/ |
| H A D | vec.h | 12 #define B(x) B[(x) ^ 15] macro
22 #define B(x) B[x] macro
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| H A D | cpu.h | 261 int8_t B[LASX_LEN / 8]; member
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| /qemu/fpu/ |
| H A D | softfloat.c | 738 #define parts_pick_nan(A, B, S) PARTS_GENERIC_64_128(pick_nan, A)(A, B, S) argument
749 #define parts_pick_nan_muladd(A, B, C, S, ABM, ABCM) \ argument
780 #define parts_add_normal(A, B) \ argument
787 #define parts_sub_normal(A, B) \ argument
795 #define parts_addsub(A, B, S, Z) \ argument
803 #define parts_mul(A, B, S) \ argument
813 #define parts_muladd_scalbn(A, B, C, Z, Y, S) \ argument
821 #define parts_div(A, B, S) \ argument
829 #define parts_modrem(A, B, Q, S) \ argument
910 #define parts_minmax(A, B, S, F) \ argument
[all …]
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| /qemu/target/arm/tcg/ |
| H A D | translate-sme.c | 200 #define FN_END(L, B) { FN_HV(L), FN_HV(B) } in trans_LDST1() argument
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| H A D | vec_helper.c | 2607 #define ADD(A, B) (A + B) argument
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| /qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 109 #define fSWAPB(A, B) do { uint8_t tmp = A; A = B; B = tmp; } while (0) argument
345 #define fCARRY_FROM_ADD32(A, B, C) \ argument
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| /qemu/hw/display/ |
| H A D | exynos4210_fimd.c | 377 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ argument
400 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ argument
420 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ argument
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| /qemu/hw/arm/ |
| H A D | exynos4210.c | 269 #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) argument
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| /qemu/target/loongarch/tcg/ |
| H A D | vec_helper.c | 988 do_vsrlr(B, uint8_t) in do_vsrlr() argument
1370 SSRLNS(B, uint16_t, int16_t, uint8_t) in SSRLNS() argument
1808 SSRLRNS(B, H, uint16_t, int16_t, uint8_t) in SSRLRNS() argument
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| /qemu/tcg/ |
| H A D | tcg.c | 838 #define C_PFX2(P, A, B) P##A##_##B argument
839 #define C_PFX3(P, A, B, C) P##A##_##B##_##C argument
840 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D argument
841 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E argument
842 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F argument
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| /qemu/target/i386/ |
| H A D | ops_sse.h | 28 #define B(n) MMX_B(n) macro
36 #define B(n) ZMM_B(n) macro
2615 uint32_t B = b->L(2); in helper_sha256rnds2() local
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| /qemu/target/s390x/tcg/ |
| H A D | translate.c | 958 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N } argument
959 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N } argument
960 #define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N } argument
971 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N } argument
972 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N } argument
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| /qemu/target/ppc/ |
| H A D | int_helper.c | 563 VARITHSAT_SIGNED(B, s8, int16_t, cvtshsb) in VARITHSAT_SIGNED() argument
1713 VINSX(B, uint8_t) in VINSX() argument
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| /qemu/target/riscv/ |
| H A D | translate.c | 808 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ argument
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