1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * AMD Common ACP header file for ACP6.3, ACP7.0 & ACP7.1 platforms
4 *
5 * Copyright (C) 2022, 2023, 2025 Advanced Micro Devices, Inc. All rights reserved.
6 */
7
8 #include <linux/soundwire/sdw_amd.h>
9 #include <sound/acp63_chip_offset_byte.h>
10
11 #define ACP_DEVICE_ID 0x15E2
12 #define ACP63_REG_START 0x1240000
13 #define ACP63_REG_END 0x125C000
14 #define ACP63_PCI_REV 0x63
15 #define ACP70_PCI_REV 0x70
16 #define ACP71_PCI_REV 0x71
17 #define ACP72_PCI_REV 0x72
18
19 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
20 #define ACP63_PGFSM_CNTL_POWER_ON_MASK 1
21 #define ACP63_PGFSM_CNTL_POWER_OFF_MASK 0
22 #define ACP63_PGFSM_STATUS_MASK 3
23 #define ACP63_POWERED_ON 0
24 #define ACP63_POWER_ON_IN_PROGRESS 1
25 #define ACP63_POWERED_OFF 2
26 #define ACP63_POWER_OFF_IN_PROGRESS 3
27
28 #define ACP_ERROR_MASK 0x20000000
29 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
30 #define PDM_DMA_STAT 0x10
31
32 #define PDM_DMA_INTR_MASK 0x10000
33 #define ACP_ERROR_STAT 29
34 #define PDM_DECIMATION_FACTOR 2
35 #define ACP_PDM_CLK_FREQ_MASK 7
36 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
37 #define ACP_PDM_ENABLE 1
38 #define ACP_PDM_DISABLE 0
39 #define ACP_PDM_DMA_EN_STATUS 2
40 #define TWO_CH 2
41 #define DELAY_US 5
42 #define ACP_COUNTER 20000
43
44 #define ACP_SRAM_PTE_OFFSET 0x03800000
45 #define PAGE_SIZE_4K_ENABLE 2
46 #define PDM_PTE_OFFSET 0
47 #define PDM_MEM_WINDOW_START 0x4000000
48
49 #define CAPTURE_MIN_NUM_PERIODS 4
50 #define CAPTURE_MAX_NUM_PERIODS 4
51 #define CAPTURE_MAX_PERIOD_SIZE 8192
52 #define CAPTURE_MIN_PERIOD_SIZE 4096
53
54 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
55 #define MIN_BUFFER MAX_BUFFER
56
57 /* time in ms for runtime suspend delay */
58 #define ACP_SUSPEND_DELAY_MS 2000
59
60 #define ACP_DMIC_DEV 2
61
62 #define ACP63_DMIC_ADDR 2
63 #define ACP63_SDW_ADDR 5
64 #define AMD_SDW_MAX_MANAGERS 2
65
66 /* time in ms for acp timeout */
67 #define ACP63_TIMEOUT 500
68
69 #define ACP_SDW0_STAT BIT(21)
70 #define ACP_SDW1_STAT BIT(2)
71 #define ACP_ERROR_IRQ BIT(29)
72
73 #define ACP_AUDIO0_TX_THRESHOLD 0x1c
74 #define ACP_AUDIO1_TX_THRESHOLD 0x1a
75 #define ACP_AUDIO2_TX_THRESHOLD 0x18
76 #define ACP_AUDIO0_RX_THRESHOLD 0x1b
77 #define ACP_AUDIO1_RX_THRESHOLD 0x19
78 #define ACP_AUDIO2_RX_THRESHOLD 0x17
79 #define ACP63_P1_AUDIO1_TX_THRESHOLD BIT(6)
80 #define ACP63_P1_AUDIO1_RX_THRESHOLD BIT(5)
81 #define ACP63_SDW_DMA_IRQ_MASK 0x1F800000
82 #define ACP63_P1_SDW_DMA_IRQ_MASK 0x60
83 #define ACP63_SDW0_DMA_MAX_STREAMS 6
84 #define ACP63_SDW1_DMA_MAX_STREAMS 2
85 #define ACP63_P1_AUDIO_TX_THRESHOLD 6
86
87 /*
88 * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping
89 * in ACP_EXTENAL_INTR_CNTL register.
90 * Stream id IRQ Bit
91 * 0 (SDW0_AUDIO0_TX) 28
92 * 1 (SDW0_AUDIO1_TX) 26
93 * 2 (SDW0_AUDIO2_TX) 24
94 * 3 (SDW0_AUDIO0_RX) 27
95 * 4 (SDW0_AUDIO1_RX) 25
96 * 5 (SDW0_AUDIO2_RX) 23
97 */
98 #define ACP63_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
99 #define ACP63_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
100
101 /*
102 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
103 * in ACP_EXTENAL_INTR_CNTL1 register.
104 * Stream id IRQ Bit
105 * 0 (SDW1_AUDIO1_TX) 6
106 * 1 (SDW1_AUDIO1_RX) 5
107 */
108 #define ACP63_SDW1_DMA_IRQ_MASK(i) (ACP63_P1_AUDIO_TX_THRESHOLD - (i))
109
110 #define ACP_DELAY_US 5
111 #define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024)
112 #define SDW0_MEM_WINDOW_START 0x4800000
113 #define ACP_SDW_SRAM_PTE_OFFSET 0x03800400
114 #define SDW0_PTE_OFFSET 0x400
115 #define SDW_FIFO_SIZE 0x100
116 #define SDW_DMA_SIZE 0x40
117 #define ACP_SDW0_FIFO_OFFSET 0x100
118 #define ACP_SDW_PTE_OFFSET 0x100
119 #define SDW_FIFO_OFFSET 0x100
120 #define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600))
121 #define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500))
122 #define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000))
123
124 #define SDW_PLAYBACK_MIN_NUM_PERIODS 2
125 #define SDW_PLAYBACK_MAX_NUM_PERIODS 8
126 #define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192
127 #define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024
128 #define SDW_CAPTURE_MIN_NUM_PERIODS 2
129 #define SDW_CAPTURE_MAX_NUM_PERIODS 8
130 #define SDW_CAPTURE_MAX_PERIOD_SIZE 8192
131 #define SDW_CAPTURE_MIN_PERIOD_SIZE 1024
132
133 #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS)
134 #define SDW_MIN_BUFFER SDW_MAX_BUFFER
135
136 #define ACP_HW_OPS(acp_data, cb) ((acp_data)->hw_ops->cb)
137
138 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F
139 #define ACP70_PGFSM_CNTL_POWER_OFF_MASK 0
140 #define ACP70_PGFSM_STATUS_MASK 0xFF
141 #define ACP70_TIMEOUT 2000
142 #define ACP70_SDW_HOST_WAKE_MASK 0x0C00000
143 #define ACP70_SDW0_HOST_WAKE_STAT BIT(24)
144 #define ACP70_SDW1_HOST_WAKE_STAT BIT(25)
145 #define ACP70_SDW0_PME_STAT BIT(26)
146 #define ACP70_SDW1_PME_STAT BIT(27)
147
148 #define ACP70_SDW0_DMA_MAX_STREAMS 6
149 #define ACP70_SDW1_DMA_MAX_STREAMS ACP70_SDW0_DMA_MAX_STREAMS
150 #define ACP70_SDW_DMA_IRQ_MASK 0x1F800000
151 #define ACP70_P1_SDW_DMA_IRQ_MASK 0x1F8
152
153 #define ACP70_P1_AUDIO0_TX_THRESHOLD 0x8
154 #define ACP70_P1_AUDIO1_TX_THRESHOLD 0x6
155 #define ACP70_P1_AUDIO2_TX_THRESHOLD 0x4
156 #define ACP70_P1_AUDIO0_RX_THRESHOLD 0x7
157 #define ACP70_P1_AUDIO1_RX_THRESHOLD 0x5
158 #define ACP70_P1_AUDIO2_RX_THRESHOLD 0x3
159
160 #define ACP70_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
161 #define ACP70_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
162
163 /*
164 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
165 * in ACP_EXTENAL_INTR_CNTL1 register for ACP70/ACP71 platforms
166 * Stream id IRQ Bit
167 * 0 (SDW1_AUDIO0_TX) 8
168 * 1 (SDW1_AUDIO1_TX) 6
169 * 2 (SDW1_AUDIO2_TX) 4
170 * 3 (SDW1_AUDIO0_RX) 7
171 * 4 (SDW1_AUDIO1_RX) 5
172 * 5 (SDW1_AUDIO2_RX) 3
173 */
174 #define ACP70_SDW1_DMA_TX_IRQ_MASK(i) (ACP70_P1_AUDIO0_TX_THRESHOLD - (2 * (i)))
175 #define ACP70_SDW1_DMA_RX_IRQ_MASK(i) (ACP70_P1_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
176
177 #define ACP70_SW0_AUDIO0_TX_EN ACP_SW0_AUDIO0_TX_EN
178 #define ACP70_SW0_AUDIO1_TX_EN ACP_SW0_AUDIO1_TX_EN
179 #define ACP70_SW0_AUDIO2_TX_EN ACP_SW0_AUDIO2_TX_EN
180 #define ACP70_SW0_AUDIO0_RX_EN ACP_SW0_AUDIO0_RX_EN
181 #define ACP70_SW0_AUDIO1_RX_EN ACP_SW0_AUDIO1_RX_EN
182 #define ACP70_SW0_AUDIO2_RX_EN ACP_SW0_AUDIO2_RX_EN
183
184 #define ACP70_SW1_AUDIO0_TX_EN 0x0003C10
185 #define ACP70_SW1_AUDIO1_TX_EN 0x0003C50
186 #define ACP70_SW1_AUDIO2_TX_EN 0x0003C6C
187 #define ACP70_SW1_AUDIO0_RX_EN 0x0003C88
188 #define ACP70_SW1_AUDIO1_RX_EN 0x0003D28
189 #define ACP70_SW1_AUDIO2_RX_EN 0x0003D44
190
191 enum acp_config {
192 ACP_CONFIG_0 = 0,
193 ACP_CONFIG_1,
194 ACP_CONFIG_2,
195 ACP_CONFIG_3,
196 ACP_CONFIG_4,
197 ACP_CONFIG_5,
198 ACP_CONFIG_6,
199 ACP_CONFIG_7,
200 ACP_CONFIG_8,
201 ACP_CONFIG_9,
202 ACP_CONFIG_10,
203 ACP_CONFIG_11,
204 ACP_CONFIG_12,
205 ACP_CONFIG_13,
206 ACP_CONFIG_14,
207 ACP_CONFIG_15,
208 ACP_CONFIG_16,
209 ACP_CONFIG_17,
210 ACP_CONFIG_18,
211 ACP_CONFIG_19,
212 ACP_CONFIG_20,
213 };
214
215 enum amd_acp63_sdw0_channel {
216 ACP63_SDW0_AUDIO0_TX = 0,
217 ACP63_SDW0_AUDIO1_TX,
218 ACP63_SDW0_AUDIO2_TX,
219 ACP63_SDW0_AUDIO0_RX,
220 ACP63_SDW0_AUDIO1_RX,
221 ACP63_SDW0_AUDIO2_RX,
222 };
223
224 enum amd_acp63_sdw1_channel {
225 ACP63_SDW1_AUDIO1_TX,
226 ACP63_SDW1_AUDIO1_RX,
227 };
228
229 enum amd_acp70_sdw_channel {
230 ACP70_SDW_AUDIO0_TX = 0,
231 ACP70_SDW_AUDIO1_TX,
232 ACP70_SDW_AUDIO2_TX,
233 ACP70_SDW_AUDIO0_RX,
234 ACP70_SDW_AUDIO1_RX,
235 ACP70_SDW_AUDIO2_RX,
236 };
237
238 struct pdm_stream_instance {
239 u16 num_pages;
240 u16 channels;
241 dma_addr_t dma_addr;
242 u64 bytescount;
243 void __iomem *acp63_base;
244 };
245
246 struct pdm_dev_data {
247 u32 pdm_irq;
248 void __iomem *acp63_base;
249 struct mutex *acp_lock;
250 struct snd_pcm_substream *capture_stream;
251 };
252
253 struct sdw_dma_dev_data {
254 void __iomem *acp_base;
255 struct mutex *acp_lock; /* used to protect acp common register access */
256 u32 acp_rev;
257 struct snd_pcm_substream *acp63_sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];
258 struct snd_pcm_substream *acp63_sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];
259 struct snd_pcm_substream *acp70_sdw0_dma_stream[ACP70_SDW0_DMA_MAX_STREAMS];
260 struct snd_pcm_substream *acp70_sdw1_dma_stream[ACP70_SDW1_DMA_MAX_STREAMS];
261 };
262
263 struct acp_sdw_dma_stream {
264 u16 num_pages;
265 u16 channels;
266 u32 stream_id;
267 u32 instance;
268 dma_addr_t dma_addr;
269 u64 bytescount;
270 };
271
272 union acp_sdw_dma_count {
273 struct {
274 u32 low;
275 u32 high;
276 } bcount;
277 u64 bytescount;
278 };
279
280 struct sdw_dma_ring_buf_reg {
281 u32 reg_dma_size;
282 u32 reg_fifo_addr;
283 u32 reg_fifo_size;
284 u32 reg_ring_buf_size;
285 u32 reg_ring_buf_addr;
286 u32 water_mark_size_reg;
287 u32 pos_low_reg;
288 u32 pos_high_reg;
289 };
290
291 struct acp63_dev_data;
292
293 /**
294 * struct acp_hw_ops - ACP PCI driver platform specific ops
295 * @acp_init: ACP initialization
296 * @acp_deinit: ACP de-initialization
297 * @acp_get_config: function to read the acp pin configuration
298 * @acp_sdw_dma_irq_thread: ACP SoundWire DMA interrupt thread
299 * acp_suspend: ACP system level suspend callback
300 * acp_resume: ACP system level resume callback
301 * acp_suspend_runtime: ACP runtime suspend callback
302 * acp_resume_runtime: ACP runtime resume callback
303 */
304 struct acp_hw_ops {
305 int (*acp_init)(void __iomem *acp_base, struct device *dev);
306 int (*acp_deinit)(void __iomem *acp_base, struct device *dev);
307 void (*acp_get_config)(struct pci_dev *pci, struct acp63_dev_data *acp_data);
308 void (*acp_sdw_dma_irq_thread)(struct acp63_dev_data *acp_data);
309 int (*acp_suspend)(struct device *dev);
310 int (*acp_resume)(struct device *dev);
311 int (*acp_suspend_runtime)(struct device *dev);
312 int (*acp_resume_runtime)(struct device *dev);
313 };
314
315 /**
316 * struct acp63_dev_data - acp pci driver context
317 * @acp63_base: acp mmio base
318 * @res: resource
319 * @hw_ops: ACP pci driver platform-specific ops
320 * @pdm_dev: ACP PDM controller platform device
321 * @dmic_codec: platform device for DMIC Codec
322 * sdw_dma_dev: platform device for SoundWire DMA controller
323 * @mach_dev: platform device for machine driver to support ACP PDM/SoundWire configuration
324 * @acp_lock: used to protect acp common registers
325 * @info: SoundWire AMD information found in ACPI tables
326 * @sdw: SoundWire context for all SoundWire manager instances
327 * @machine: ACPI machines for SoundWire interface
328 * @is_sdw_dev: flag set to true when any SoundWire manager instances are available
329 * @is_pdm_dev: flag set to true when ACP PDM controller exists
330 * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS
331 * @is_sdw_config: flag set to true when SDW configuration is selected from BIOS
332 * @sdw_en_stat: flag set to true when any one of the SoundWire manager instance is enabled
333 * @acp70_sdw0_wake_event: flag set to true when wake irq asserted for SW0 instance
334 * @acp70_sdw1_wake_event: flag set to true when wake irq asserted for SW1 instance
335 * @addr: pci ioremap address
336 * @reg_range: ACP reigister range
337 * @acp_rev: ACP PCI revision id
338 * @acp_sw_pad_keeper_en: store acp SoundWire pad keeper enable register value
339 * @acp_pad_pulldown_ctrl: store acp pad pulldown control register value
340 * @acp63_sdw0-dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire
341 * manager-SW0 instance
342 * @acp63_sdw_dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire
343 * manager-SW1 instance
344 * @acp70_sdw0-dma_intr_stat: DMA interrupt status array for ACP7.0 platform SoundWire
345 * manager-SW0 instance
346 * @acp70_sdw_dma_intr_stat: DMA interrupt status array for ACP7.0 platform SoundWire
347 * manager-SW1 instance
348 */
349
350 struct acp63_dev_data {
351 void __iomem *acp63_base;
352 struct resource *res;
353 struct acp_hw_ops *hw_ops;
354 struct platform_device *pdm_dev;
355 struct platform_device *dmic_codec_dev;
356 struct platform_device *sdw_dma_dev;
357 struct platform_device *mach_dev;
358 struct mutex acp_lock; /* protect shared registers */
359 struct sdw_amd_acpi_info info;
360 /* sdw context allocated by SoundWire driver */
361 struct sdw_amd_ctx *sdw;
362 struct snd_soc_acpi_mach *machines;
363 bool is_sdw_dev;
364 bool is_pdm_dev;
365 bool is_pdm_config;
366 bool is_sdw_config;
367 bool sdw_en_stat;
368 bool acp70_sdw0_wake_event;
369 bool acp70_sdw1_wake_event;
370 u32 addr;
371 u32 reg_range;
372 u32 acp_rev;
373 u32 acp_sw_pad_keeper_en;
374 u32 acp_pad_pulldown_ctrl;
375 u16 acp63_sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS];
376 u16 acp63_sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS];
377 u16 acp70_sdw0_dma_intr_stat[ACP70_SDW0_DMA_MAX_STREAMS];
378 u16 acp70_sdw1_dma_intr_stat[ACP70_SDW1_DMA_MAX_STREAMS];
379 };
380
381 void acp63_hw_init_ops(struct acp_hw_ops *hw_ops);
382 void acp70_hw_init_ops(struct acp_hw_ops *hw_ops);
383
acp_hw_init(struct acp63_dev_data * adata,struct device * dev)384 static inline int acp_hw_init(struct acp63_dev_data *adata, struct device *dev)
385 {
386 if (adata && adata->hw_ops && adata->hw_ops->acp_init)
387 return ACP_HW_OPS(adata, acp_init)(adata->acp63_base, dev);
388 return -EOPNOTSUPP;
389 }
390
acp_hw_deinit(struct acp63_dev_data * adata,struct device * dev)391 static inline int acp_hw_deinit(struct acp63_dev_data *adata, struct device *dev)
392 {
393 if (adata && adata->hw_ops && adata->hw_ops->acp_deinit)
394 return ACP_HW_OPS(adata, acp_deinit)(adata->acp63_base, dev);
395 return -EOPNOTSUPP;
396 }
397
acp_hw_get_config(struct pci_dev * pci,struct acp63_dev_data * adata)398 static inline void acp_hw_get_config(struct pci_dev *pci, struct acp63_dev_data *adata)
399 {
400 if (adata && adata->hw_ops && adata->hw_ops->acp_get_config)
401 ACP_HW_OPS(adata, acp_get_config)(pci, adata);
402 }
403
acp_hw_sdw_dma_irq_thread(struct acp63_dev_data * adata)404 static inline void acp_hw_sdw_dma_irq_thread(struct acp63_dev_data *adata)
405 {
406 if (adata && adata->hw_ops && adata->hw_ops->acp_sdw_dma_irq_thread)
407 ACP_HW_OPS(adata, acp_sdw_dma_irq_thread)(adata);
408 }
409
acp_hw_suspend(struct device * dev)410 static inline int acp_hw_suspend(struct device *dev)
411 {
412 struct acp63_dev_data *adata = dev_get_drvdata(dev);
413
414 if (adata && adata->hw_ops && adata->hw_ops->acp_suspend)
415 return ACP_HW_OPS(adata, acp_suspend)(dev);
416 return -EOPNOTSUPP;
417 }
418
acp_hw_resume(struct device * dev)419 static inline int acp_hw_resume(struct device *dev)
420 {
421 struct acp63_dev_data *adata = dev_get_drvdata(dev);
422
423 if (adata && adata->hw_ops && adata->hw_ops->acp_resume)
424 return ACP_HW_OPS(adata, acp_resume)(dev);
425 return -EOPNOTSUPP;
426 }
427
acp_hw_suspend_runtime(struct device * dev)428 static inline int acp_hw_suspend_runtime(struct device *dev)
429 {
430 struct acp63_dev_data *adata = dev_get_drvdata(dev);
431
432 if (adata && adata->hw_ops && adata->hw_ops->acp_suspend_runtime)
433 return ACP_HW_OPS(adata, acp_suspend_runtime)(dev);
434 return -EOPNOTSUPP;
435 }
436
acp_hw_runtime_resume(struct device * dev)437 static inline int acp_hw_runtime_resume(struct device *dev)
438 {
439 struct acp63_dev_data *adata = dev_get_drvdata(dev);
440
441 if (adata && adata->hw_ops && adata->hw_ops->acp_resume_runtime)
442 return ACP_HW_OPS(adata, acp_resume_runtime)(dev);
443 return -EOPNOTSUPP;
444 }
445
446 int snd_amd_acp_find_config(struct pci_dev *pci);
447