Lines Matching +full:- +full:- +full:disable +full:- +full:pie
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include "qemu/qemu-print.h"
17 #include "hw/qdev-properties.h"
18 #include "exec/translation-block.h"
21 #include "fpu/softfloat-helpers.h"
31 #include "accel/tcg/cpu-ldst.h"
32 #include "accel/tcg/cpu-ops.h"
69 {EXCCODE_INE, "Instruction Non-Existent"},
75 {EXCCODE_SXD, "128 bit vector instructions Disable exception"},
76 {EXCCODE_ASXD, "256 bit vector instructions Disable exception"},
102 cs->exception_index = exception; in do_raise_exception()
114 return cpu_env(cs)->pc; in loongarch_cpu_get_pc()
123 CPULoongArchState *env = &cpu->env; in loongarch_cpu_set_irq()
133 env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); in loongarch_cpu_set_irq()
134 if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { in loongarch_cpu_set_irq()
146 ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && in cpu_loongarch_hw_interrupts_enabled()
147 !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); in cpu_loongarch_hw_interrupts_enabled()
158 pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); in cpu_loongarch_hw_interrupts_pending()
159 status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); in cpu_loongarch_hw_interrupts_pending()
171 int cause = -1; in loongarch_cpu_do_interrupt()
172 bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); in loongarch_cpu_do_interrupt()
173 uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); in loongarch_cpu_do_interrupt()
175 if (cs->exception_index != EXCCODE_INT) { in loongarch_cpu_do_interrupt()
179 __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, in loongarch_cpu_do_interrupt()
180 cs->exception_index, in loongarch_cpu_do_interrupt()
181 loongarch_exception_name(cs->exception_index)); in loongarch_cpu_do_interrupt()
184 switch (cs->exception_index) { in loongarch_cpu_do_interrupt()
186 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); in loongarch_cpu_do_interrupt()
187 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); in loongarch_cpu_do_interrupt()
190 env->CSR_DERA = env->pc; in loongarch_cpu_do_interrupt()
191 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); in loongarch_cpu_do_interrupt()
192 set_pc(env, env->CSR_EENTRY + 0x480); in loongarch_cpu_do_interrupt()
195 if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { in loongarch_cpu_do_interrupt()
196 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); in loongarch_cpu_do_interrupt()
202 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
213 env->CSR_BADV = env->pc; in loongarch_cpu_do_interrupt()
223 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
227 cs->exception_index); in loongarch_cpu_do_interrupt()
232 env->CSR_BADI = cpu_ldl_code(env, env->pc); in loongarch_cpu_do_interrupt()
237 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, in loongarch_cpu_do_interrupt()
238 FIELD_EX64(env->CSR_CRMD, in loongarch_cpu_do_interrupt()
240 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, in loongarch_cpu_do_interrupt()
241 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); in loongarch_cpu_do_interrupt()
243 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); in loongarch_cpu_do_interrupt()
244 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); in loongarch_cpu_do_interrupt()
245 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, in loongarch_cpu_do_interrupt()
246 PC, (env->pc >> 2)); in loongarch_cpu_do_interrupt()
248 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, in loongarch_cpu_do_interrupt()
250 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, in loongarch_cpu_do_interrupt()
252 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, in loongarch_cpu_do_interrupt()
253 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV)); in loongarch_cpu_do_interrupt()
254 env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, in loongarch_cpu_do_interrupt()
255 FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)); in loongarch_cpu_do_interrupt()
256 env->CSR_ERA = env->pc; in loongarch_cpu_do_interrupt()
259 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); in loongarch_cpu_do_interrupt()
260 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); in loongarch_cpu_do_interrupt()
266 if (cs->exception_index == EXCCODE_INT) { in loongarch_cpu_do_interrupt()
269 uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); in loongarch_cpu_do_interrupt()
270 pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); in loongarch_cpu_do_interrupt()
272 /* Find the highest-priority interrupt. */ in loongarch_cpu_do_interrupt()
273 vector = 31 - clz32(pending); in loongarch_cpu_do_interrupt()
274 set_pc(env, env->CSR_EENTRY + \ in loongarch_cpu_do_interrupt()
281 __func__, env->pc, env->CSR_ERA, in loongarch_cpu_do_interrupt()
282 cause, env->CSR_BADV, env->CSR_DERA, vector, in loongarch_cpu_do_interrupt()
283 env->CSR_ECFG, env->CSR_ESTAT); in loongarch_cpu_do_interrupt()
286 set_pc(env, env->CSR_TLBRENTRY); in loongarch_cpu_do_interrupt()
288 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); in loongarch_cpu_do_interrupt()
295 " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc, in loongarch_cpu_do_interrupt()
296 tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, in loongarch_cpu_do_interrupt()
297 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, in loongarch_cpu_do_interrupt()
298 env->CSR_ECFG, in loongarch_cpu_do_interrupt()
299 tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, in loongarch_cpu_do_interrupt()
300 env->CSR_BADI, env->gpr[11], cs->cpu_index, in loongarch_cpu_do_interrupt()
301 env->CSR_ASID); in loongarch_cpu_do_interrupt()
303 cs->exception_index = -1; in loongarch_cpu_do_interrupt()
330 cs->exception_index = EXCCODE_INT; in loongarch_cpu_exec_interrupt()
350 flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); in loongarch_get_tb_cpu_state()
351 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; in loongarch_get_tb_cpu_state()
352 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; in loongarch_get_tb_cpu_state()
353 flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; in loongarch_get_tb_cpu_state()
356 return (TCGTBCPUState){ .pc = env->pc, .flags = flags }; in loongarch_get_tb_cpu_state()
363 set_pc(cpu_env(cs), tb->pc); in loongarch_cpu_synchronize_from_tb()
379 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && in loongarch_cpu_has_work()
392 if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { in loongarch_cpu_mmu_index()
393 return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); in loongarch_cpu_mmu_index()
403 CPULoongArchState *env = &cpu->env; in loongarch_la464_init_csr()
408 num = FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); in loongarch_la464_init_csr()
428 CPULoongArchState *env = &cpu->env; in loongarch_la464_initfn()
433 env->cpucfg[i] = 0x0; in loongarch_la464_initfn()
436 cpu->dtb_compatible = "loongarch,Loongson-3A5000"; in loongarch_la464_initfn()
437 env->cpucfg[0] = 0x14c010; /* PRID */ in loongarch_la464_initfn()
443 /* GPA address width of VM is 47, field value is 47 - 1 */ in loongarch_la464_initfn()
446 field = 0x2f; /* 48 bit - 1 */ in loongarch_la464_initfn()
456 env->cpucfg[1] = data; in loongarch_la464_initfn()
469 env->cpucfg[2] = data; in loongarch_la464_initfn()
471 env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */ in loongarch_la464_initfn()
476 env->cpucfg[5] = data; in loongarch_la464_initfn()
487 env->cpucfg[16] = data; in loongarch_la464_initfn()
493 env->cpucfg[17] = data; in loongarch_la464_initfn()
499 env->cpucfg[18] = data; in loongarch_la464_initfn()
505 env->cpucfg[19] = data; in loongarch_la464_initfn()
511 env->cpucfg[20] = data; in loongarch_la464_initfn()
513 env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); in loongarch_la464_initfn()
515 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8); in loongarch_la464_initfn()
516 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f); in loongarch_la464_initfn()
517 env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); in loongarch_la464_initfn()
519 env->CSR_PRCFG2 = 0x3ffff000; in loongarch_la464_initfn()
521 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2); in loongarch_la464_initfn()
522 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63); in loongarch_la464_initfn()
523 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7); in loongarch_la464_initfn()
524 env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8); in loongarch_la464_initfn()
533 CPULoongArchState *env = &cpu->env; in loongarch_la132_initfn()
538 env->cpucfg[i] = 0x0; in loongarch_la132_initfn()
541 cpu->dtb_compatible = "loongarch,Loongson-1C103"; in loongarch_la132_initfn()
542 env->cpucfg[0] = 0x148042; /* PRID */ in loongarch_la132_initfn()
555 env->cpucfg[1] = data; in loongarch_la132_initfn()
560 /* '-cpu max' for TCG: we use cpu la464. */ in loongarch_max_initfn()
571 if (lacc->parent_phases.hold) { in loongarch_cpu_reset_hold()
572 lacc->parent_phases.hold(obj, type); in loongarch_cpu_reset_hold()
576 env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; in loongarch_cpu_reset_hold()
578 env->fcsr0 = 0x0; in loongarch_cpu_reset_hold()
582 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); in loongarch_cpu_reset_hold()
583 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); in loongarch_cpu_reset_hold()
584 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); in loongarch_cpu_reset_hold()
585 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); in loongarch_cpu_reset_hold()
586 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); in loongarch_cpu_reset_hold()
587 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); in loongarch_cpu_reset_hold()
589 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); in loongarch_cpu_reset_hold()
590 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); in loongarch_cpu_reset_hold()
591 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); in loongarch_cpu_reset_hold()
592 env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); in loongarch_cpu_reset_hold()
594 env->CSR_MISC = 0; in loongarch_cpu_reset_hold()
596 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); in loongarch_cpu_reset_hold()
597 env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); in loongarch_cpu_reset_hold()
599 env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); in loongarch_cpu_reset_hold()
600 env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); in loongarch_cpu_reset_hold()
601 env->CSR_CPUID = cs->cpu_index; in loongarch_cpu_reset_hold()
602 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); in loongarch_cpu_reset_hold()
603 env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); in loongarch_cpu_reset_hold()
604 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); in loongarch_cpu_reset_hold()
605 env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); in loongarch_cpu_reset_hold()
606 env->CSR_TID = cs->cpu_index; in loongarch_cpu_reset_hold()
608 * Workaround for edk2-stable202408, CSR PGD register is set only if in loongarch_cpu_reset_hold()
613 env->CSR_PGDH = 0; in loongarch_cpu_reset_hold()
614 env->CSR_PGDL = 0; in loongarch_cpu_reset_hold()
615 env->CSR_PWCH = 0; in loongarch_cpu_reset_hold()
616 env->CSR_EENTRY = 0; in loongarch_cpu_reset_hold()
617 env->CSR_TLBRENTRY = 0; in loongarch_cpu_reset_hold()
618 env->CSR_MERRENTRY = 0; in loongarch_cpu_reset_hold()
620 if (env->CSR_PRCFG2 == 0) { in loongarch_cpu_reset_hold()
621 env->CSR_PRCFG2 = 0x3fffff000; in loongarch_cpu_reset_hold()
623 tlb_ps = ctz32(env->CSR_PRCFG2); in loongarch_cpu_reset_hold()
624 env->CSR_STLBPS = FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps); in loongarch_cpu_reset_hold()
625 env->CSR_PWCL = FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); in loongarch_cpu_reset_hold()
627 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); in loongarch_cpu_reset_hold()
628 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); in loongarch_cpu_reset_hold()
629 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); in loongarch_cpu_reset_hold()
630 env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); in loongarch_cpu_reset_hold()
634 env->pc = 0x1c000000; in loongarch_cpu_reset_hold()
636 memset(env->tlb, 0, sizeof(env->tlb)); in loongarch_cpu_reset_hold()
646 cs->exception_index = -1; in loongarch_cpu_reset_hold()
651 info->endian = BFD_ENDIAN_LITTLE; in loongarch_cpu_disas_set_info()
652 info->print_insn = print_insn_loongarch; in loongarch_cpu_disas_set_info()
672 lacc->parent_realize(dev, errp); in loongarch_cpu_realizefn()
683 lacc->parent_unrealize(dev); in loongarch_cpu_unrealizefn()
688 return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF; in loongarch_get_lsx()
696 cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; in loongarch_set_lsx()
697 if (cpu->lsx == ON_OFF_AUTO_OFF) { in loongarch_set_lsx()
698 cpu->lasx = ON_OFF_AUTO_OFF; in loongarch_set_lsx()
699 if (cpu->lasx == ON_OFF_AUTO_ON) { in loongarch_set_lsx()
700 error_setg(errp, "Failed to disable LSX since LASX is enabled"); in loongarch_set_lsx()
711 val = cpu->env.cpucfg[2]; in loongarch_set_lsx()
712 if (cpu->lsx == ON_OFF_AUTO_ON) { in loongarch_set_lsx()
718 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0); in loongarch_set_lsx()
719 val = cpu->env.cpucfg[2]; in loongarch_set_lsx()
722 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value); in loongarch_set_lsx()
727 return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF; in loongarch_get_lasx()
735 cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; in loongarch_set_lasx()
736 if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) { in loongarch_set_lasx()
747 val = cpu->env.cpucfg[2]; in loongarch_set_lasx()
748 if (cpu->lasx == ON_OFF_AUTO_ON) { in loongarch_set_lasx()
755 cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value); in loongarch_set_lasx()
762 cpu->lbt = ON_OFF_AUTO_OFF; in loongarch_cpu_post_init()
763 cpu->pmu = ON_OFF_AUTO_OFF; in loongarch_cpu_post_init()
764 cpu->lsx = ON_OFF_AUTO_AUTO; in loongarch_cpu_post_init()
765 cpu->lasx = ON_OFF_AUTO_AUTO; in loongarch_cpu_post_init()
783 timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, in loongarch_cpu_init()
816 if (!csr_info || (csr_info->flags & CSRFL_UNUSED)) { in loongarch_cpu_dump_csr()
829 addr = (void *)env + csr_info->offset; in loongarch_cpu_dump_csr()
830 qemu_fprintf(f, " %s ", csr_info->name); in loongarch_cpu_dump_csr()
831 len = strlen(csr_info->name); in loongarch_cpu_dump_csr()
837 j = find_last_bit((void *)addr, BITS_PER_LONG) & (BITS_PER_LONG - 1); in loongarch_cpu_dump_csr()
856 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); in loongarch_cpu_dump_state()
857 qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0); in loongarch_cpu_dump_state()
864 qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]); in loongarch_cpu_dump_state()
876 qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i].vreg.D(0)); in loongarch_cpu_dump_state()
909 #include "hw/core/sysemu-cpu-ops.h"
921 return cpu->phy_id; in loongarch_cpu_get_arch_id()
926 DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0),
927 DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0),
928 DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0),
929 DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
941 &lacc->parent_realize); in loongarch_cpu_class_init()
943 &lacc->parent_unrealize); in loongarch_cpu_class_init()
945 &lacc->parent_phases); in loongarch_cpu_class_init()
947 cc->class_by_name = loongarch_cpu_class_by_name; in loongarch_cpu_class_init()
948 cc->dump_state = loongarch_cpu_dump_state; in loongarch_cpu_class_init()
949 cc->set_pc = loongarch_cpu_set_pc; in loongarch_cpu_class_init()
950 cc->get_pc = loongarch_cpu_get_pc; in loongarch_cpu_class_init()
952 cc->get_arch_id = loongarch_cpu_get_arch_id; in loongarch_cpu_class_init()
953 dc->vmsd = &vmstate_loongarch_cpu; in loongarch_cpu_class_init()
954 cc->sysemu_ops = &loongarch_sysemu_ops; in loongarch_cpu_class_init()
956 cc->disas_set_info = loongarch_cpu_disas_set_info; in loongarch_cpu_class_init()
957 cc->gdb_read_register = loongarch_cpu_gdb_read_register; in loongarch_cpu_class_init()
958 cc->gdb_write_register = loongarch_cpu_gdb_write_register; in loongarch_cpu_class_init()
959 cc->gdb_stop_before_watchpoint = true; in loongarch_cpu_class_init()
962 cc->tcg_ops = &loongarch_tcg_ops; in loongarch_cpu_class_init()
964 dc->user_creatable = true; in loongarch_cpu_class_init()
976 cc->gdb_core_xml_file = "loongarch-base32.xml"; in loongarch32_cpu_class_init()
977 cc->gdb_arch_name = loongarch32_gdb_arch_name; in loongarch32_cpu_class_init()
989 cc->gdb_core_xml_file = "loongarch-base64.xml"; in loongarch64_cpu_class_init()
990 cc->gdb_arch_name = loongarch64_gdb_arch_name; in loongarch64_cpu_class_init()