Lines Matching +full:string +full:- +full:array +full:- +full:property

3 // SPDX-License-Identifier: GPL-2.0-or-later
13 qdev::{Clock, ClockEvent, DeviceImpl, DeviceState, Property, ResetType, ResettablePhasesImpl},
44 fn index(&self, idx: hwaddr) -> &Self::Output { in index()
49 // FIFOs use 32-bit indices instead of usize, for compatibility with
57 const fn len(&self) -> u32 { in len()
63 fn index_mut(&mut self, idx: u32) -> &mut Self::Output { in index_mut()
71 fn index(&self, idx: u32) -> &Self::Output { in index()
131 // expand the padding_for_rust[] array in the C PL011State struct.
139 /// The byte string that identifies the device.
172 fn properties() -> &'static [Property] { in properties()
175 fn vmsd() -> Option<&'static VMStateDescription> { in vmsd()
178 const REALIZE: Option<fn(&Self) -> qemu_api::Result<()>> = Some(Self::realize);
188 pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) { in read()
206 // "The UARTICR Register is the interrupt clear register and is write-only" in read()
220 ) -> bool { in write()
286 fn read_data_register(&mut self, update: &mut bool) -> u32 { in read_data_register()
291 self.read_count -= 1; in read_data_register()
292 self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1); in read_data_register()
305 fn write_data_register(&mut self, value: u32) -> bool { in write_data_register()
314 fn loopback_tx(&mut self, value: registers::Data) -> bool { in loopback_tx()
317 // In real hardware, TX loopback happens at the serial-bit level in loopback_tx()
321 // Because the real hardware TX fifo is time-drained at the frame in loopback_tx()
329 // hardware flow-control is enabled. in loopback_tx()
336 fn loopback_mdmctrl(&mut self) -> bool { in loopback_mdmctrl()
342 * Loopback software-driven modem control outputs to modem status inputs: in loopback_mdmctrl()
382 fn loopback_break(&mut self, enable: bool) -> bool { in loopback_break()
423 pub fn fifo_enabled(&self) -> bool { in fifo_enabled()
428 pub fn loopback_enabled(&self) -> bool { in loopback_enabled()
433 pub fn fifo_depth(&self) -> u32 { in fifo_depth()
434 // Note: FIFO depth is expected to be power-of-2 in fifo_depth()
442 pub fn fifo_rx_put(&mut self, value: registers::Data) -> bool { in fifo_rx_put()
445 let slot = (self.read_pos + self.read_count) & (depth - 1); in fifo_rx_put()
460 pub fn post_load(&mut self) -> Result<(), ()> { in post_load()
461 /* Sanity-check input state */ in post_load()
468 // character in the FIFO in FIFO-disabled mode is in in post_load()
469 // element 0 of the array; convert to follow the current in post_load()
483 /// Initializes a pre-allocated, uninitialized instance of `PL011State`.
534 fn read(&self, offset: hwaddr, _size: u32) -> u64 { in read()
538 u64::from(device_id[(offset - 0xfe0) >> 2]) in read()
580 fn can_receive(&self) -> u32 { in can_receive()
582 // trace_pl011_can_receive(s->lcr, s->read_count, r); in can_receive()
583 regs.fifo_depth() - regs.read_count in can_receive()
622 fn realize(&self) -> qemu_api::Result<()> { in realize()
640 pub fn post_load(&self, _version_id: u32) -> Result<(), ()> { in post_load()
664 ) -> *mut DeviceState { in pl011_create()