3 // SPDX-License-Identifier: GPL-2.0-or-later
47     fn index(&self, idx: hwaddr) -> &Self::Output {  in index()
52 // FIFOs use 32-bit indices instead of usize, for compatibility with
60     const fn len(&self) -> u32 {  in len()
66     fn index_mut(&mut self, idx: u32) -> &mut Self::Output {  in index_mut()
74     fn index(&self, idx: u32) -> &Self::Output {  in index()
169     const INSTANCE_INIT: Option<unsafe fn(ParentInit<Self>)> = Some(Self::init);
175     fn properties() -> &'static [Property] {  in properties()
178     fn vmsd() -> Option<&'static VMStateDescription> {  in vmsd()
181     const REALIZE: Option<fn(&Self) -> qemu_api::Result<()>> = Some(Self::realize);
191     pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) {  in read()
209                 // "The UARTICR Register is the interrupt clear register and is write-only"  in read()
223     ) -> bool {  in write()
288     fn read_data_register(&mut self, update: &mut bool) -> u32 {  in read_data_register()
293             self.read_count -= 1;  in read_data_register()
294             self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);  in read_data_register()
307     fn write_data_register(&mut self, value: u32) -> bool {  in write_data_register()
322     fn loopback_tx(&mut self, value: registers::Data) -> bool {  in loopback_tx()
325         // In real hardware, TX loopback happens at the serial-bit level  in loopback_tx()
329         // Because the real hardware TX fifo is time-drained at the frame  in loopback_tx()
337         // hardware flow-control is enabled.  in loopback_tx()
344     fn loopback_mdmctrl(&mut self) -> bool {  in loopback_mdmctrl()
350          * Loopback software-driven modem control outputs to modem status inputs:  in loopback_mdmctrl()
390     fn loopback_break(&mut self, enable: bool) -> bool {  in loopback_break()
431     pub fn fifo_enabled(&self) -> bool {  in fifo_enabled()
436     pub fn loopback_enabled(&self) -> bool {  in loopback_enabled()
441     pub fn fifo_depth(&self) -> u32 {  in fifo_depth()
442         // Note: FIFO depth is expected to be power-of-2  in fifo_depth()
450     pub fn fifo_rx_put(&mut self, value: registers::Data) -> bool {  in fifo_rx_put()
453         let slot = (self.read_pos + self.read_count) & (depth - 1);  in fifo_rx_put()
468     pub fn post_load(&mut self) -> Result<(), ()> {  in post_load()
469         /* Sanity-check input state */  in post_load()
476             // character in the FIFO in FIFO-disabled mode is in  in post_load()
491     /// Initializes a pre-allocated, uninitialized instance of `PL011State`.
499     unsafe fn init(mut this: ParentInit<Self>) {  in init()  method
537     fn read(&self, offset: hwaddr, _size: u32) -> u64 {  in read()
541                 u64::from(device_id[(offset - 0xfe0) >> 2])  in read()
586     fn can_receive(&self) -> u32 {  in can_receive()
588         // trace_pl011_can_receive(s->lcr, s->read_count, r);  in can_receive()
589         regs.fifo_depth() - regs.read_count  in can_receive()
628     fn realize(&self) -> qemu_api::Result<()> {  in realize()
646     pub fn post_load(&self, _version_id: u32) -> Result<(), ()> {  in post_load()
670 ) -> *mut DeviceState {  in pl011_create()