Lines Matching +full:0 +full:x10000
11 * 0) UART (16550A)
47 [XIANGSHAN_KMH_ROM] = { 0x1000, 0xF000 },
48 [XIANGSHAN_KMH_UART0] = { 0x310B0000, 0x10000 },
49 [XIANGSHAN_KMH_CLINT] = { 0x38000000, 0x10000 },
50 [XIANGSHAN_KMH_APLIC_M] = { 0x31100000, 0x4000 },
51 [XIANGSHAN_KMH_APLIC_S] = { 0x31120000, 0x4000 },
52 [XIANGSHAN_KMH_IMSIC_M] = { 0x3A800000, 0x10000 },
53 [XIANGSHAN_KMH_IMSIC_S] = { 0x3B000000, 0x80000 },
54 [XIANGSHAN_KMH_DRAM] = { 0x80000000, 0x0 },
61 hwaddr addr = 0; in xiangshan_kmh_create_aia()
66 for (i = 0; i < num_harts; i++) { in xiangshan_kmh_create_aia()
67 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true, in xiangshan_kmh_create_aia()
73 for (i = 0; i < num_harts; i++) { in xiangshan_kmh_create_aia()
83 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, in xiangshan_kmh_create_aia()
89 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, in xiangshan_kmh_create_aia()
104 qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0); in xiangshan_kmh_soc_realize()
115 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); in xiangshan_kmh_soc_realize()
119 0, num_harts, false); in xiangshan_kmh_soc_realize()
123 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, in xiangshan_kmh_soc_realize()
184 memmap[XIANGSHAN_KMH_ROM].size, 0, 0); in type_init()