ethernet/ti/cpsw_priv.c

25 #include "cpsw.h"
34 int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv);
36 void cpsw_intr_enable(struct cpsw_common *cpsw)
38 	writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
39 	writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
41 	cpdma_ctlr_int_ctrl(cpsw->dma, true);
44 void cpsw_intr_disable(struct cpsw_common *cpsw)
46 	writel_relaxed(0, &cpsw->wr_regs->tx_en);
47 	writel_relaxed(0, &cpsw->wr_regs->rx_en);
49 	cpdma_ctlr_int_ctrl(cpsw->dma, false);
88 	struct cpsw_common *cpsw = dev_id;
90 	writel(0, &cpsw->wr_regs->tx_en);
91 	cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
93 	if (cpsw->quirk_irq) {
94 		disable_irq_nosync(cpsw->irqs_table[1]);
95 		cpsw->tx_irq_disabled = true;
98 	napi_schedule(&cpsw->napi_tx);
104 	struct cpsw_common *cpsw = dev_id;
106 	writel(0, &cpsw->wr_regs->rx_en);
107 	cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
109 	if (cpsw->quirk_irq) {
110 		disable_irq_nosync(cpsw->irqs_table[0]);
111 		cpsw->rx_irq_disabled = true;
114 	napi_schedule(&cpsw->napi_rx);
120 	struct cpsw_common *cpsw = dev_id;
122 	writel(0, &cpsw->wr_regs->misc_en);
123 	cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_MISC);
124 	cpts_misc_interrupt(cpsw->cpts);
125 	writel(0x10, &cpsw->wr_regs->misc_en);
132 	struct cpsw_common	*cpsw = napi_to_cpsw(napi_tx);
138 	ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
143 		txv = &cpsw->txv[ch];
156 		writel(0xff, &cpsw->wr_regs->tx_en);
164 	struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
167 	num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
170 		writel(0xff, &cpsw->wr_regs->tx_en);
171 		if (cpsw->tx_irq_disabled) {
172 			cpsw->tx_irq_disabled = false;
173 			enable_irq(cpsw->irqs_table[1]);
182 	struct cpsw_common	*cpsw = napi_to_cpsw(napi_rx);
188 	ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
193 		rxv = &cpsw->rxv[ch];
206 		writel(0xff, &cpsw->wr_regs->rx_en);
214 	struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
217 	num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
220 		writel(0xff, &cpsw->wr_regs->rx_en);
221 		if (cpsw->rx_irq_disabled) {
222 			cpsw->rx_irq_disabled = false;
223 			enable_irq(cpsw->irqs_table[0]);
234 	struct cpsw_common *cpsw = priv->cpsw;
256 	if (!cpsw_ale_get_vlan_p0_untag(cpsw->ale, vid)) {
293 	struct cpsw_common *cpsw = priv->cpsw;
298 	cpsw_intr_disable(cpsw);
299 	for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
300 		cpdma_chan_stop(cpsw->txv[ch].ch);
301 		cpdma_chan_start(cpsw->txv[ch].ch);
304 	cpsw_intr_enable(cpsw);
309 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
313 	for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
314 		if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
315 			speed += cpsw->slaves[i].phy->speed;
320 int cpsw_need_resplit(struct cpsw_common *cpsw)
326 	speed = cpsw_get_common_speed(cpsw);
327 	if (speed == cpsw->speed || !speed)
330 	cpsw->speed = speed;
332 	for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
333 		ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
341 	if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
347 void cpsw_split_res(struct cpsw_common *cpsw)
350 	struct cpsw_vector *txv = cpsw->txv;
356 	for (i = 0; i < cpsw->tx_ch_num; i++) {
365 	if (cpsw->tx_ch_num == rlim_ch_num) {
368 		ch_budget = NAPI_POLL_WEIGHT / cpsw->tx_ch_num;
372 		max_rate = cpsw->speed * 1000;
385 			    (cpsw->tx_ch_num - rlim_ch_num);
387 			      (cpsw->tx_ch_num - rlim_ch_num);
392 	for (i = 0; i < cpsw->tx_ch_num; i++) {
406 			cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
411 			cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
422 	ch_budget = budget / cpsw->rx_ch_num;
423 	for (i = 0; i < cpsw->rx_ch_num; i++) {
424 		cpsw->rxv[i].budget = ch_budget;
429 		cpsw->rxv[0].budget += budget;
432 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
440 	struct device *dev = cpsw->dev;
445 	data = &cpsw->data;
446 	cpsw->rx_ch_num = 1;
447 	cpsw->tx_ch_num = 1;
449 	cpsw->version = readl(&cpsw->regs->id_ver);
454 	switch (cpsw->version) {
456 		cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
458 		cpsw->hw_stats	     = ss_regs + CPSW1_HW_STATS;
470 		cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
472 		cpsw->hw_stats	     = ss_regs + CPSW2_HW_STATS;
482 		dev_err(dev, "unknown version 0x%08x\n", cpsw->version);
486 	for (i = 0; i < cpsw->data.slaves; i++) {
487 		struct cpsw_slave *slave = &cpsw->slaves[i];
488 		void __iomem		*regs = cpsw->regs;
491 		slave->data	= &cpsw->data.slave_data[i];
494 		slave->mac_sl = cpsw_sl_get("cpsw", dev, regs + sliver_offset);
505 	ale_params.dev_id		= "cpsw";
506 	ale_params.bus_freq		= cpsw->bus_freq_mhz * 1000000;
508 	cpsw->ale = cpsw_ale_create(&ale_params);
509 	if (IS_ERR(cpsw->ale)) {
511 		return PTR_ERR(cpsw->ale);
528 	dma_params.bus_freq_mhz		= cpsw->bus_freq_mhz;
531 	cpsw->dma = cpdma_ctlr_create(&dma_params);
532 	if (!cpsw->dma) {
537 	cpts_node = of_get_child_by_name(cpsw->dev->of_node, "cpts");
539 		cpts_node = cpsw->dev->of_node;
541 	cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpts_node,
543 	if (IS_ERR(cpsw->cpts)) {
544 		ret = PTR_ERR(cpsw->cpts);
545 		cpdma_ctlr_destroy(cpsw->dma);
556 	struct cpsw_common *cpsw = priv->cpsw;
557 	struct cpsw_slave *slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
580 	struct cpsw_common *cpsw = priv->cpsw;
584 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
587 	switch (cpsw->version) {
613 	writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
614 	writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype);
622 	struct cpsw_common *cpsw = priv->cpsw;
631 	if (cpsw->version != CPSW_VERSION_1 &&
632 	    cpsw->version != CPSW_VERSION_2 &&
633 	    cpsw->version != CPSW_VERSION_3)
667 	switch (cpsw->version) {
685 	struct cpsw_common *cpsw = ndev_to_cpsw(dev);
688 	if (cpsw->version != CPSW_VERSION_1 &&
689 	    cpsw->version != CPSW_VERSION_2 &&
690 	    cpsw->version != CPSW_VERSION_3)
716 	struct cpsw_common *cpsw = priv->cpsw;
727 	min_rate = cpdma_chan_get_min_rate(cpsw->dma);
734 	if (rate > cpsw->speed) {
739 	ret = pm_runtime_resume_and_get(cpsw->dev);
743 	ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
744 	pm_runtime_put(cpsw->dev);
750 	for (i = 0; i < cpsw->data.slaves; i++) {
751 		slave = &cpsw->slaves[i];
758 	cpsw_split_res(cpsw);
772 	struct cpsw_common *cpsw = priv->cpsw;
776 	val = readl_relaxed(&cpsw->regs->ptype);
778 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
788 	struct cpsw_common *cpsw = priv->cpsw;
792 	val = readl_relaxed(&cpsw->regs->ptype);
794 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
799 	writel_relaxed(val, &cpsw->regs->ptype);
804 	struct cpsw_common *cpsw = priv->cpsw;
815 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
864 	struct cpsw_common *cpsw = priv->cpsw;
873 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
874 	tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
916 	struct cpsw_common *cpsw = priv->cpsw;
939 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
953 	ret = pm_runtime_resume_and_get(cpsw->dev);
968 	pm_runtime_put_sync(cpsw->dev);
976 	struct cpsw_common *cpsw = priv->cpsw;
989 	ret = pm_runtime_resume_and_get(cpsw->dev);
1016 	offset = cpsw->version == CPSW_VERSION_1 ?
1019 	slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1022 	pm_runtime_put_sync(cpsw->dev);
1062 	struct cpsw_common *cpsw = priv->cpsw;
1076 	tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1084 	struct cpsw_common *cpsw = priv->cpsw;
1092 	for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1093 		pool = cpsw->page_pool[ch];
1094 		ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1107 			ret = cpdma_chan_idle_submit_mapped(cpsw->rxv[ch].ch,
1109 							    cpsw->rx_packet_max,
1127 static struct page_pool *cpsw_create_page_pool(struct cpsw_common *cpsw,
1138 	pp_params.dev = cpsw->dev;
1142 		dev_err(cpsw->dev, "cannot create rx page pool\n");
1147 static int cpsw_create_rx_pool(struct cpsw_common *cpsw, int ch)
1152 	pool_size = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1153 	pool = cpsw_create_page_pool(cpsw, pool_size);
1157 		cpsw->page_pool[ch] = pool;
1164 	struct cpsw_common *cpsw = priv->cpsw;
1169 	pool = cpsw->page_pool[ch];
1193 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw)
1198 	for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1199 		for (i = 0; i < cpsw->data.slaves; i++) {
1200 			ndev = cpsw->slaves[i].ndev;
1207 		page_pool_destroy(cpsw->page_pool[ch]);
1208 		cpsw->page_pool[ch] = NULL;
1212 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw)
1217 	for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1218 		ret = cpsw_create_rx_pool(cpsw, ch);
1225 		for (i = 0; i < cpsw->data.slaves; i++) {
1226 			ndev = cpsw->slaves[i].ndev;
1239 	cpsw_destroy_xdp_rxqs(cpsw);
1274 	struct cpsw_common *cpsw = priv->cpsw;
1283 	txch = cpsw->txv[0].ch;
1307 	struct cpsw_common *cpsw = priv->cpsw;
1362 	page_pool_recycle_direct(cpsw->page_pool[ch], page);
1403 	port_id = cpsw_slave_index(priv->cpsw, priv) + 1;
1407 		ret = cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id, rate_pkt_ps);
1415 		ret = cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, rate_pkt_ps);
1489 	u32 port_id = cpsw_slave_index(priv->cpsw, priv) + 1;
1494 		cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id, 0);
1500 		cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, 0);
1557 	u32 port_id = cpsw_slave_index(priv->cpsw, priv) + 1;
1560 		cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id,
1564 		cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id,