ethernet/realtek/r8169_main.c

84 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))
1023 	RTL_W32(tp, ERIDR, val);
1025 	RTL_W32(tp, ERIAR, cmd);
1041 	RTL_W32(tp, ERIAR, cmd);
1084 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1094 	RTL_W32(tp, GPHY_OCP, reg << 15);
1105 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1122 	RTL_W32(tp, OCPDR, reg << 15);
1217 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1231 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1254 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1259 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1324 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1334 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1342 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1355 	RTL_W32(tp, OCPDR, data);
1356 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1537 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1554 		RTL_W32(tp, IntrStatus_8125, bits);
1562 		RTL_W32(tp, IntrMask_8125, 0);
1570 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1743 	RTL_W32(tp, RxConfig, rx_config);
1832 	RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1834 	RTL_W32(tp, CounterAddrLow, cmd);
1835 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
2453 	RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2456 	RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2484 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2489 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2492 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2495 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2498 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2502 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2595 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2641 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2646 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2654 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2684 	RTL_W32(tp, TxConfig, val);
2700 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2701 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2702 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2703 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2720 	RTL_W32(tp, 0x7c, val);
2756 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2757 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2760 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2772 	RTL_W32(tp, CSIDR, value);
2773 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2783 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
3141 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3142 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3176 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3197 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3602 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3605 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3631 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3652 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3654 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3679 	RTL_W32(tp, RSS_CTRL_8125, 0);
3869 			RTL_W32(tp, i, 0);
3876 			RTL_W32(tp, i, 0);