182 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)  in mt7530_write()  function
252 	mt7530_write(priv, MT7530_ATC, val);  in mt7530_fdb_cmd()
328 		mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);  in mt7530_fdb_write()
446 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
451 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
455 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
460 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
466 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
474 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
480 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
487 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
494 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
497 	mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);  in mt7531_pll_setup()
500 	mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);  in mt7531_pll_setup()
505 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
509 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
518 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);  in mt7530_mib_reset()
519 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);  in mt7530_mib_reset()
1001 	mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));  in mt7530_set_ageing_time()
1039 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);  in mt7530_setup_port5()
1053 		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);  in mt7530_setup_port5()
1062 		mt7530_write(priv, MT7530_P5RGMIITXCR,  in mt7530_setup_port5()
1066 		mt7530_write(priv, MT7530_IO_DRV_CR,  in mt7530_setup_port5()
1070 	mt7530_write(priv, MT753X_MTRAP, val);  in mt7530_setup_port5()
1289 	mt7530_write(priv, MT7530_PVC_P(port),  in mt753x_cpu_port_enable()
1307 	mt7530_write(priv, MT7530_PCR_P(port),  in mt753x_cpu_port_enable()
1608 		mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),  in mt7530_port_set_vlan_unaware()
1610 		mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG  in mt7530_port_set_vlan_unaware()
1807 	mt7530_write(priv, MT7530_VTCR, val);  in mt7530_vlan_cmd()
1863 	mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_add()
1902 		mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_del()
1904 		mt7530_write(priv, MT7530_VAWD1, 0);  in mt7530_hw_vlan_del()
1905 		mt7530_write(priv, MT7530_VAWD2, 0);  in mt7530_hw_vlan_del()
1940 	mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_setup_vlan0()
2047 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_add()
2057 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_add()
2076 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_del()
2081 		mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_del()
2179 	mt7530_write(priv, MT7530_LED_GPIO_OE, 0);  in mt7530_setup_gpio()
2180 	mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);  in mt7530_setup_gpio()
2181 	mt7530_write(priv, MT7530_LED_IO_MODE, 0);  in mt7530_setup_gpio()
2436 	mt7530_write(priv, MT7530_SYS_CTRL,  in mt7530_setup()
2442 		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),  in mt7530_setup()
2618 		mt7530_write(priv, MT753X_CPORT_SPTAG_CFG,  in mt7531_setup_common()
2676 		mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);  in mt7531_setup()
2679 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);  in mt7531_setup()
2888 	mt7530_write(priv, MT7531_CLKGEN_CTRL, val);  in mt7531_rgmii_setup()
3210 		mt7530_write(priv, MT753X_ERLCR_P(port), val);  in mt753x_tc_setup_qdisc_tbf()
3252 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);  in mt7988_setup()