hw/hns/hns_roce_hw_v2.c

1182 		    struct hns_roce_v2_cmq_ring *csq)
1187 	csq->desc_num = CMD_CSQ_DESC_NUM;
1188 	spin_lock_init(&csq->lock);
1189 	csq->flag = TYPE_CSQ;
1190 	csq->head = 0;
1192 	ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1196 	dma = csq->desc_dma_addr;
1200 		   (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1216 	ret = init_csq(hr_dev, &priv->cmq.csq);
1227 	hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1248 	return tail == priv->cmq.csq.head;
1315 	struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1321 	tail = csq->head;
1326 		csq->desc[csq->head++] = desc[i];
1327 		if (csq->head == csq->desc_num)
1328 			csq->head = 0;
1332 	roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1340 			trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]);
1343 			desc_ret = le16_to_cpu(csq->desc[tail++].retval);
1344 			if (tail == csq->desc_num)
1355 			 csq->head, tail);
1356 		csq->head = tail;
1373 	struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1384 		spin_lock_bh(&csq->lock);
1385 		rsv_tail = csq->head;
1389 			spin_unlock_bh(&csq->lock);
1395 			desc[i] = csq->desc[rsv_tail++];
1396 			if (rsv_tail == csq->desc_num)
1399 		spin_unlock_bh(&csq->lock);