Lines Matching +full:0 +full:xffb00000
31 #size-cells = <0>;
50 cpu0: cpu@0 {
52 reg = <0x0>;
60 reg = <0x1>;
68 reg = <0x2>;
76 reg = <0x3>;
86 arm,smc-id = <0x82000010>;
89 #size-cells = <0>;
92 reg = <0x14>;
137 reg = <0x0 0xff610000 0x0 0x200>;
142 gpio-ranges = <&pinctrl 0 0 32>;
149 reg = <0x0 0xffaf0000 0x0 0x200>;
154 gpio-ranges = <&pinctrl 0 32 32>;
161 reg = <0x0 0xffb00000 0x0 0x200>;
166 gpio-ranges = <&pinctrl 0 64 32>;
173 reg = <0x0 0xffb10000 0x0 0x200>;
178 gpio-ranges = <&pinctrl 0 96 32>;
185 reg = <0x0 0xffb20000 0x0 0x200>;
190 gpio-ranges = <&pinctrl 0 128 32>;
208 reg = <0x0 0x0010f000 0x0 0x100>;
225 #clock-cells = <0>;
232 #clock-cells = <0>;
237 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
243 reg = <0x0 0xfed01000 0 0x1000>,
244 <0x0 0xfed02000 0 0x2000>,
245 <0x0 0xfed04000 0 0x2000>,
246 <0x0 0xfed06000 0 0x2000>;
250 #address-cells = <0>;
256 reg = <0x0 0xff200000 0x0 0x20>;
261 reg = <0x0 0xff200080 0x0 0x20>;
266 reg = <0x0 0xff200100 0x0 0x20>;
271 reg = <0x0 0xff200200 0x0 0x20>;
276 reg = <0x0 0xff200280 0x0 0x20>;
281 reg = <0x0 0xff200300 0x0 0x20>;
286 reg = <0x0 0xff200380 0x0 0x20>;
291 reg = <0x0 0xff210000 0x0 0x20>;
296 reg = <0x0 0xff210080 0x0 0x20>;
301 reg = <0x0 0xff220000 0x0 0x20>;
306 reg = <0x0 0xff220080 0x0 0x20>;
311 reg = <0x0 0xff240000 0x0 0x20>;
316 reg = <0x0 0xff250000 0x0 0x20>;
321 reg = <0x0 0xff260000 0x0 0x20>;
326 reg = <0x0 0xff270000 0x0 0x20>;
331 reg = <0x0 0xff270080 0x0 0x20>;
336 reg = <0x0 0xff270100 0x0 0x20>;
341 reg = <0x0 0xff270200 0x0 0x20>;
346 reg = <0x0 0xff270280 0x0 0x20>;
351 reg = <0x0 0xff270300 0x0 0x20>;
356 reg = <0x0 0xff270380 0x0 0x20>;
361 reg = <0x0 0xff270480 0x0 0x20>;
366 reg = <0x0 0xff270500 0x0 0x20>;
371 reg = <0x0 0xff280000 0x0 0x20>;
376 reg = <0x0 0xff280080 0x0 0x20>;
381 reg = <0x0 0xff280100 0x0 0x20>;
386 reg = <0x0 0xff280180 0x0 0x20>;
391 reg = <0x0 0xff280200 0x0 0x20>;
396 reg = <0x0 0xff280280 0x0 0x20>;
401 reg = <0x0 0xff280300 0x0 0x20>;
406 reg = <0x0 0xff280380 0x0 0x20>;
411 reg = <0x0 0xff280400 0x0 0x20>;
416 reg = <0x0 0xff340000 0x0 0x8000>;
421 reg = <0x0 0xff360000 0x0 0x10000>;
426 reg = <0x0 0xff4a0000 0x0 0x30000>;
469 reg = <0x0 0xff540000 0x0 0x40000>;
474 reg = <0x0 0xff600000 0x0 0x2000>;
480 #size-cells = <0>;
489 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
502 #power-domain-cells = <0>;
516 #power-domain-cells = <0>;
530 #power-domain-cells = <0>;
538 reg = <0x0 0xff700000 0x0 0x40000>;
567 reg = <0x0 0xff9c0000 0x0 0x1000>;
574 #size-cells = <0>;
581 reg = <0x0 0xff9d0000 0x0 0x1000>;
588 #size-cells = <0>;
594 reg = <0x0 0xff9f0000 0x0 0x100>;
606 reg = <0x0 0xff9f8000 0x0 0x100>;
618 reg = <0x0 0xffa00000 0x0 0x100>;
630 reg = <0x0 0xffa08000 0x0 0x100>;
642 reg = <0x0 0xffa10000 0x0 0x100>;
654 reg = <0x0 0xffa18000 0x0 0x100>;
666 reg = <0x0 0xffa20000 0x0 0x100>;
678 reg = <0x0 0xffa28000 0x0 0x100>;
691 reg = <0x0 0xffa50000 0x0 0x1000>;
696 #size-cells = <0>;
703 reg = <0x0 0xffa58000 0x0 0x1000>;
708 #size-cells = <0>;
715 reg = <0x0 0xffa60000 0x0 0x1000>;
720 pinctrl-0 = <&i2c2m1_xfer>;
722 #size-cells = <0>;
729 reg = <0x0 0xffa68000 0x0 0x1000>;
734 #size-cells = <0>;
741 reg = <0x0 0xffa70000 0x0 0x1000>;
746 pinctrl-0 = <&i2c4_xfer>;
748 #size-cells = <0>;
755 reg = <0x0 0xffa78000 0x0 0x1000>;
760 #size-cells = <0>;
767 reg = <0x0 0xffa80000 0x0 0x1000>;
772 #size-cells = <0>;
779 reg = <0x0 0xffa88000 0x0 0x1000>;
784 pinctrl-0 = <&i2c7_xfer>;
786 #size-cells = <0>;
793 reg = <0x0 0xffa90000 0x0 0x10>;
803 reg = <0x0 0xffa90010 0x0 0x10>;
813 reg = <0x0 0xffa90020 0x0 0x10>;
823 reg = <0x0 0xffa90030 0x0 0x10>;
833 reg = <0x0 0xffa98000 0x0 0x10>;
843 reg = <0x0 0xffa98010 0x0 0x10>;
853 reg = <0x0 0xffa98020 0x0 0x10>;
863 reg = <0x0 0xffa98030 0x0 0x10>;
872 reg = <0x0 0xffae0000 0x0 0x10000>;
884 reg = <0x0 0xffbd0000 0x0 0x10000>;
908 #address-cells = <0x1>;
909 #size-cells = <0x0>;
913 reg = <0x2>;
917 pinctrl-0 = <&fephym0_led_link>,
924 snps,blen = <0 0 0 0 16 8 4>;
942 reg = <0x0 0xffbe0000 0x0 0x10000>;
966 #address-cells = <0x1>;
967 #size-cells = <0x0>;
971 snps,blen = <0 0 0 0 16 8 4>;
990 reg = <0x0 0xffbf0000 0x0 0x10000>;
1002 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
1014 reg = <0x0 0xffc10000 0x0 0x4000>;
1020 fifo-depth = <0x100>;
1024 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
1033 reg = <0x0 0xffc20000 0x0 0x4000>;
1039 fifo-depth = <0x100>;
1043 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
1052 reg = <0x0 0xffc30000 0x0 0x4000>;
1058 fifo-depth = <0x100>;
1062 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
1072 reg = <0x0 0xffd60000 0x0 0x4000>;
1075 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,