Lines Matching +full:opp +full:- +full:fuse +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
53 #include <soc/tegra/fuse.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60 #include <dt-bindings/gpio/tegra234-gpio.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
390 * struct tegra_pmc - NVIDIA Tegra PMC
406 * @corereq_high: core power request is active-high
407 * @sysclkreq_high: system clock request is active-high
420 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
421 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
487 if (pmc->tz_only) { in tegra_pmc_readl()
491 if (pmc->dev) in tegra_pmc_readl()
492 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
502 return readl(pmc->base + offset); in tegra_pmc_readl()
510 if (pmc->tz_only) { in tegra_pmc_writel()
514 if (pmc->dev) in tegra_pmc_writel()
515 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
522 writel(value, pmc->base + offset); in tegra_pmc_writel()
528 if (pmc->tz_only) in tegra_pmc_scratch_readl()
531 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
537 if (pmc->tz_only) in tegra_pmc_scratch_writel()
540 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
550 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
558 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
563 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
570 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
571 return -EINVAL; in tegra_powergate_lookup()
573 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
577 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
581 return -ENODEV; in tegra_powergate_lookup()
593 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
594 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
602 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
642 * tegra_powergate_set() - set the state of a partition
652 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
653 return -EINVAL; in tegra_powergate_set()
655 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
658 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
662 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
664 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
674 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
681 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
701 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
712 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
713 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); in tegra_powergate_prepare_clocks()
715 if (!pg->clk_rates[i]) { in tegra_powergate_prepare_clocks()
716 err = -EINVAL; in tegra_powergate_prepare_clocks()
720 if (pg->clk_rates[i] <= safe_rate) in tegra_powergate_prepare_clocks()
729 err = clk_set_rate(pg->clks[i], safe_rate); in tegra_powergate_prepare_clocks()
737 while (i--) in tegra_powergate_prepare_clocks()
738 clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_prepare_clocks()
748 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
749 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_unprepare_clocks()
761 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
762 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
770 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
771 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
779 while (i--) in tegra_powergate_enable_clocks()
780 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
790 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
796 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
812 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
818 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
824 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
825 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
846 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
865 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
875 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
888 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
903 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
909 pg->genpd.name, err); in tegra_genpd_power_on()
913 reset_control_release(pg->reset); in tegra_genpd_power_on()
922 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
925 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
928 pg->genpd.name, err); in tegra_genpd_power_off()
935 pg->genpd.name, err); in tegra_genpd_power_off()
936 reset_control_release(pg->reset); in tegra_genpd_power_off()
943 * tegra_powergate_power_on() - power on partition
949 return -EINVAL; in tegra_powergate_power_on()
956 * tegra_powergate_power_off() - power off partition
962 return -EINVAL; in tegra_powergate_power_off()
969 * tegra_powergate_is_powered() - check if partition is powered
976 return -EINVAL; in tegra_powergate_is_powered()
982 * tegra_powergate_remove_clamping() - remove power clamps for partition
988 return -EINVAL; in tegra_powergate_remove_clamping()
995 * tegra_powergate_sequence_power_up() - power up partition
1009 return -EINVAL; in tegra_powergate_sequence_power_up()
1013 return -ENOMEM; in tegra_powergate_sequence_power_up()
1015 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_sequence_power_up()
1016 if (!pg->clk_rates) { in tegra_powergate_sequence_power_up()
1017 kfree(pg->clks); in tegra_powergate_sequence_power_up()
1018 return -ENOMEM; in tegra_powergate_sequence_power_up()
1021 pg->id = id; in tegra_powergate_sequence_power_up()
1022 pg->clks = &clk; in tegra_powergate_sequence_power_up()
1023 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
1024 pg->reset = rst; in tegra_powergate_sequence_power_up()
1025 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1029 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1032 kfree(pg->clk_rates); in tegra_powergate_sequence_power_up()
1040 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1050 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1051 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1053 return -EINVAL; in tegra_get_cpu_powergate_id()
1057 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1072 * tegra_pmc_cpu_power_on() - power on CPU partition
1087 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1115 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_program_reboot_reason()
1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1175 seq_printf(s, "------------------\n"); in powergate_show()
1177 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1182 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1200 return -ENODEV; in tegra_powergate_of_get_clks()
1202 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1203 if (!pg->clks) in tegra_powergate_of_get_clks()
1204 return -ENOMEM; in tegra_powergate_of_get_clks()
1206 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_of_get_clks()
1207 if (!pg->clk_rates) { in tegra_powergate_of_get_clks()
1208 kfree(pg->clks); in tegra_powergate_of_get_clks()
1209 return -ENOMEM; in tegra_powergate_of_get_clks()
1213 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1214 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1215 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1220 pg->num_clks = count; in tegra_powergate_of_get_clks()
1225 while (i--) in tegra_powergate_of_get_clks()
1226 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1228 kfree(pg->clk_rates); in tegra_powergate_of_get_clks()
1229 kfree(pg->clks); in tegra_powergate_of_get_clks()
1237 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1240 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1241 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1242 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1247 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1254 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1256 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1260 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1265 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1266 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1274 struct device *dev = pmc->dev; in tegra_powergate_add()
1281 return -ENOMEM; in tegra_powergate_add()
1283 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1286 err = -ENODEV; in tegra_powergate_add()
1294 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1296 pg->id = id; in tegra_powergate_add()
1297 pg->genpd.name = np->name; in tegra_powergate_add()
1298 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1299 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1300 pg->pmc = pmc; in tegra_powergate_add()
1302 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1323 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1330 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1337 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1342 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1345 reset_control_put(pg->reset); in tegra_powergate_add()
1348 while (pg->num_clks--) in tegra_powergate_add()
1349 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1351 kfree(pg->clks); in tegra_powergate_add()
1354 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1364 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1369 unsigned int level) in tegra_pmc_core_pd_set_performance_state() argument
1371 struct dev_pm_opp *opp; in tegra_pmc_core_pd_set_performance_state() local
1374 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); in tegra_pmc_core_pd_set_performance_state()
1375 if (IS_ERR(opp)) { in tegra_pmc_core_pd_set_performance_state()
1376 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", in tegra_pmc_core_pd_set_performance_state()
1377 level, opp); in tegra_pmc_core_pd_set_performance_state()
1378 return PTR_ERR(opp); in tegra_pmc_core_pd_set_performance_state()
1381 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1382 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1383 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1385 dev_pm_opp_put(opp); in tegra_pmc_core_pd_set_performance_state()
1388 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", in tegra_pmc_core_pd_set_performance_state()
1389 level, err); in tegra_pmc_core_pd_set_performance_state()
1402 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1404 return -ENOMEM; in tegra_pmc_core_pd_add()
1406 genpd->name = "core"; in tegra_pmc_core_pd_add()
1407 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; in tegra_pmc_core_pd_add()
1409 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1411 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1412 "failed to set core OPP regulator\n"); in tegra_pmc_core_pd_add()
1416 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1422 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1426 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1447 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_init()
1466 if (of_parse_phandle_with_args(child, "power-domains", in tegra_powergate_init()
1467 "#power-domain-cells", in tegra_powergate_init()
1491 reset_control_put(pg->reset); in tegra_powergate_remove()
1493 while (pg->num_clks--) in tegra_powergate_remove()
1494 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1496 kfree(pg->clks); in tegra_powergate_remove()
1498 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1524 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_remove_all()
1536 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1537 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1538 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1551 if (pad->dpd == UINT_MAX) in tegra_io_pad_prepare()
1552 return -EINVAL; in tegra_io_pad_prepare()
1554 *request = pad->request; in tegra_io_pad_prepare()
1555 *status = pad->status; in tegra_io_pad_prepare()
1556 *mask = BIT(pad->dpd); in tegra_io_pad_prepare()
1558 if (pmc->clk) { in tegra_io_pad_prepare()
1559 rate = pmc->rate; in tegra_io_pad_prepare()
1561 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1562 return -ENODEV; in tegra_io_pad_prepare()
1591 return -ETIMEDOUT; in tegra_io_pad_poll()
1596 if (pmc->clk) in tegra_io_pad_unprepare()
1601 * tegra_io_pad_power_enable() - enable power to I/O pad
1615 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1616 return -ENOENT; in tegra_io_pad_power_enable()
1619 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1623 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1631 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1638 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1644 * tegra_io_pad_power_disable() - disable power to I/O pad
1658 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1659 return -ENOENT; in tegra_io_pad_power_disable()
1662 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1666 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1674 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1681 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1694 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1695 return -ENOENT; in tegra_io_pad_is_powered()
1698 if (pad->dpd == UINT_MAX) in tegra_io_pad_is_powered()
1699 return -EINVAL; in tegra_io_pad_is_powered()
1701 status = pad->status; in tegra_io_pad_is_powered()
1702 mask = BIT(pad->dpd); in tegra_io_pad_is_powered()
1717 return -ENOENT; in tegra_io_pad_set_voltage()
1719 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1720 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1722 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1724 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1728 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1730 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1734 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1736 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1743 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1745 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1750 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1764 return -ENOENT; in tegra_io_pad_get_voltage()
1766 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1767 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1769 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1774 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1781 * tegra_io_rail_power_on() - enable power to I/O rail
1793 * tegra_io_rail_power_off() - disable power to I/O rail
1807 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1815 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1830 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1840 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1844 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1859 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1860 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1864 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1868 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1872 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1876 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1881 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1883 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1884 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1886 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1888 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1889 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1891 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1893 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1895 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1897 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1898 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1900 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1901 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1903 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1905 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1906 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1908 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1909 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1911 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1912 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1914 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1915 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1917 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1919 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1920 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1922 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1923 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1930 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1931 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1932 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1933 return -ENOMEM; in tegra_pmc_init()
1935 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1936 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1937 return -ENOMEM; in tegra_pmc_init()
1939 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1940 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1941 return -ENOMEM; in tegra_pmc_init()
1943 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1944 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1945 return -ENOMEM; in tegra_pmc_init()
1948 if (pmc->soc->init) in tegra_pmc_init()
1949 pmc->soc->init(pmc); in tegra_pmc_init()
1958 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1962 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1965 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1967 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1971 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1976 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1977 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1981 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1982 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1986 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1987 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1991 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
2014 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
2024 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2034 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2042 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2052 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2077 return -EINVAL; in tegra_io_pad_pinconf_get()
2081 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2089 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2097 return -EINVAL; in tegra_io_pad_pinconf_get()
2118 return -EINVAL; in tegra_io_pad_pinconf_set()
2127 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
2129 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
2136 return -EINVAL; in tegra_io_pad_pinconf_set()
2137 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2142 return -EINVAL; in tegra_io_pad_pinconf_set()
2164 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2167 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2168 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2169 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2171 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2173 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2174 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2175 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2188 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2189 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2190 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2192 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2195 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2205 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2206 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2207 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2209 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2212 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2219 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2222 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2230 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2244 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
2245 return -EINVAL; in tegra_pmc_irq_translate()
2247 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2248 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
2256 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
2257 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2263 return -EINVAL; in tegra_pmc_irq_alloc()
2265 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2266 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
2269 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
2272 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2276 event->id, in tegra_pmc_irq_alloc()
2277 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2281 /* simple hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2282 if (event->irq == 0) { in tegra_pmc_irq_alloc()
2283 err = irq_domain_disconnect_hierarchy(domain->parent, virq); in tegra_pmc_irq_alloc()
2287 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2290 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
2291 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2300 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2301 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2302 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2306 event->id, in tegra_pmc_irq_alloc()
2307 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2309 /* GPIO hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2310 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2311 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2317 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2318 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2335 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2336 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2346 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2369 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2370 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2372 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2395 return -EINVAL; in tegra210_pmc_irq_set_type()
2408 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2410 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2411 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2420 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2421 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2424 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2427 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2434 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2437 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2447 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2453 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2454 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2460 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2461 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2466 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2467 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2471 return -EINVAL; in tegra186_pmc_irq_set_type()
2474 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2481 if (data->parent_data) in tegra_irq_mask_parent()
2487 if (data->parent_data) in tegra_irq_unmask_parent()
2493 if (data->parent_data) in tegra_irq_eoi_parent()
2501 if (data->parent_data) in tegra_irq_set_affinity_parent()
2504 return -EINVAL; in tegra_irq_set_affinity_parent()
2512 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2521 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2522 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2523 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2524 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2525 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2526 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2527 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2529 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2531 if (!pmc->domain) { in tegra_pmc_irq_init()
2532 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2533 return -ENOMEM; in tegra_pmc_irq_init()
2547 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2551 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2555 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2560 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2578 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2589 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2590 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2591 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2592 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2593 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2603 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2622 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2631 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2651 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2653 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2655 init.name = data->name; in tegra_pmc_clk_out_register()
2657 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2658 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2662 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2663 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2664 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2665 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2667 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2674 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2681 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2690 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2707 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2709 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2717 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2718 gate->offs = offset; in tegra_pmc_clk_gate_register()
2719 gate->shift = shift; in tegra_pmc_clk_gate_register()
2721 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2732 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2733 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2739 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2743 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2744 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2745 if (!clk_data->clks) in tegra_pmc_clock_register()
2748 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2751 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2753 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2756 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2760 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2761 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2765 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2767 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2769 data->name, err); in tegra_pmc_clock_register()
2773 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2776 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2784 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2795 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2803 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2809 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2814 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2867 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2868 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2871 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2881 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2895 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2896 return -ENODEV; in tegra_pmc_probe()
2898 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2902 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, in tegra_pmc_probe()
2914 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2915 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2916 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2918 pmc->wake = base; in tegra_pmc_probe()
2923 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2924 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2925 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2927 pmc->aotag = base; in tegra_pmc_probe()
2932 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2933 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2934 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2936 pmc->scratch = base; in tegra_pmc_probe()
2939 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2940 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2941 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2945 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2948 err = devm_register_reboot_notifier(&pdev->dev, in tegra_pmc_probe()
2951 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", in tegra_pmc_probe()
2956 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2961 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2967 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2970 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2975 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2985 if (pmc->clk) { in tegra_pmc_probe()
2986 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2987 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2988 &pmc->clk_nb); in tegra_pmc_probe()
2990 dev_err(&pdev->dev, in tegra_pmc_probe()
2995 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2998 pmc->dev = &pdev->dev; in tegra_pmc_probe()
3002 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); in tegra_pmc_probe()
3018 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3026 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3027 iounmap(pmc->base); in tegra_pmc_probe()
3028 pmc->base = base; in tegra_pmc_probe()
3029 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3031 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3036 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3037 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3044 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
3046 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
3047 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
3058 writel(value, pmc->wake + offset); in wke_32kwritel()
3062 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) in wke_write_wake_level() argument
3067 value = readl(pmc->wake + offset); in wke_write_wake_level()
3068 if (level) in wke_write_wake_level()
3073 writel(value, pmc->wake + offset); in wke_write_wake_level()
3080 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3081 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3094 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3104 * the polarity of the wake level from 0->1 while latching to force in wke_read_sw_wake_status()
3107 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3119 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3121 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3122 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3125 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3135 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3136 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3137 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3150 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3157 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3160 if (!desc || !desc->action || !desc->action->name) { in tegra186_pmc_process_wake_events()
3161 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3165 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3175 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3176 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3177 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3187 /* flip the wakeup trigger for dual-edge triggered pads in tegra186_pmc_wake_syscore_suspend()
3190 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3191 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3192 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3193 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3255 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3260 if (pmc->corereq_high) in tegra20_pmc_init()
3274 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3275 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3276 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3277 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3512 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3514 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3515 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3516 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3517 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3545 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3547 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3548 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3549 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3550 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3627 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3649 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3650 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3651 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3652 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3653 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3657 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3663 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3691 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3692 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3693 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3694 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3698 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3704 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3758 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3759 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3760 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3761 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3762 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3766 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3772 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3773 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3774 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3786 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3788 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3789 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3791 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3792 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3827 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3829 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3830 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3832 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3833 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3847 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3848 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3850 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3862 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3864 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3872 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3954 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3955 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3956 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3957 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3965 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3966 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3968 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3969 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3970 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3971 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3972 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3976 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3978 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3979 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3981 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3982 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3983 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3985 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3996 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3997 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3999 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
4000 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4092 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4093 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4094 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4095 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4096 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4097 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4098 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4139 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4146 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4147 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4148 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4149 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4157 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4164 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4165 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4166 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4167 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4227 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4265 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4266 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4267 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4268 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4269 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4270 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4271 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4272 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4273 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4282 * Newer device-trees have power domains, but we need to prepare all in tegra_pmc_sync_state()
4283 * device drivers with runtime PM and OPP support first, otherwise in tegra_pmc_sync_state()
4286 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4290 * Older device-trees don't have core PD, and thus, there are in tegra_pmc_sync_state()
4294 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4297 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4299 /* this is a no-op if core regulator isn't used */ in tegra_pmc_sync_state()
4300 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4302 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4310 .name = "tegra-pmc",
4326 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4333 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4334 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4336 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
4343 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4360 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4365 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
4366 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
4369 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
4385 * nice with multi-platform kernels. in tegra_pmc_early_init()
4397 return -ENXIO; in tegra_pmc_early_init()
4401 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4402 if (!pmc->base) { in tegra_pmc_early_init()
4405 return -ENXIO; in tegra_pmc_early_init()
4409 pmc->soc = match->data; in tegra_pmc_early_init()
4411 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4412 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4415 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4416 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4417 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4421 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
4423 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
4425 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()