Lines Matching +full:negative +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0
14 * enum ice_dpll_pin_type - enumerate ice pin types:
30 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
34 * ice_dpll_is_reset - check if reset is in progress
41 * * false - no reset in progress
42 * * true - reset in progress
46 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
54 * ice_dpll_pin_freq_set - set pin's frequency
63 * Context: Called under pf->dplls.lock
65 * * 0 - success
66 * * negative - error on AQ or wrong pin type given
79 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
80 pin->flags[0], freq, 0); in ice_dpll_pin_freq_set()
84 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
88 return -EINVAL; in ice_dpll_pin_freq_set()
94 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
95 freq, pin->idx); in ice_dpll_pin_freq_set()
98 pin->freq = freq; in ice_dpll_pin_freq_set()
104 * ice_dpll_frequency_set - wrapper for pin callback for set frequency
115 * Context: Acquires pf->dplls.lock
117 * * 0 - success
118 * * negative - error pin not found or couldn't set in hw
129 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set()
133 return -EBUSY; in ice_dpll_frequency_set()
135 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
137 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
143 * ice_dpll_input_frequency_set - input pin callback for set frequency
153 * Context: Calls a function which acquires pf->dplls.lock
155 * * 0 - success
156 * * negative - error pin not found or couldn't set in hw
168 * ice_dpll_output_frequency_set - output pin callback for set frequency
178 * Context: Calls a function which acquires pf->dplls.lock
180 * * 0 - success
181 * * negative - error pin not found or couldn't set in hw
193 * ice_dpll_frequency_get - wrapper for pin callback for get frequency
204 * Context: Acquires pf->dplls.lock
206 * * 0 - success
207 * * negative - error pin not found or couldn't get from hw
217 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get()
219 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
220 *frequency = p->freq; in ice_dpll_frequency_get()
221 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
227 * ice_dpll_input_frequency_get - input pin callback for get frequency
237 * Context: Calls a function which acquires pf->dplls.lock
239 * * 0 - success
240 * * negative - error pin not found or couldn't get from hw
252 * ice_dpll_output_frequency_get - output pin callback for get frequency
262 * Context: Calls a function which acquires pf->dplls.lock
264 * * 0 - success
265 * * negative - error pin not found or couldn't get from hw
277 * ice_dpll_pin_enable - enable a pin on dplls
284 * Enable a pin on both dplls. Store current state in pin->flags.
286 * Context: Called under pf->dplls.lock
288 * * 0 - OK
289 * * negative - error
301 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_enable()
304 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_enable()
308 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_enable()
311 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, dpll_idx, in ice_dpll_pin_enable()
315 return -EINVAL; in ice_dpll_pin_enable()
320 ret, ice_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_enable()
321 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_enable()
327 * ice_dpll_pin_disable - disable a pin on dplls
333 * Disable a pin on both dplls. Store current state in pin->flags.
335 * Context: Called under pf->dplls.lock
337 * * 0 - OK
338 * * negative - error
350 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_disable()
352 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_disable()
355 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_disable()
357 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, 0, 0, 0); in ice_dpll_pin_disable()
360 return -EINVAL; in ice_dpll_pin_disable()
365 ret, ice_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_disable()
366 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_disable()
372 * ice_dpll_pin_state_update - update pin's state
382 * Context: Called under pf->dplls.lock
384 * * 0 - OK
385 * * negative - error
397 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL, in ice_dpll_pin_state_update()
398 NULL, &pin->flags[0], in ice_dpll_pin_state_update()
399 &pin->freq, &pin->phase_adjust); in ice_dpll_pin_state_update()
402 if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
403 if (pin->pin) { in ice_dpll_pin_state_update()
404 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
405 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
408 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
409 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
413 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
415 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
419 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
421 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
426 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
427 &pin->flags[0], &parent, in ice_dpll_pin_state_update()
428 &pin->freq, NULL); in ice_dpll_pin_state_update()
433 if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
434 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
435 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
438 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
439 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
443 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
445 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
450 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
454 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
456 &pin->flags[parent], in ice_dpll_pin_state_update()
461 pin->flags[parent]) in ice_dpll_pin_state_update()
462 pin->state[parent] = DPLL_PIN_STATE_CONNECTED; in ice_dpll_pin_state_update()
464 pin->state[parent] = in ice_dpll_pin_state_update()
469 return -EINVAL; in ice_dpll_pin_state_update()
478 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
479 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
484 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
485 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
490 * ice_dpll_hw_input_prio_set - set input priority value in hardware
499 * Context: Called under pf->dplls.lock
501 * * 0 - success
502 * * negative - failure
511 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
517 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
518 prio, pin->idx); in ice_dpll_hw_input_prio_set()
520 dpll->input_prio[pin->idx] = prio; in ice_dpll_hw_input_prio_set()
526 * ice_dpll_lock_status_get - get dpll lock status callback
534 * Context: Acquires pf->dplls.lock
536 * * 0 - success
537 * * negative - failure
545 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get()
547 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
548 *status = d->dpll_state; in ice_dpll_lock_status_get()
549 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
555 * ice_dpll_mode_get - get dpll's working mode
563 * Context: Acquires pf->dplls.lock
565 * * 0 - success
566 * * negative - failure
573 struct ice_pf *pf = d->pf; in ice_dpll_mode_get()
575 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
576 *mode = d->mode; in ice_dpll_mode_get()
577 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
583 * ice_dpll_pin_state_set - set pin's state on dpll
594 * Context: Acquires pf->dplls.lock
596 * * 0 - OK or no change required
597 * * negative - error
607 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set()
611 return -EBUSY; in ice_dpll_pin_state_set()
613 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
615 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
618 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
621 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
627 * ice_dpll_output_state_set - enable/disable output pin on dpll device
637 * Context: Calls a function which acquires pf->dplls.lock
639 * * 0 - successfully enabled mode
640 * * negative - failed to enable mode
652 if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED) in ice_dpll_output_state_set()
660 * ice_dpll_input_state_set - enable/disable input pin on dpll levice
670 * Context: Calls a function which acquires pf->dplls.lock
672 * * 0 - successfully enabled mode
673 * * negative - failed to enable mode
688 * ice_dpll_pin_state_get - set pin's state on dpll
699 * Context: Acquires pf->dplls.lock
701 * * 0 - success
702 * * negative - failed to get state
713 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get()
717 return -EBUSY; in ice_dpll_pin_state_get()
719 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
725 *state = p->state[d->dpll_idx]; in ice_dpll_pin_state_get()
728 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
734 * ice_dpll_output_state_get - get output pin state on dpll device
744 * Context: Calls a function which acquires pf->dplls.lock
746 * * 0 - success
747 * * negative - failed to get state
760 * ice_dpll_input_state_get - get input pin state on dpll device
770 * Context: Calls a function which acquires pf->dplls.lock
772 * * 0 - success
773 * * negative - failed to get state
786 * ice_dpll_input_prio_get - get dpll's input prio
791 * @prio: on success - returns input priority on dpll
796 * Context: Acquires pf->dplls.lock
798 * * 0 - success
799 * * negative - failure
808 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get()
810 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
811 *prio = d->input_prio[p->idx]; in ice_dpll_input_prio_get()
812 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
818 * ice_dpll_input_prio_set - set dpll input prio
828 * Context: Acquires pf->dplls.lock
830 * * 0 - success
831 * * negative - failure
840 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set()
844 return -EBUSY; in ice_dpll_input_prio_set()
846 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
848 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
854 * ice_dpll_input_direction - callback for get input pin direction
865 * * 0 - success
879 * ice_dpll_output_direction - callback for get output pin direction
890 * * 0 - success
904 * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
912 * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
914 * Context: Acquires pf->dplls.lock
916 * * 0 - success
917 * * negative - error
926 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get()
928 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
929 *phase_adjust = p->phase_adjust; in ice_dpll_pin_phase_adjust_get()
930 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
936 * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
945 * Helper for dpll subsystem callback. Handler for setting phase adjust value
948 * Context: Acquires pf->dplls.lock
950 * * 0 - success
951 * * negative - error
962 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set()
967 return -EBUSY; in ice_dpll_pin_phase_adjust_set()
969 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
973 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
975 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_pin_phase_adjust_set()
977 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
982 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) in ice_dpll_pin_phase_adjust_set()
984 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
986 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
990 ret = -EINVAL; in ice_dpll_pin_phase_adjust_set()
993 p->phase_adjust = phase_adjust; in ice_dpll_pin_phase_adjust_set()
994 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
999 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1000 phase_adjust, p->idx, d->dpll_idx); in ice_dpll_pin_phase_adjust_set()
1006 * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
1014 * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
1017 * Context: Calls a function which acquires pf->dplls.lock
1019 * * 0 - success
1020 * * negative - error
1034 * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
1042 * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
1045 * Context: Calls a function which acquires pf->dplls.lock
1047 * * 0 - success
1048 * * negative - error
1065 * ice_dpll_phase_offset_get - callback for get dpll phase shift value
1073 * Dpll subsystem callback. Handler for getting phase shift value between
1076 * Context: Acquires pf->dplls.lock
1078 * * 0 - success
1079 * * negative - error
1087 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get()
1089 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1090 if (d->active_input == pin) in ice_dpll_phase_offset_get()
1091 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1094 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1100 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
1110 * Context: Acquires pf->dplls.lock
1112 * * 0 - success
1113 * * negative - failure
1124 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set()
1125 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_set()
1129 return -EBUSY; in ice_dpll_rclk_state_on_pin_set()
1131 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1132 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
1133 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
1136 if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) || in ice_dpll_rclk_state_on_pin_set()
1137 (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) { in ice_dpll_rclk_state_on_pin_set()
1140 p->idx, state, parent->idx); in ice_dpll_rclk_state_on_pin_set()
1143 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
1144 &p->freq); in ice_dpll_rclk_state_on_pin_set()
1149 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
1150 state, p->idx, parent->idx); in ice_dpll_rclk_state_on_pin_set()
1152 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1158 * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin
1168 * Context: Acquires pf->dplls.lock
1170 * * 0 - success
1171 * * negative - failure
1181 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get()
1182 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_get()
1186 return -EBUSY; in ice_dpll_rclk_state_on_pin_get()
1188 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1189 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
1190 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
1198 *state = p->state[hw_idx]; in ice_dpll_rclk_state_on_pin_get()
1201 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1241 * ice_generate_clock_id - generates unique clock_id for registering dpll.
1251 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
1255 * ice_dpll_notify_changes - notify dpll subsystem about changes
1264 if (d->prev_dpll_state != d->dpll_state) { in ice_dpll_notify_changes()
1265 d->prev_dpll_state = d->dpll_state; in ice_dpll_notify_changes()
1266 dpll_device_change_ntf(d->dpll); in ice_dpll_notify_changes()
1268 if (d->prev_input != d->active_input) { in ice_dpll_notify_changes()
1269 if (d->prev_input) in ice_dpll_notify_changes()
1270 dpll_pin_change_ntf(d->prev_input); in ice_dpll_notify_changes()
1271 d->prev_input = d->active_input; in ice_dpll_notify_changes()
1272 if (d->active_input) { in ice_dpll_notify_changes()
1273 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
1277 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
1278 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
1279 if (!pin_notified && d->active_input) in ice_dpll_notify_changes()
1280 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
1285 * ice_dpll_update_state - update dpll state
1292 * Context: Called by kworker under pf->dplls.lock
1294 * * 0 - success
1295 * * negative - AQ failure
1303 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
1304 &d->input_idx, &d->ref_state, &d->eec_mode, in ice_dpll_update_state()
1305 &d->phase_offset, &d->dpll_state); in ice_dpll_update_state()
1309 d->dpll_idx, d->prev_input_idx, d->input_idx, in ice_dpll_update_state()
1310 d->dpll_state, d->prev_dpll_state, d->mode); in ice_dpll_update_state()
1314 d->dpll_idx, ret, in ice_dpll_update_state()
1315 ice_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
1319 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED || in ice_dpll_update_state()
1320 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ) in ice_dpll_update_state()
1321 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
1322 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1326 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER || in ice_dpll_update_state()
1327 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) { in ice_dpll_update_state()
1328 d->active_input = NULL; in ice_dpll_update_state()
1329 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) in ice_dpll_update_state()
1330 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1331 d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
1332 d->input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
1337 } else if (d->input_idx != d->prev_input_idx) { in ice_dpll_update_state()
1338 if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
1339 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
1344 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
1345 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1346 d->active_input = p->pin; in ice_dpll_update_state()
1351 d->prev_input_idx = d->input_idx; in ice_dpll_update_state()
1358 * ice_dpll_periodic_work - DPLLs periodic worker
1362 * Context: Holds pf->dplls.lock
1368 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
1369 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
1372 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
1374 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
1379 d->cgu_state_acq_err_num++; in ice_dpll_periodic_work()
1381 if (d->cgu_state_acq_err_num > in ice_dpll_periodic_work()
1385 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1389 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1395 kthread_queue_delayed_work(d->kworker, &d->work, in ice_dpll_periodic_work()
1401 * ice_dpll_release_pins - release pins resources from dpll subsystem
1416 * ice_dpll_get_pins - get pins from dpll subsystem
1423 * Get pins - allocate - in dpll subsystem, store them in pin field of given
1427 * * 0 - success
1428 * * negative - allocation failure reason
1448 while (--i >= 0) in ice_dpll_get_pins()
1454 * ice_dpll_unregister_pins - unregister pins from a dpll
1474 * ice_dpll_register_pins - register pins with a dpll
1483 * * 0 - success
1484 * * negative - registration failure reason
1501 while (--i >= 0) in ice_dpll_register_pins()
1507 * ice_dpll_deinit_direct_pins - deinitialize direct pins
1532 * ice_dpll_init_direct_pins - initialize direct pins
1546 * * 0 - success
1547 * * negative - registration failure reason
1557 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
1579 * ice_dpll_deinit_rclk_pin - release rclk pin resources
1586 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin()
1591 for (i = 0; i < rclk->num_parents; i++) { in ice_dpll_deinit_rclk_pin()
1592 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
1595 dpll_pin_on_pin_unregister(parent, rclk->pin, in ice_dpll_deinit_rclk_pin()
1598 if (WARN_ON_ONCE(!vsi || !vsi->netdev)) in ice_dpll_deinit_rclk_pin()
1600 dpll_netdev_pin_clear(vsi->netdev); in ice_dpll_deinit_rclk_pin()
1601 dpll_pin_put(rclk->pin); in ice_dpll_deinit_rclk_pin()
1605 * ice_dpll_init_rclk_pins - initialize recovered clock pin
1616 * * 0 - success
1617 * * negative - registration failure reason
1628 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
1631 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
1632 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
1634 ret = -ENODEV; in ice_dpll_init_rclk_pins()
1637 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1638 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1642 if (WARN_ON((!vsi || !vsi->netdev))) in ice_dpll_init_rclk_pins()
1643 return -EINVAL; in ice_dpll_init_rclk_pins()
1644 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
1650 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
1651 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1652 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1659 * ice_dpll_deinit_pins - deinitialize direct pins
1668 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
1669 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
1670 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
1671 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
1672 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
1673 struct ice_dpll *de = &d->eec; in ice_dpll_deinit_pins()
1674 struct ice_dpll *dp = &d->pps; in ice_dpll_deinit_pins()
1678 ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
1680 ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
1685 ice_dpll_unregister_pins(dp->dpll, outputs, in ice_dpll_deinit_pins()
1687 ice_dpll_unregister_pins(de->dpll, outputs, in ice_dpll_deinit_pins()
1694 * ice_dpll_init_pins - init pins and register pins with a dplls
1702 * * 0 - success
1703 * * negative - initialization failure reason
1710 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
1711 pf->dplls.num_inputs, in ice_dpll_init_pins()
1713 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
1717 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1718 pf->dplls.num_inputs, in ice_dpll_init_pins()
1719 pf->dplls.num_outputs, in ice_dpll_init_pins()
1721 pf->dplls.eec.dpll, in ice_dpll_init_pins()
1722 pf->dplls.pps.dpll); in ice_dpll_init_pins()
1726 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id; in ice_dpll_init_pins()
1727 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx, in ice_dpll_init_pins()
1734 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1735 pf->dplls.num_outputs, in ice_dpll_init_pins()
1736 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1737 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1739 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
1740 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1741 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1746 * ice_dpll_deinit_dpll - deinitialize dpll device
1758 dpll_device_unregister(d->dpll, &ice_dpll_ops, d); in ice_dpll_deinit_dpll()
1759 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll()
1763 * ice_dpll_init_dpll - initialize dpll device in dpll subsystem
1773 * * 0 - success
1774 * * negative - initialization failure reason
1780 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
1783 d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE); in ice_dpll_init_dpll()
1784 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll()
1785 ret = PTR_ERR(d->dpll); in ice_dpll_init_dpll()
1790 d->pf = pf; in ice_dpll_init_dpll()
1793 ret = dpll_device_register(d->dpll, type, &ice_dpll_ops, d); in ice_dpll_init_dpll()
1795 dpll_device_put(d->dpll); in ice_dpll_init_dpll()
1804 * ice_dpll_deinit_worker - deinitialize dpll kworker
1811 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
1813 kthread_cancel_delayed_work_sync(&d->work); in ice_dpll_deinit_worker()
1814 kthread_destroy_worker(d->kworker); in ice_dpll_deinit_worker()
1818 * ice_dpll_init_worker - Initialize DPLLs periodic worker
1823 * Context: Shall be called after pf->dplls.lock is initialized.
1825 * * 0 - success
1826 * * negative - create worker failure
1830 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
1833 kthread_init_delayed_work(&d->work, ice_dpll_periodic_work); in ice_dpll_init_worker()
1834 kworker = kthread_create_worker(0, "ice-dplls-%s", in ice_dpll_init_worker()
1838 d->kworker = kworker; in ice_dpll_init_worker()
1839 d->cgu_state_acq_err_num = 0; in ice_dpll_init_worker()
1840 kthread_queue_delayed_work(d->kworker, &d->work, 0); in ice_dpll_init_worker()
1846 * ice_dpll_init_info_direct_pins - initializes direct pins info
1854 * * 0 - success
1855 * * negative - init failure reason
1861 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
1862 int num_pins, i, ret = -EINVAL; in ice_dpll_init_info_direct_pins()
1863 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
1871 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
1872 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
1876 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
1877 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
1881 return -EINVAL; in ice_dpll_init_info_direct_pins()
1890 ret = ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i, in ice_dpll_init_info_direct_pins()
1891 &de->input_prio[i]); in ice_dpll_init_info_direct_pins()
1894 ret = ice_aq_get_cgu_ref_prio(hw, dp->dpll_idx, i, in ice_dpll_init_info_direct_pins()
1895 &dp->input_prio[i]); in ice_dpll_init_info_direct_pins()
1901 pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
1903 -pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
1906 pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
1908 -pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
1927 * ice_dpll_init_info_rclk_pin - initializes rclk pin information
1930 * Init information for rclk pin, cache them in pf->dplls.rclk.
1933 * * 0 - success
1934 * * negative - init failure reason
1938 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
1940 pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT; in ice_dpll_init_info_rclk_pin()
1941 pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; in ice_dpll_init_info_rclk_pin()
1942 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
1949 * ice_dpll_init_pins_info - init pins info wrapper
1956 * * 0 - success
1957 * * negative - init failure reason
1969 return -EINVAL; in ice_dpll_init_pins_info()
1974 * ice_dpll_deinit_info - release memory allocated for pins info
1981 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
1982 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
1983 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
1984 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
1988 * ice_dpll_init_info - prepare pf's dpll information structure
1992 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
1995 * * 0 - success
1996 * * negative - init failure reason
2001 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
2002 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
2003 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
2004 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
2007 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
2012 ret, ice_aq_str(hw->adminq.sq_last_status)); in ice_dpll_init_info()
2016 de->dpll_idx = abilities.eec_dpll_idx; in ice_dpll_init_info()
2017 dp->dpll_idx = abilities.pps_dpll_idx; in ice_dpll_init_info()
2018 d->num_inputs = abilities.num_inputs; in ice_dpll_init_info()
2019 d->num_outputs = abilities.num_outputs; in ice_dpll_init_info()
2020 d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj); in ice_dpll_init_info()
2021 d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj); in ice_dpll_init_info()
2023 alloc_size = sizeof(*d->inputs) * d->num_inputs; in ice_dpll_init_info()
2024 d->inputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2025 if (!d->inputs) in ice_dpll_init_info()
2026 return -ENOMEM; in ice_dpll_init_info()
2028 alloc_size = sizeof(*de->input_prio) * d->num_inputs; in ice_dpll_init_info()
2029 de->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2030 if (!de->input_prio) in ice_dpll_init_info()
2031 return -ENOMEM; in ice_dpll_init_info()
2033 dp->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2034 if (!dp->input_prio) in ice_dpll_init_info()
2035 return -ENOMEM; in ice_dpll_init_info()
2042 alloc_size = sizeof(*d->outputs) * d->num_outputs; in ice_dpll_init_info()
2043 d->outputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
2044 if (!d->outputs) { in ice_dpll_init_info()
2045 ret = -ENOMEM; in ice_dpll_init_info()
2054 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
2055 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
2058 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
2059 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
2063 de->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
2064 dp->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
2067 "%s - success, inputs:%u, outputs:%u rclk-parents:%u\n", in ice_dpll_init_info()
2068 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); in ice_dpll_init_info()
2074 "%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n", in ice_dpll_init_info()
2075 __func__, d->inputs, de->input_prio, in ice_dpll_init_info()
2076 dp->input_prio, d->outputs); in ice_dpll_init_info()
2082 * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem
2090 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2096 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
2101 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
2102 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
2104 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
2108 * ice_dpll_init - initialize support for dpll subsystem
2115 * Context: Initializes pf->dplls.lock mutex.
2120 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
2123 mutex_init(&d->lock); in ice_dpll_init()
2127 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
2130 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
2141 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
2148 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
2150 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
2154 mutex_destroy(&d->lock); in ice_dpll_init()