Lines Matching full:pf
35 * @pf: private board structure
44 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack) in ice_dpll_is_reset() argument
46 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
47 NL_SET_ERR_MSG(extack, "PF reset in progress"); in ice_dpll_is_reset()
55 * @pf: private board structure
63 * Context: Called under pf->dplls.lock
69 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_freq_set() argument
79 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
84 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
94 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
115 * Context: Acquires pf->dplls.lock
129 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set() local
132 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_frequency_set()
135 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
136 ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack); in ice_dpll_frequency_set()
137 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
153 * Context: Calls a function which acquires pf->dplls.lock
178 * Context: Calls a function which acquires pf->dplls.lock
204 * Context: Acquires pf->dplls.lock
217 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get() local
219 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
221 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
237 * Context: Calls a function which acquires pf->dplls.lock
262 * Context: Calls a function which acquires pf->dplls.lock
286 * Context: Called under pf->dplls.lock
335 * Context: Called under pf->dplls.lock
373 * @pf: private board struct
382 * Context: Called under pf->dplls.lock
388 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_state_update() argument
397 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL, in ice_dpll_pin_state_update()
404 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
405 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
408 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
409 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
413 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
415 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
419 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
421 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
426 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
434 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
435 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
438 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
439 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
443 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
445 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
450 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
454 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
478 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
481 dev_err_ratelimited(ice_pf_to_dev(pf), in ice_dpll_pin_state_update()
484 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
491 * @pf: board private structure
499 * Context: Called under pf->dplls.lock
505 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll, in ice_dpll_hw_input_prio_set() argument
511 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
517 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
534 * Context: Acquires pf->dplls.lock
545 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get() local
547 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
549 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
563 * Context: Acquires pf->dplls.lock
573 struct ice_pf *pf = d->pf; in ice_dpll_mode_get() local
575 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
577 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
594 * Context: Acquires pf->dplls.lock
607 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set() local
610 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_set()
613 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
615 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
618 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
620 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_set()
621 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
637 * Context: Calls a function which acquires pf->dplls.lock
670 * Context: Calls a function which acquires pf->dplls.lock
699 * Context: Acquires pf->dplls.lock
713 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get() local
716 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_get()
719 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
720 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_get()
728 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
744 * Context: Calls a function which acquires pf->dplls.lock
770 * Context: Calls a function which acquires pf->dplls.lock
796 * Context: Acquires pf->dplls.lock
808 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get() local
810 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
812 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
828 * Context: Acquires pf->dplls.lock
840 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set() local
843 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_prio_set()
846 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
847 ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack); in ice_dpll_input_prio_set()
848 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
914 * Context: Acquires pf->dplls.lock
926 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get() local
928 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
930 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
948 * Context: Acquires pf->dplls.lock
962 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set() local
966 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_phase_adjust_set()
969 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
977 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
986 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
994 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
999 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1017 * Context: Calls a function which acquires pf->dplls.lock
1045 * Context: Calls a function which acquires pf->dplls.lock
1076 * Context: Acquires pf->dplls.lock
1087 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get() local
1089 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1094 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1110 * Context: Acquires pf->dplls.lock
1124 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set() local
1128 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_set()
1131 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1132 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
1133 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
1143 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
1149 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
1152 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1168 * Context: Acquires pf->dplls.lock
1181 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get() local
1185 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_get()
1188 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1189 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
1190 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
1193 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, in ice_dpll_rclk_state_on_pin_get()
1201 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1242 * @pf: board private structure
1249 static u64 ice_generate_clock_id(struct ice_pf *pf) in ice_generate_clock_id() argument
1251 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
1286 * @pf: pf private structure
1292 * Context: Called by kworker under pf->dplls.lock
1298 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init) in ice_dpll_update_state() argument
1303 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
1307 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_update_state()
1312 dev_err(ice_pf_to_dev(pf), in ice_dpll_update_state()
1315 ice_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
1321 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
1322 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1323 return ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1330 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1335 ret = ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1339 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
1340 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1345 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1347 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1362 * Context: Holds pf->dplls.lock
1367 struct ice_pf *pf = container_of(d, struct ice_pf, dplls); in ice_dpll_periodic_work() local
1368 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
1369 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
1372 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
1374 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
1375 ret = ice_dpll_update_state(pf, de, false); in ice_dpll_periodic_work()
1377 ret = ice_dpll_update_state(pf, dp, false); in ice_dpll_periodic_work()
1383 dev_err(ice_pf_to_dev(pf), in ice_dpll_periodic_work()
1385 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1389 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1417 * @pf: board private structure
1431 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, in ice_dpll_get_pins() argument
1533 * @pf: board private structure
1550 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, in ice_dpll_init_direct_pins() argument
1557 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
1580 * @pf: board private structure
1584 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf) in ice_dpll_deinit_rclk_pin() argument
1586 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin()
1587 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_deinit_rclk_pin()
1592 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
1606 * @pf: board private structure
1612 * pin with the parents it has in the info. Register pin with the pf's main vsi
1620 ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_init_rclk_pins() argument
1623 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_init_rclk_pins()
1627 ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF, in ice_dpll_init_rclk_pins()
1628 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
1631 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
1632 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
1637 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1638 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1644 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
1650 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
1651 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1652 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1660 * @pf: board private structure
1661 * @cgu: if cgu is controlled by this pf
1666 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu) in ice_dpll_deinit_pins() argument
1668 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
1669 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
1670 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
1671 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
1672 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
1676 ice_dpll_deinit_rclk_pin(pf); in ice_dpll_deinit_pins()
1695 * @pf: board private structure
1698 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
1705 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) in ice_dpll_init_pins() argument
1710 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
1711 pf->dplls.num_inputs, in ice_dpll_init_pins()
1713 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
1717 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1718 pf->dplls.num_inputs, in ice_dpll_init_pins()
1719 pf->dplls.num_outputs, in ice_dpll_init_pins()
1721 pf->dplls.eec.dpll, in ice_dpll_init_pins()
1722 pf->dplls.pps.dpll); in ice_dpll_init_pins()
1726 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id; in ice_dpll_init_pins()
1727 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx, in ice_dpll_init_pins()
1734 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1735 pf->dplls.num_outputs, in ice_dpll_init_pins()
1736 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1737 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1739 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
1740 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1741 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1747 * @pf: board private structure
1755 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu) in ice_dpll_deinit_dpll() argument
1764 * @pf: board private structure
1777 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu, in ice_dpll_init_dpll() argument
1780 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
1786 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_dpll()
1790 d->pf = pf; in ice_dpll_init_dpll()
1792 ice_dpll_update_state(pf, d, true); in ice_dpll_init_dpll()
1805 * @pf: board private structure
1809 static void ice_dpll_deinit_worker(struct ice_pf *pf) in ice_dpll_deinit_worker() argument
1811 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
1819 * @pf: board private structure
1823 * Context: Shall be called after pf->dplls.lock is initialized.
1828 static int ice_dpll_init_worker(struct ice_pf *pf) in ice_dpll_init_worker() argument
1830 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
1835 dev_name(ice_pf_to_dev(pf))); in ice_dpll_init_worker()
1847 * @pf: board private structure
1850 * Init information for directly connected pins, cache them in pf's pins
1858 ice_dpll_init_info_direct_pins(struct ice_pf *pf, in ice_dpll_init_info_direct_pins() argument
1861 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
1863 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
1871 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
1872 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
1876 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
1877 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
1901 pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
1903 -pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
1906 pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
1908 -pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
1914 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_direct_pins()
1920 pins[i].pf = pf; in ice_dpll_init_info_direct_pins()
1928 * @pf: board private structure
1930 * Init information for rclk pin, cache them in pf->dplls.rclk.
1936 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf) in ice_dpll_init_info_rclk_pin() argument
1938 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
1942 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
1944 return ice_dpll_pin_state_update(pf, pin, in ice_dpll_init_info_rclk_pin()
1950 * @pf: board private structure
1960 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type) in ice_dpll_init_pins_info() argument
1965 return ice_dpll_init_info_direct_pins(pf, pin_type); in ice_dpll_init_pins_info()
1967 return ice_dpll_init_info_rclk_pin(pf); in ice_dpll_init_pins_info()
1975 * @pf: board private structure
1979 static void ice_dpll_deinit_info(struct ice_pf *pf) in ice_dpll_deinit_info() argument
1981 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
1982 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
1983 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
1984 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
1988 * ice_dpll_init_info - prepare pf's dpll information structure
1989 * @pf: board private structure
1992 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
1998 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu) in ice_dpll_init_info() argument
2001 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
2002 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
2003 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
2004 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
2007 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
2010 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
2037 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT); in ice_dpll_init_info()
2049 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT); in ice_dpll_init_info()
2054 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
2055 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
2058 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
2059 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
2060 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); in ice_dpll_init_info()
2066 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_init_info()
2073 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
2077 ice_dpll_deinit_info(pf); in ice_dpll_init_info()
2084 * @pf: board private structure
2090 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2092 void ice_dpll_deinit(struct ice_pf *pf) in ice_dpll_deinit() argument
2094 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_deinit()
2096 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
2098 ice_dpll_deinit_worker(pf); in ice_dpll_deinit()
2100 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_deinit()
2101 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
2102 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
2103 ice_dpll_deinit_info(pf); in ice_dpll_deinit()
2104 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
2109 * @pf: board private structure
2115 * Context: Initializes pf->dplls.lock mutex.
2117 void ice_dpll_init(struct ice_pf *pf) in ice_dpll_init() argument
2119 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_init()
2120 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
2124 err = ice_dpll_init_info(pf, cgu); in ice_dpll_init()
2127 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
2130 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
2133 err = ice_dpll_init_pins(pf, cgu); in ice_dpll_init()
2137 err = ice_dpll_init_worker(pf); in ice_dpll_init()
2141 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
2146 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_init()
2148 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
2150 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
2152 ice_dpll_deinit_info(pf); in ice_dpll_init()
2155 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); in ice_dpll_init()