Lines Matching +full:mmc +full:- +full:hs400 +full:- +full:enhanced +full:- +full:strobe
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
10 #include <linux/mmc/host.h>
16 #include "sdhci-cqhci.h"
17 #include "sdhci-pltfm.h"
41 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
52 if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) in enable_clock_gating()
64 /* Reset will clear this, so re-enable it */ in brcmstb_reset()
77 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register in brcmstb_sdhci_reset_cmd_data()
91 mmc_hostname(host->mmc), (int)mask); in brcmstb_sdhci_reset_cmd_data()
107 /* Reset will clear this, so re-enable it */ in brcmstb_reset_74165b0()
111 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) in sdhci_brcmstb_hs400es() argument
113 struct sdhci_host *host = mmc_priv(mmc); in sdhci_brcmstb_hs400es()
117 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", in sdhci_brcmstb_hs400es()
119 reg = readl(host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
120 if (ios->enhanced_strobe) in sdhci_brcmstb_hs400es()
124 writel(reg, host->ioaddr + SDHCI_VENDOR); in sdhci_brcmstb_hs400es()
131 host->mmc->actual_clock = 0; in sdhci_brcmstb_set_clock()
133 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_brcmstb_set_clock()
147 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", in sdhci_brcmstb_set_uhs_signaling()
167 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ in sdhci_brcmstb_set_uhs_signaling()
171 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) in sdhci_brcmstb_dumpregs() argument
173 sdhci_dumpregs(mmc_priv(mmc)); in sdhci_brcmstb_dumpregs()
176 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) in sdhci_brcmstb_cqe_enable() argument
178 struct sdhci_host *host = mmc_priv(mmc); in sdhci_brcmstb_cqe_enable()
187 sdhci_cqe_enable(mmc); in sdhci_brcmstb_cqe_enable()
241 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
242 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
243 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
244 { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },
256 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_brcmstb_cqhci_irq()
268 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) in sdhci_brcmstb_add_host()
271 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); in sdhci_brcmstb_add_host()
272 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_brcmstb_add_host()
277 cq_host = devm_kzalloc(mmc_dev(host->mmc), in sdhci_brcmstb_add_host()
280 ret = -ENOMEM; in sdhci_brcmstb_add_host()
284 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_brcmstb_add_host()
285 cq_host->ops = &sdhci_brcmstb_cqhci_ops; in sdhci_brcmstb_add_host()
287 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_brcmstb_add_host()
289 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); in sdhci_brcmstb_add_host()
290 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_brcmstb_add_host()
293 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_brcmstb_add_host()
321 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); in sdhci_brcmstb_probe()
322 match_priv = match->data; in sdhci_brcmstb_probe()
324 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); in sdhci_brcmstb_probe()
326 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in sdhci_brcmstb_probe()
328 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_brcmstb_probe()
332 brcmstb_pdata.ops = match_priv->ops; in sdhci_brcmstb_probe()
340 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { in sdhci_brcmstb_probe()
341 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; in sdhci_brcmstb_probe()
342 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; in sdhci_brcmstb_probe()
345 /* Map in the non-standard CFG registers */ in sdhci_brcmstb_probe()
346 priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); in sdhci_brcmstb_probe()
347 if (IS_ERR(priv->cfg_regs)) { in sdhci_brcmstb_probe()
348 res = PTR_ERR(priv->cfg_regs); in sdhci_brcmstb_probe()
353 res = mmc_of_parse(host->mmc); in sdhci_brcmstb_probe()
359 * voltage switch so only enable it for non-removable devices. in sdhci_brcmstb_probe()
361 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && in sdhci_brcmstb_probe()
362 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) in sdhci_brcmstb_probe()
363 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; in sdhci_brcmstb_probe()
366 * If the chip has enhanced strobe and it's enabled, add in sdhci_brcmstb_probe()
369 if (match_priv->hs400es && in sdhci_brcmstb_probe()
370 (host->mmc->caps2 & MMC_CAP2_HS400_ES)) in sdhci_brcmstb_probe()
371 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; in sdhci_brcmstb_probe()
379 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) in sdhci_brcmstb_probe()
380 host->caps &= ~SDHCI_CAN_64BIT; in sdhci_brcmstb_probe()
381 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | in sdhci_brcmstb_probe()
384 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) in sdhci_brcmstb_probe()
385 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; in sdhci_brcmstb_probe()
388 if (device_property_read_u32(&pdev->dev, "clock-frequency", in sdhci_brcmstb_probe()
389 &priv->base_freq_hz) != 0) in sdhci_brcmstb_probe()
392 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); in sdhci_brcmstb_probe()
394 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); in sdhci_brcmstb_probe()
403 clk_set_rate(base_clk, priv->base_freq_hz); in sdhci_brcmstb_probe()
406 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; in sdhci_brcmstb_probe()
407 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); in sdhci_brcmstb_probe()
409 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_brcmstb_probe()
411 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", in sdhci_brcmstb_probe()
413 priv->base_clk = base_clk; in sdhci_brcmstb_probe()
420 pltfm_host->clk = clk; in sdhci_brcmstb_probe()
431 sdhci_pltfm_suspend(&pdev->dev); in sdhci_brcmstb_shutdown()
443 clk_disable_unprepare(priv->base_clk); in sdhci_brcmstb_suspend()
455 if (!ret && priv->base_freq_hz) { in sdhci_brcmstb_resume()
456 ret = clk_prepare_enable(priv->base_clk); in sdhci_brcmstb_resume()
464 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) in sdhci_brcmstb_resume()
465 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); in sdhci_brcmstb_resume()
478 .name = "sdhci-brcmstb",