Lines Matching +full:0 +full:xfee00000
53 #define MSI_RANGE_START (0xfee00000)
54 #define MSI_RANGE_END (0xfeefffff)
55 #define HT_RANGE_START (0xfd00000000ULL)
56 #define HT_RANGE_END (0xffffffffffULL)
104 p->uid[0] ? p->uid : NULL)) { in get_acpihid_device_id()
178 if (devid < 0) in rlookup_amd_iommu()
230 return 0; in clone_alias()
234 return 0; in clone_alias()
242 return 0; in clone_alias()
280 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1); in setup_aliases()
312 if (devid < 0) in acpihid_device_group()
336 u32 flags = 0; in pdev_get_caps()
345 if (features >= 0) { in pdev_get_caps()
364 return 0; in pdev_enable_cap_ats()
384 dev_data->ats_enabled = 0; in pdev_disable_cap_ats()
394 return 0; in amd_iommu_pdev_enable_cap_pri()
405 ret = 0; in amd_iommu_pdev_enable_cap_pri()
418 dev_data->pri_enabled = 0; in amd_iommu_pdev_disable_cap_pri()
428 return 0; in pdev_enable_cap_pasid()
432 ret = pci_enable_pasid(pdev, 0); in pdev_enable_cap_pasid()
446 dev_data->pasid_enabled = 0; in pdev_disable_cap_pasid()
479 if (sbdf < 0) in check_device()
501 return 0; in iommu_init_device()
504 if (sbdf < 0) in iommu_init_device()
528 return 0; in iommu_init_device()
538 if (sbdf < 0) in iommu_ignore_device()
543 memset(&dev_table[devid], 0, sizeof(struct dev_table_entry)); in iommu_ignore_device()
576 for (i = 0; i < 4; ++i) in dump_dte_entry()
585 for (i = 0; i < 4; ++i) in dump_command()
596 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; in amd_iommu_report_rmp_hw_error()
597 vmg_tag = (event[1]) & 0xFFFF; in amd_iommu_report_rmp_hw_error()
599 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8); in amd_iommu_report_rmp_hw_error()
602 devid & 0xff); in amd_iommu_report_rmp_hw_error()
608 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n", in amd_iommu_report_rmp_hw_error()
612 …("Event logged [RMP_HW_ERROR device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n… in amd_iommu_report_rmp_hw_error()
628 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; in amd_iommu_report_rmp_fault()
629 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF; in amd_iommu_report_rmp_fault()
630 vmg_tag = (event[1]) & 0xFFFF; in amd_iommu_report_rmp_fault()
635 devid & 0xff); in amd_iommu_report_rmp_fault()
641 …pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x… in amd_iommu_report_rmp_fault()
645 …ged [RMP_PAGE_FAULT device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=… in amd_iommu_report_rmp_fault()
655 (((flags) & EVENT_FLAG_I) == 0)
668 devid & 0xff); in amd_iommu_report_page_fault()
682 pr_err_ratelimited(" device=%04x:%02x:%02x.%x domain=0x%04x\n", in amd_iommu_report_page_fault()
697 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", in amd_iommu_report_page_fault()
701 …("Event logged [IO_PAGE_FAULT device=%04x:%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\… in amd_iommu_report_page_fault()
716 int count = 0; in iommu_print_event()
722 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; in iommu_print_event()
723 pasid = (event[0] & EVENT_DOMID_MASK_HI) | in iommu_print_event()
728 if (type == 0) { in iommu_print_event()
745 …ogged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\… in iommu_print_event()
752 "address=0x%llx flags=0x%04x]\n", in iommu_print_event()
757 …ogged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\… in iommu_print_event()
762 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); in iommu_print_event()
766 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", in iommu_print_event()
770 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%04x:%02x:%02x.%x address=0x%llx]\n", in iommu_print_event()
775 …logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\… in iommu_print_event()
787 tag = event[1] & 0x03FF; in iommu_print_event()
788 …ged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%… in iommu_print_event()
793 …dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08… in iommu_print_event()
794 event[0], event[1], event[2], event[3]); in iommu_print_event()
804 memset(__evt, 0, 4 * sizeof(u32)); in iommu_print_event()
844 for (i = 0; i < LOOP_TIMEOUT; ++i) { in iommu_poll_ppr_log()
845 if (PPR_REQ_TYPE(raw[0]) != 0) in iommu_poll_ppr_log()
851 entry[0] = raw[0]; in iommu_poll_ppr_log()
861 raw[0] = raw[1] = 0UL; in iommu_poll_ppr_log()
882 return 0; in amd_iommu_register_ga_log_notifier()
919 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) in iommu_poll_ga_log()
1033 int i = 0; in wait_on_sem()
1045 return 0; in wait_on_sem()
1072 memset(cmd, 0, sizeof(*cmd)); in build_completion_wait()
1073 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; in build_completion_wait()
1082 memset(cmd, 0, sizeof(*cmd)); in build_inv_dte()
1083 cmd->data[0] = devid; in build_inv_dte()
1122 /* Clear bits 11:0 */ in build_inv_address()
1135 memset(cmd, 0, sizeof(*cmd)); in build_inv_iommu_pages()
1143 cmd->data[0] |= pasid; in build_inv_iommu_pages()
1155 memset(cmd, 0, sizeof(*cmd)); in build_inv_iotlb_pages()
1157 cmd->data[0] = devid; in build_inv_iotlb_pages()
1158 cmd->data[0] |= (qdep & 0xff) << 24; in build_inv_iotlb_pages()
1163 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; in build_inv_iotlb_pages()
1164 cmd->data[1] |= (pasid & 0xff) << 16; in build_inv_iotlb_pages()
1174 memset(cmd, 0, sizeof(*cmd)); in build_complete_ppr()
1176 cmd->data[0] = devid; in build_complete_ppr()
1181 cmd->data[3] = tag & 0x1ff; in build_complete_ppr()
1189 memset(cmd, 0, sizeof(*cmd)); in build_inv_all()
1195 memset(cmd, 0, sizeof(*cmd)); in build_inv_irt()
1196 cmd->data[0] = devid; in build_inv_irt()
1208 unsigned int count = 0; in __iommu_queue_command_sync()
1215 if (left <= 0x20) { in __iommu_queue_command_sync()
1238 return 0; in __iommu_queue_command_sync()
1272 return 0; in iommu_completion_wait()
1305 for (devid = 0; devid <= last_bdf; ++devid) in amd_iommu_flush_dte_all()
1320 for (dom_id = 0; dom_id <= last_bdf; ++dom_id) { in amd_iommu_flush_tlb_all()
1322 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, in amd_iommu_flush_tlb_all()
1334 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, in amd_iommu_flush_tlb_domid()
1368 for (devid = 0; devid <= last_bdf; devid++) in amd_iommu_flush_irt_all()
1449 ret = device_flush_iotlb(dev_data, 0, ~0UL, in device_flush_dte()
1466 int ret = 0, i; in __domain_flush_pages()
1475 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { in __domain_flush_pages()
1519 while (size != 0) { in amd_iommu_domain_flush_pages()
1531 if (likely((unsigned long)address != 0)) in amd_iommu_domain_flush_pages()
1550 amd_iommu_domain_flush_pages(domain, 0, in amd_iommu_domain_flush_all()
1558 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { in amd_iommu_domain_flush_complete()
1611 BUG_ON(id == 0); in domain_id_alloc()
1612 if (id > 0 && id < MAX_DOMAIN_ID) in domain_id_alloc()
1615 id = 0; in domain_id_alloc()
1624 if (id > 0 && id < MAX_DOMAIN_ID) in domain_id_free()
1634 for (i = 0; i < 512; ++i) { in free_gcr3_tbl_level1()
1649 for (i = 0; i < 512; ++i) { in free_gcr3_tbl_level2()
1666 BUG_ON(domain->glx != 0); in free_gcr3_table()
1704 return 0; in setup_gcr3_table()
1710 u64 pte_root = 0; in set_dte_entry()
1711 u64 flags = 0; in set_dte_entry()
1727 if (!amd_iommu_snp_en || (domain->id != 0)) in set_dte_entry()
1750 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; in set_dte_entry()
1753 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; in set_dte_entry()
1780 dev_table[devid].data[0] = pte_root; in set_dte_entry()
1797 dev_table[devid].data[0] = DTE_FLAG_V; in clear_dte_entry()
1800 dev_table[devid].data[0] |= DTE_FLAG_TV; in clear_dte_entry()
1873 int ret = 0; in attach_device()
1975 iommu_setup_dma_ops(dev, 0, U64_MAX); in amd_iommu_probe_finalize()
2062 WARN_ON(domain->dev_cnt != 0); in cleanup_domain()
2099 return 0; in protection_domain_init_v1()
2111 return 0; in protection_domain_init_v2()
2179 return ~0ULL; in dma_max_address()
2204 * Since DTE[Mode]=0 is prohibited on SNP-enabled system, in do_iommu_domain_alloc()
2217 domain->domain.geometry.aperture_start = 0; in do_iommu_domain_alloc()
2237 domain = do_iommu_domain_alloc(type, NULL, 0); in amd_iommu_domain_alloc()
2290 return 0; in amd_iommu_attach_device()
2311 dev_data->use_vapic = 0; in amd_iommu_attach_device()
2328 return 0; in amd_iommu_iotlb_sync_map()
2337 int prot = 0; in amd_iommu_map_pages()
2388 return 0; in amd_iommu_unmap_pages()
2390 r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0; in amd_iommu_unmap_pages()
2446 return 0; in amd_iommu_set_dirty_tracking()
2455 pte_root = dev_table[dev_data->devid].data[0]; in amd_iommu_set_dirty_tracking()
2461 dev_table[dev_data->devid].data[0] = pte_root; in amd_iommu_set_dirty_tracking()
2473 return 0; in amd_iommu_set_dirty_tracking()
2508 if (sbdf < 0) in amd_iommu_get_resv_regions()
2518 int type, prot = 0; in amd_iommu_get_resv_regions()
2546 0, IOMMU_RESV_MSI, GFP_KERNEL); in amd_iommu_get_resv_regions()
2553 0, IOMMU_RESV_RESERVED, GFP_KERNEL); in amd_iommu_get_resv_regions()
2594 return 0; in amd_iommu_def_domain_type()
2601 * - SNP is enabled, because it prohibits DTE[Mode]=0. in amd_iommu_def_domain_type()
2609 return 0; in amd_iommu_def_domain_type()
2664 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { in __flush_pasid()
2665 if (domain->dev_iommu[i] == 0) in __flush_pasid()
2669 if (ret != 0) in __flush_pasid()
2696 if (ret != 0) in __flush_pasid()
2703 ret = 0; in __flush_pasid()
2732 return __flush_pasid(domain, pasid, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS); in __amd_iommu_flush_tlb()
2755 index = (pasid >> (9 * level)) & 0x1ff; in __get_gcr3_pte()
2758 if (level == 0) in __get_gcr3_pte()
2806 return 0; in __clear_gcr3()
2808 *pte = 0; in __clear_gcr3()
2945 memset(table->table, 0, in __alloc_irq_table()
2948 memset(table->table, 0, in __alloc_irq_table()
2978 return 0; in set_remap_table_entry_alias()
3064 for (index = ALIGN(table->min_index, alignment), c = 0; in alloc_irq_index()
3069 c = 0; in alloc_irq_index()
3075 for (; c != 0; --c) in alloc_irq_index()
3121 return 0; in __modify_irte_ga()
3135 return 0; in modify_irte_ga()
3154 return 0; in modify_irte()
3179 irte->val = 0; in irte_prepare()
3193 irte->lo.val = 0; in irte_ga_prepare()
3194 irte->hi.val = 0; in irte_ga_prepare()
3223 irte->fields.valid = 0; in irte_deactivate()
3231 irte->lo.fields_remap.valid = 0; in irte_ga_deactivate()
3271 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3272 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3273 irte->hi.fields.vector = 0xff; in irte_ga_set_allocated()
3281 return irte->val != 0; in irte_is_allocated()
3289 return irte->hi.fields.vector != 0; in irte_ga_is_allocated()
3294 table->table[index] = 0; in irte_clear_allocated()
3302 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3303 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3333 msg->address_lo = 0; in fill_msi_msg()
3406 if (sbdf < 0) in irq_remapping_alloc()
3416 if (ret < 0) in irq_remapping_alloc()
3430 for (i = 0; i < 32; ++i) in irq_remapping_alloc()
3448 if (index < 0) { in irq_remapping_alloc()
3454 for (i = 0; i < nr_irqs; i++) { in irq_remapping_alloc()
3485 return 0; in irq_remapping_alloc()
3488 for (i--; i >= 0; i--) { in irq_remapping_alloc()
3493 for (i = 0; i < nr_irqs; i++) in irq_remapping_alloc()
3508 for (i = 0; i < nr_irqs; i++) { in irq_remapping_free()
3535 return 0; in irq_remapping_activate()
3540 return 0; in irq_remapping_activate()
3562 return 0; in irq_remapping_select()
3565 devid = get_ioapic_devid(fwspec->param[0]); in irq_remapping_select()
3567 devid = get_hpet_devid(fwspec->param[0]); in irq_remapping_select()
3569 if (devid < 0) in irq_remapping_select()
3570 return 0; in irq_remapping_select()
3571 iommu = __rlookup_amd_iommu((devid >> 16), (devid & 0xffff)); in irq_remapping_select()
3591 return 0; in amd_iommu_activate_guest_mode()
3595 entry->lo.val = 0; in amd_iommu_activate_guest_mode()
3596 entry->hi.val = 0; in amd_iommu_activate_guest_mode()
3619 return 0; in amd_iommu_deactivate_guest_mode()
3623 entry->lo.val = 0; in amd_iommu_deactivate_guest_mode()
3624 entry->hi.val = 0; in amd_iommu_deactivate_guest_mode()
3659 return 0; in amd_ir_set_vcpu_affinity()
3690 ir_data->cached_ga_tag = 0; in amd_ir_set_vcpu_affinity()
3726 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) in amd_ir_set_affinity()
3777 iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0, in amd_iommu_create_irq_domain()
3793 return 0; in amd_iommu_create_irq_domain()
3803 return 0; in amd_iommu_update_ga()
3808 if (cpu >= 0) { in amd_iommu_update_ga()