Lines Matching +full:1 +full:c12
120 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); in armv6_pmcr_read()
127 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); in armv6_pmcr_write()
130 #define ARMV6_PMCR_ENABLE (1 << 0)
131 #define ARMV6_PMCR_CTR01_RESET (1 << 1)
132 #define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
133 #define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
134 #define ARMV6_PMCR_COUNT0_IEN (1 << 4)
135 #define ARMV6_PMCR_COUNT1_IEN (1 << 5)
136 #define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
137 #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
138 #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
139 #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
168 WARN_ONCE(1, "invalid counter number (%d)\n", counter); in armv6_pmcr_counter_has_overflowed()
180 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); in armv6pmu_read_counter()
182 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); in armv6pmu_read_counter()
184 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); in armv6pmu_read_counter()
186 WARN_ONCE(1, "invalid counter number (%d)\n", counter); in armv6pmu_read_counter()
197 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); in armv6pmu_write_counter()
199 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); in armv6pmu_write_counter()
201 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); in armv6pmu_write_counter()
203 WARN_ONCE(1, "invalid counter number (%d)\n", counter); in armv6pmu_write_counter()
224 WARN_ONCE(1, "invalid counter number (%d)\n", idx); in armv6pmu_enable_event()
363 WARN_ONCE(1, "invalid counter number (%d)\n", idx); in armv6pmu_disable_event()