Lines Matching +full:sub +full:- +full:processor
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
22 #include <sound/soc-dapm.h>
51 pll->id = id; in pll_init()
52 mutex_init(&pll->lock); in pll_init()
67 aif->id = id; in aif_init()
86 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
91 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
92 mutex_init(&ram->lock); in coeff_ram_init()
104 status->streams |= mask; in set_aif_status_active()
112 status->streams &= mask; in set_aif_status_inactive()
117 return status->streams; in aifs_active()
122 return (0x03 << aif_id * 2) & status->streams; in aif_active()
283 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); in tscs454_data_init()
284 if (IS_ERR(tscs454->regmap)) { in tscs454_data_init()
285 ret = PTR_ERR(tscs454->regmap); in tscs454_data_init()
290 aif_init(&tscs454->aifs[i], i); in tscs454_data_init()
292 mutex_init(&tscs454->aifs_status_lock); in tscs454_data_init()
293 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
294 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
296 coeff_ram_init(&tscs454->dac_ram); in tscs454_data_init()
297 coeff_ram_init(&tscs454->spk_ram); in tscs454_data_init()
298 coeff_ram_init(&tscs454->sub_ram); in tscs454_data_init()
315 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_get()
316 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_get()
320 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_get()
321 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_get()
322 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_get()
323 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_get()
324 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_get()
325 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_get()
326 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_get()
327 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_get()
328 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_get()
330 return -EINVAL; in coeff_ram_get()
335 memcpy(ucontrol->value.bytes.data, in coeff_ram_get()
336 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); in coeff_ram_get()
363 ret = -EIO; in write_coeff_ram()
364 dev_err(component->dev, in write_coeff_ram()
369 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); in write_coeff_ram()
371 dev_err(component->dev, in write_coeff_ram()
376 ret = regmap_bulk_write(tscs454->regmap, r_wr, in write_coeff_ram()
380 dev_err(component->dev, in write_coeff_ram()
396 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_put()
397 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_put()
398 unsigned int coeff_cnt = params->max / COEFF_SIZE; in coeff_ram_put()
408 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_put()
409 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_put()
410 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_put()
411 coeff_ram_synced = &tscs454->dac_ram.synced; in coeff_ram_put()
415 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_put()
416 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_put()
417 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_put()
418 coeff_ram_synced = &tscs454->spk_ram.synced; in coeff_ram_put()
422 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_put()
423 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_put()
424 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_put()
425 coeff_ram_synced = &tscs454->sub_ram.synced; in coeff_ram_put()
430 return -EINVAL; in coeff_ram_put()
437 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], in coeff_ram_put()
438 ucontrol->value.bytes.data, params->max); in coeff_ram_put()
440 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
441 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
447 ctl->addr, coeff_cnt); in coeff_ram_put()
449 dev_err(component->dev, in coeff_ram_put()
458 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
459 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
470 mutex_lock(&tscs454->dac_ram.lock); in coeff_ram_sync()
471 if (!tscs454->dac_ram.synced) { in coeff_ram_sync()
472 ret = write_coeff_ram(component, tscs454->dac_ram.cache, in coeff_ram_sync()
476 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
480 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
482 mutex_lock(&tscs454->spk_ram.lock); in coeff_ram_sync()
483 if (!tscs454->spk_ram.synced) { in coeff_ram_sync()
484 ret = write_coeff_ram(component, tscs454->spk_ram.cache, in coeff_ram_sync()
488 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
492 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
494 mutex_lock(&tscs454->sub_ram.lock); in coeff_ram_sync()
495 if (!tscs454->sub_ram.synced) { in coeff_ram_sync()
496 ret = write_coeff_ram(component, tscs454->sub_ram.cache, in coeff_ram_sync()
500 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
504 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
634 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in set_sysclk()
635 freq = clk_get_rate(tscs454->sysclk); in set_sysclk()
637 freq = tscs454->bclk_freq; in set_sysclk()
640 ret = -EINVAL; in set_sysclk()
641 dev_err(component->dev, in set_sysclk()
648 pll_ctl->settings[i].addr, in set_sysclk()
649 pll_ctl->settings[i].val); in set_sysclk()
651 dev_err(component->dev, in set_sysclk()
663 mutex_lock(&pll->lock); in reserve_pll()
664 pll->users++; in reserve_pll()
665 mutex_unlock(&pll->lock); in reserve_pll()
670 mutex_lock(&pll->lock); in free_pll()
671 pll->users--; in free_pll()
672 mutex_unlock(&pll->lock); in free_pll()
679 snd_soc_dapm_to_component(source->dapm); in pll_connected()
683 if (strstr(source->name, "PLL 1")) { in pll_connected()
684 mutex_lock(&tscs454->pll1.lock); in pll_connected()
685 users = tscs454->pll1.users; in pll_connected()
686 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
687 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, in pll_connected()
690 mutex_lock(&tscs454->pll2.lock); in pll_connected()
691 users = tscs454->pll2.users; in pll_connected()
692 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
693 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, in pll_connected()
708 snd_soc_dapm_to_component(w->dapm); in pll_power_event()
716 if (strstr(w->name, "PLL 1")) in pll_power_event()
740 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", in pll_power_event()
749 dev_err(component->dev, in pll_power_event()
777 ret = -ENODEV; in aif_set_provider()
778 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); in aif_set_provider()
786 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", in aif_set_provider()
799 ret = aif_set_provider(component, aif->id, aif->provider); in aif_prepare()
811 mutex_lock(&tscs454->aifs_status_lock); in aif_free()
813 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); in aif_free()
815 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); in aif_free()
817 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", in aif_free()
818 aif->id, tscs454->aifs_status.streams); in aif_free()
820 if (!aif_active(&tscs454->aifs_status, aif->id)) { in aif_free()
822 aif_set_provider(component, aif->id, false); in aif_free()
823 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", in aif_free()
824 aif->pll->id, aif->id); in aif_free()
825 free_pll(aif->pll); in aif_free()
828 if (!aifs_active(&tscs454->aifs_status)) { in aif_free()
829 dev_dbg(component->dev, "Freeing pll %d from ir\n", in aif_free()
830 tscs454->internal_rate.pll->id); in aif_free()
831 free_pll(tscs454->internal_rate.pll); in aif_free()
834 mutex_unlock(&tscs454->aifs_status_lock); in aif_free()
907 "DMic 2", "ClassD", "DAC", "Sub"};
957 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
1029 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1051 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1105 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1111 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1117 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1135 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1136 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1139 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1142 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1191 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1195 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1199 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1205 "Pre Scale + EQ Band 0 - 1",
1206 "Pre Scale + EQ Band 0 - 2",
1207 "Pre Scale + EQ Band 0 - 3",
1208 "Pre Scale + EQ Band 0 - 4",
1209 "Pre Scale + EQ Band 0 - 5",
1255 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1258 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1483 (struct coeff_ram_ctl *)kcontrol->private_value; in bytes_info_ext()
1484 struct soc_bytes_ext *params = &ctl->bytes_ext; in bytes_info_ext()
1486 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in bytes_info_ext()
1487 ucontrol->count = params->max; in bytes_info_ext()
1587 SOC_ENUM("Input Processor Channel 0/1 Operation",
1600 SOC_ENUM("Input Processor Channel 2/3 Operation",
1711 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1716 SOC_SINGLE("Speaker De-Emphasis Switch",
1719 SOC_ENUM("Sub Polarity", sub_pol_enum),
1720 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1721 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1723 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1746 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1771 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1788 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1805 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1830 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1900 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1917 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1934 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1959 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
2011 SOC_SINGLE("Sub EQ 2 Switch",
2013 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2014 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2015 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2017 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2018 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2019 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2021 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2022 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2023 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2024 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2025 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2026 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2028 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2029 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2033 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2037 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2040 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2043 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2045 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2046 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2050 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2054 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2057 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2060 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2062 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2063 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2067 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2071 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2074 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2077 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2079 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2080 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2081 SOC_SINGLE("Sub CLE Expander Switch",
2083 SOC_SINGLE("Sub CLE Limiter Switch",
2085 SOC_SINGLE("Sub CLE Compressor Switch",
2088 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2092 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2096 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2099 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2102 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2104 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2108 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2113 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2116 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2118 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2122 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2125 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2128 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2130 SOC_SINGLE("Sub Treble Enhancement Switch",
2132 SOC_SINGLE("Sub Treble NLF Switch",
2134 SOC_SINGLE("Sub Bass Enhancement Switch",
2136 SOC_SINGLE("Sub Bass NLF Switch",
2280 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2281 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2282 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2283 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2284 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2285 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2287 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2288 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2289 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2290 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2291 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2292 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2294 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2295 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2297 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2298 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2299 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2300 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2301 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2302 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2304 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2305 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2306 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2307 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2308 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2309 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2311 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2312 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2314 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2315 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2317 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2318 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2320 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2322 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2324 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2326 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2327 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2329 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2330 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2332 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2334 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2336 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2338 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2340 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2342 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2343 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2345 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2346 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2348 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2349 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2368 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2370 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2372 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2374 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2381 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2413 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2429 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2441 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2448 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2458 SND_SOC_DAPM_OUTPUT("Sub Out"),
2545 /* Sub Path */
2546 {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2547 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2548 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2549 {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2550 {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2551 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2552 {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2553 {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2554 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2555 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2556 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2557 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2558 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2559 {"Sub Mux", "DMic 2 Left", "DMic 2"},
2560 {"Sub Mux", "DMic 2 Right", "DMic 2"},
2561 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2562 {"Sub Mux", "ClassD Left", "ClassD Left"},
2563 {"Sub Mux", "ClassD Right", "ClassD Right"},
2564 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2565 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2566 {"Sub", NULL, "Sub Mux"},
2567 {"Sub", NULL, "PLLs"},
2568 {"Sub Out", NULL, "Sub Power"},
2569 {"Sub Out", NULL, "Sub"},
2593 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2594 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2596 {"Input Processor Channel 0", NULL, "PLLs"},
2597 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2599 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2600 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2602 {"Input Processor Channel 1", NULL, "PLLs"},
2603 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2605 {"Input Processor Channel 2", NULL, "PLLs"},
2606 {"Input Processor Channel 2", NULL, "DMic 2"},
2608 {"Input Processor Channel 3", NULL, "PLLs"},
2609 {"Input Processor Channel 3", NULL, "DMic 2"},
2611 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2612 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2613 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2614 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2616 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2617 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2618 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2619 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2621 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2622 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2623 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2624 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2635 struct snd_soc_component *component = dai->component; in tscs454_set_sysclk()
2640 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); in tscs454_set_sysclk()
2645 if (bclk_dai != dai->id) in tscs454_set_sysclk()
2648 tscs454->bclk_freq = freq; in tscs454_set_sysclk()
2657 struct snd_soc_component *component = dai->component; in tscs454_set_bclk_ratio()
2661 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", in tscs454_set_bclk_ratio()
2662 dai->id, ratio); in tscs454_set_bclk_ratio()
2664 switch (dai->id) { in tscs454_set_bclk_ratio()
2678 ret = -EINVAL; in tscs454_set_bclk_ratio()
2679 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); in tscs454_set_bclk_ratio()
2694 ret = -EINVAL; in tscs454_set_bclk_ratio()
2695 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); in tscs454_set_bclk_ratio()
2702 dev_err(component->dev, in tscs454_set_bclk_ratio()
2717 aif->provider = true; in set_aif_provider_from_fmt()
2720 aif->provider = false; in set_aif_provider_from_fmt()
2723 ret = -EINVAL; in set_aif_provider_from_fmt()
2724 dev_err(component->dev, "Unsupported format (%d)\n", ret); in set_aif_provider_from_fmt()
2748 ret = -EINVAL; in set_aif_tdm_delay()
2749 dev_err(component->dev, in set_aif_tdm_delay()
2756 dev_err(component->dev, "Failed to setup tdm format (%d)\n", in set_aif_tdm_delay()
2782 ret = -EINVAL; in set_aif_format_from_fmt()
2783 dev_err(component->dev, in set_aif_format_from_fmt()
2811 ret = -EINVAL; in set_aif_format_from_fmt()
2812 dev_err(component->dev, "Format unsupported (%d)\n", ret); in set_aif_format_from_fmt()
2819 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", in set_aif_format_from_fmt()
2846 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2847 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2866 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2867 dev_err(component->dev, "Format unknown (%d)\n", ret); in set_aif_clock_format_from_fmt()
2874 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2885 struct snd_soc_component *component = dai->component; in tscs454_set_dai_fmt()
2887 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_set_dai_fmt()
2894 ret = set_aif_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2898 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2909 struct snd_soc_component *component = dai->component; in tscs454_dai1_set_tdm_slot()
2917 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2918 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2933 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2934 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2949 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2950 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2955 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2966 struct snd_soc_component *component = dai->component; in tscs454_dai23_set_tdm_slot()
2975 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2976 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
2980 switch (dai->id) { in tscs454_dai23_set_tdm_slot()
2988 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2989 dev_err(component->dev, "Unrecognized interface %d (%d)\n", in tscs454_dai23_set_tdm_slot()
2990 dai->id, ret); in tscs454_dai23_set_tdm_slot()
3002 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3003 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3018 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3019 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3024 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3082 ret = -EINVAL; in set_aif_fs()
3083 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); in set_aif_fs()
3098 ret = -EINVAL; in set_aif_fs()
3099 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); in set_aif_fs()
3106 dev_err(component->dev, in set_aif_fs()
3136 ret = -EINVAL; in set_aif_sample_format()
3137 dev_err(component->dev, "Unsupported format width (%d)\n", ret); in set_aif_sample_format()
3152 ret = -EINVAL; in set_aif_sample_format()
3153 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); in set_aif_sample_format()
3160 dev_err(component->dev, in set_aif_sample_format()
3172 struct snd_soc_component *component = dai->component; in tscs454_hw_params()
3175 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_params()
3179 mutex_lock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3181 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, in tscs454_hw_params()
3182 aif->id, fs); in tscs454_hw_params()
3184 if (!aif_active(&tscs454->aifs_status, aif->id)) { in tscs454_hw_params()
3186 aif->pll = &tscs454->pll1; in tscs454_hw_params()
3188 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3190 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", in tscs454_hw_params()
3191 aif->pll->id, aif->id); in tscs454_hw_params()
3193 reserve_pll(aif->pll); in tscs454_hw_params()
3196 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ in tscs454_hw_params()
3199 tscs454->internal_rate.pll = &tscs454->pll1; in tscs454_hw_params()
3201 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
3203 dev_dbg(component->dev, "Reserving pll %d for ir\n", in tscs454_hw_params()
3204 tscs454->internal_rate.pll->id); in tscs454_hw_params()
3206 reserve_pll(tscs454->internal_rate.pll); in tscs454_hw_params()
3209 ret = set_aif_fs(component, aif->id, fs); in tscs454_hw_params()
3211 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); in tscs454_hw_params()
3215 ret = set_aif_sample_format(component, params_format(params), aif->id); in tscs454_hw_params()
3217 dev_err(component->dev, in tscs454_hw_params()
3222 set_aif_status_active(&tscs454->aifs_status, aif->id, in tscs454_hw_params()
3223 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_params()
3225 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", in tscs454_hw_params()
3226 aif->id, tscs454->aifs_status.streams); in tscs454_hw_params()
3230 mutex_unlock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3238 struct snd_soc_component *component = dai->component; in tscs454_hw_free()
3240 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_free()
3243 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_free()
3250 struct snd_soc_component *component = dai->component; in tscs454_prepare()
3252 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_prepare()
3287 switch (tscs454->sysclk_src_id) { in tscs454_probe()
3301 ret = -EINVAL; in tscs454_probe()
3302 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); in tscs454_probe()
3309 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); in tscs454_probe()
3313 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in tscs454_probe()
3338 .name = "tscs454-dai1",
3358 .name = "tscs454-dai2",
3378 .name = "tscs454-dai3",
3408 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); in tscs454_i2c_probe()
3410 return -ENOMEM; in tscs454_i2c_probe()
3419 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); in tscs454_i2c_probe()
3420 if (!IS_ERR(tscs454->sysclk)) { in tscs454_i2c_probe()
3422 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { in tscs454_i2c_probe()
3423 ret = PTR_ERR(tscs454->sysclk); in tscs454_i2c_probe()
3424 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); in tscs454_i2c_probe()
3428 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); in tscs454_i2c_probe()
3429 tscs454->sysclk_src_id = src; in tscs454_i2c_probe()
3431 ret = regmap_write(tscs454->regmap, in tscs454_i2c_probe()
3434 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); in tscs454_i2c_probe()
3437 regcache_mark_dirty(tscs454->regmap); in tscs454_i2c_probe()
3439 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, in tscs454_i2c_probe()
3442 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); in tscs454_i2c_probe()
3446 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); in tscs454_i2c_probe()
3448 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, in tscs454_i2c_probe()
3451 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); in tscs454_i2c_probe()