Lines Matching +full:micbias1 +full:- +full:ext +full:- +full:cap
1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
107 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in playback_gpio_reset()
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_set()
143 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, in capture_gpio_set()
145 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, in capture_gpio_set()
157 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_reset()
159 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, in capture_gpio_reset()
161 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in capture_gpio_reset()
167 switch (priv->mtkaif_protocol) { in mt6358_mtkaif_tx_enable()
170 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
174 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
177 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
183 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
187 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
194 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
198 regmap_update_bits(priv->regmap, in mt6358_mtkaif_tx_enable()
209 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, in mt6358_mtkaif_tx_disable()
229 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
239 stage = up ? i : target - i; in hp_main_output_ramp()
240 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in hp_main_output_ramp()
242 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in hp_main_output_ramp()
254 stage = up ? i : 0xf - i; in hp_aux_feedback_loop_gain_ramp()
255 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in hp_aux_feedback_loop_gain_ramp()
267 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in hp_pull_down()
272 for (i = 0x6; i >= 0x1; i--) { in hp_pull_down()
273 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in hp_pull_down()
291 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", in headset_volume_ramp()
294 dev_info(priv->dev, "%s(), from %d, to %d\n", in headset_volume_ramp()
298 offset = to - from; in headset_volume_ramp()
300 offset = from - to; in headset_volume_ramp()
306 reg_idx = from - count; in headset_volume_ramp()
309 regmap_update_bits(priv->regmap, in headset_volume_ramp()
315 offset--; in headset_volume_ramp()
327 (struct soc_mixer_control *)kcontrol->private_value; in mt6358_put_volsw()
335 switch (mc->reg) { in mt6358_put_volsw()
337 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); in mt6358_put_volsw()
338 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = in mt6358_put_volsw()
340 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = in mt6358_put_volsw()
344 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); in mt6358_put_volsw()
345 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = in mt6358_put_volsw()
347 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = in mt6358_put_volsw()
351 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); in mt6358_put_volsw()
352 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = in mt6358_put_volsw()
354 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = in mt6358_put_volsw()
359 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); in mt6358_put_volsw()
360 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = in mt6358_put_volsw()
362 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); in mt6358_put_volsw()
363 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = in mt6358_put_volsw()
376 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt6358_enable_wov_phase2()
378 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_enable_wov_phase2()
379 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_enable_wov_phase2()
383 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); in mt6358_enable_wov_phase2()
384 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_enable_wov_phase2()
386 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, in mt6358_enable_wov_phase2()
390 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, in mt6358_enable_wov_phase2()
392 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); in mt6358_enable_wov_phase2()
393 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); in mt6358_enable_wov_phase2()
394 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); in mt6358_enable_wov_phase2()
395 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); in mt6358_enable_wov_phase2()
396 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); in mt6358_enable_wov_phase2()
397 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); in mt6358_enable_wov_phase2()
398 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); in mt6358_enable_wov_phase2()
399 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, in mt6358_enable_wov_phase2()
401 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, in mt6358_enable_wov_phase2()
403 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); in mt6358_enable_wov_phase2()
411 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); in mt6358_disable_wov_phase2()
412 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, in mt6358_disable_wov_phase2()
414 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, in mt6358_disable_wov_phase2()
416 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); in mt6358_disable_wov_phase2()
417 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); in mt6358_disable_wov_phase2()
418 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); in mt6358_disable_wov_phase2()
419 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); in mt6358_disable_wov_phase2()
420 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); in mt6358_disable_wov_phase2()
421 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); in mt6358_disable_wov_phase2()
422 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); in mt6358_disable_wov_phase2()
423 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, in mt6358_disable_wov_phase2()
427 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, in mt6358_disable_wov_phase2()
429 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_disable_wov_phase2()
431 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); in mt6358_disable_wov_phase2()
432 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_disable_wov_phase2()
435 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_disable_wov_phase2()
436 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt6358_disable_wov_phase2()
448 ucontrol->value.integer.value[0] = priv->wov_enabled; in mt6358_get_wov()
457 int enabled = ucontrol->value.integer.value[0]; in mt6358_put_wov()
460 return -EINVAL; in mt6358_put_wov()
462 if (priv->wov_enabled != enabled) { in mt6358_put_wov()
468 priv->wov_enabled = enabled; in mt6358_put_wov()
482 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode; in mt6358_dmic_mode_get()
483 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); in mt6358_dmic_mode_get()
493 int enabled = ucontrol->value.integer.value[0]; in mt6358_dmic_mode_set()
496 return -EINVAL; in mt6358_dmic_mode_set()
498 if (priv->dmic_one_wire_mode != enabled) { in mt6358_dmic_mode_set()
499 priv->dmic_one_wire_mode = enabled; in mt6358_dmic_mode_set()
500 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); in mt6358_dmic_mode_set()
504 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode); in mt6358_dmic_mode_set()
509 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
529 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
795 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_clksq_event()
798 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_clksq_event()
803 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, in mt_clksq_event()
818 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_sgen_event()
821 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
826 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
828 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
830 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
832 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
834 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, in mt_sgen_event()
837 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, in mt_sgen_event()
843 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
844 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
857 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_aif_in_event()
860 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
861 __func__, event, priv->dl_rate); in mt_aif_in_event()
868 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
870 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
872 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
874 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_aif_in_event()
878 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_aif_in_event()
879 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_aif_in_event()
892 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_enable()
895 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_enable()
899 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_enable()
901 /* Set HPR/HPL gain as minimum (~ -40dB) */ in mtk_hp_enable()
902 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); in mtk_hp_enable()
905 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_enable()
907 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_enable()
909 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_enable()
911 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_enable()
913 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_enable()
916 /* Enable cap-less LDOs (1.5V) */ in mtk_hp_enable()
917 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_enable()
919 /* Enable NV regulator (-1.2V) */ in mtk_hp_enable()
920 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_enable()
926 /* Disable headphone short-circuit protection */ in mtk_hp_enable()
927 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_enable()
930 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
933 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_enable()
936 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
938 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_enable()
941 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
943 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
945 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
947 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
949 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
951 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
954 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
956 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
959 /* Selec HS/LO cap size (6.5pF default) */ in mtk_hp_enable()
960 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_enable()
963 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
970 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_enable()
975 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); in mtk_hp_enable()
978 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_enable()
980 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); in mtk_hp_enable()
984 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_enable()
986 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
987 /* Enable low-noise mode of DAC */ in mtk_hp_enable()
988 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
992 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
994 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
996 /* Disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_enable()
1004 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_disable()
1008 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1011 /* Disable low-noise mode of DAC */ in mtk_hp_disable()
1012 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mtk_hp_disable()
1016 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1020 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_disable()
1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_disable()
1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_disable()
1029 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], in mtk_hp_disable()
1033 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_disable()
1042 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1045 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_disable()
1048 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_disable()
1051 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1055 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1059 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_disable()
1063 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mtk_hp_disable()
1066 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1070 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, in mtk_hp_disable()
1074 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mtk_hp_disable()
1077 /* Disable NV regulator (-1.2V) */ in mtk_hp_disable()
1078 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_disable()
1079 /* Disable cap-less LDOs (1.5V) */ in mtk_hp_disable()
1080 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_disable()
1083 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, in mtk_hp_disable()
1087 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, in mtk_hp_disable()
1091 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_disable()
1093 /* disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_disable()
1101 /* Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_enable()
1104 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_spk_enable()
1108 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_spk_enable()
1110 /* Set HPR/HPL gain to -10dB */ in mtk_hp_spk_enable()
1111 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); in mtk_hp_spk_enable()
1114 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_spk_enable()
1116 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_spk_enable()
1118 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_spk_enable()
1120 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_spk_enable()
1122 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_spk_enable()
1125 /* Enable cap-less LDOs (1.5V) */ in mtk_hp_spk_enable()
1126 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mtk_hp_spk_enable()
1128 /* Enable NV regulator (-1.2V) */ in mtk_hp_spk_enable()
1129 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_spk_enable()
1135 /* Disable headphone short-circuit protection */ in mtk_hp_spk_enable()
1136 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_spk_enable()
1139 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1142 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_spk_enable()
1145 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1147 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_spk_enable()
1149 /* Disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_enable()
1153 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_spk_enable()
1155 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_spk_enable()
1157 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_spk_enable()
1160 /* Selec HS/LO cap size (6.5pF default) */ in mtk_hp_spk_enable()
1161 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_spk_enable()
1164 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); in mtk_hp_spk_enable()
1168 /* Set LO gain as minimum (~ -40dB) */ in mtk_hp_spk_enable()
1169 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); in mtk_hp_spk_enable()
1173 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); in mtk_hp_spk_enable()
1176 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); in mtk_hp_spk_enable()
1178 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); in mtk_hp_spk_enable()
1180 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); in mtk_hp_spk_enable()
1183 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_enable()
1185 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << in mtk_hp_spk_enable()
1187 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_enable()
1189 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << in mtk_hp_spk_enable()
1193 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_spk_enable()
1195 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); in mtk_hp_spk_enable()
1196 /* Enable low-noise mode of DAC */ in mtk_hp_spk_enable()
1197 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); in mtk_hp_spk_enable()
1199 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); in mtk_hp_spk_enable()
1200 /* Switch HPL/R MUX to Line-out */ in mtk_hp_spk_enable()
1201 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); in mtk_hp_spk_enable()
1209 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1212 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1216 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1220 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_spk_disable()
1224 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], in mtk_hp_spk_disable()
1228 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, in mtk_hp_spk_disable()
1235 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_spk_disable()
1238 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_spk_disable()
1240 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_spk_disable()
1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_spk_disable()
1249 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1252 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1256 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mtk_hp_spk_disable()
1259 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mtk_hp_spk_disable()
1263 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mtk_hp_spk_disable()
1267 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mtk_hp_spk_disable()
1269 /* Disable NV regulator (-1.2V) */ in mtk_hp_spk_disable()
1270 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_spk_disable()
1271 /* Disable cap-less LDOs (1.5V) */ in mtk_hp_spk_disable()
1272 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); in mtk_hp_spk_disable()
1274 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); in mtk_hp_spk_disable()
1277 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, in mtk_hp_spk_disable()
1279 /* disable Pull-down HPL/R to AVSS28_AUD */ in mtk_hp_spk_disable()
1289 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_hp_event()
1291 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1294 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1297 priv->dev_counter[device], in mt_hp_event()
1302 priv->dev_counter[device]++; in mt_hp_event()
1303 if (priv->dev_counter[device] > 1) in mt_hp_event()
1305 else if (priv->dev_counter[device] <= 0) in mt_hp_event()
1306 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", in mt_hp_event()
1308 priv->dev_counter[device]); in mt_hp_event()
1310 priv->mux_select[MUX_HP_L] = mux; in mt_hp_event()
1318 priv->dev_counter[device]--; in mt_hp_event()
1319 if (priv->dev_counter[device] > 0) { in mt_hp_event()
1321 } else if (priv->dev_counter[device] < 0) { in mt_hp_event()
1322 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", in mt_hp_event()
1324 priv->dev_counter[device]); in mt_hp_event()
1325 priv->dev_counter[device] = 0; in mt_hp_event()
1329 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) in mt_hp_event()
1331 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) in mt_hp_event()
1334 priv->mux_select[MUX_HP_L] = mux; in mt_hp_event()
1347 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_rcv_event()
1350 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1353 dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1358 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mt_rcv_event()
1361 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mt_rcv_event()
1363 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mt_rcv_event()
1365 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mt_rcv_event()
1367 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mt_rcv_event()
1369 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mt_rcv_event()
1372 /* Enable cap-less LDOs (1.5V) */ in mt_rcv_event()
1373 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_rcv_event()
1375 /* Enable NV regulator (-1.2V) */ in mt_rcv_event()
1376 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mt_rcv_event()
1382 /* Disable handset short-circuit protection */ in mt_rcv_event()
1383 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1386 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1388 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mt_rcv_event()
1391 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1393 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1396 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mt_rcv_event()
1398 /* Selec HS/LO cap size (6.5pF default) */ in mt_rcv_event()
1399 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mt_rcv_event()
1402 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1404 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1407 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_rcv_event()
1411 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1412 /* Enable low-noise mode of DAC */ in mt_rcv_event()
1413 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1415 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1419 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1424 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt_rcv_event()
1428 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_rcv_event()
1432 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); in mt_rcv_event()
1435 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1439 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt_rcv_event()
1443 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mt_rcv_event()
1447 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, in mt_rcv_event()
1451 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, in mt_rcv_event()
1454 /* Disable NV regulator (-1.2V) */ in mt_rcv_event()
1455 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, in mt_rcv_event()
1457 /* Disable cap-less LDOs (1.5V) */ in mt_rcv_event()
1458 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_rcv_event()
1461 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, in mt_rcv_event()
1475 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_aif_out_event()
1478 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
1479 __func__, event, priv->ul_rate); in mt_aif_out_event()
1499 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_supply_event()
1502 dev_dbg(priv->dev, "%s(), event 0x%x\n", in mt_adc_supply_event()
1508 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_adc_supply_event()
1511 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, in mt_adc_supply_event()
1514 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1517 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1522 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1525 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, in mt_adc_supply_event()
1529 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); in mt_adc_supply_event()
1531 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, in mt_adc_supply_event()
1543 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; in mt6358_amic_enable()
1544 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; in mt6358_amic_enable()
1545 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; in mt6358_amic_enable()
1547 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", in mt6358_amic_enable()
1552 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1553 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1554 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_enable()
1555 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); in mt6358_amic_enable()
1556 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); in mt6358_amic_enable()
1564 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1568 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1572 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1577 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, in mt6358_amic_enable()
1583 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ in mt6358_amic_enable()
1585 regmap_write(priv->regmap, in mt6358_amic_enable()
1588 regmap_write(priv->regmap, in mt6358_amic_enable()
1594 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1596 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1600 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1602 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1608 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1613 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1619 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1625 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1629 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1636 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1641 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1647 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1653 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1657 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_enable()
1668 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_enable()
1672 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, in mt6358_amic_enable()
1680 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); in mt6358_amic_enable()
1683 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); in mt6358_amic_enable()
1690 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; in mt6358_amic_disable()
1691 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; in mt6358_amic_disable()
1692 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; in mt6358_amic_disable()
1694 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", in mt6358_amic_disable()
1698 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, in mt6358_amic_disable()
1705 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1708 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1711 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1715 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_amic_disable()
1719 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1722 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1725 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1729 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_amic_disable()
1734 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_amic_disable()
1736 /* Disable MICBIAS1 */ in mt6358_amic_disable()
1737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_amic_disable()
1742 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_disable()
1744 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1746 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1748 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1754 dev_info(priv->dev, "%s()\n", __func__); in mt6358_dmic_enable()
1758 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); in mt6358_dmic_enable()
1761 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_dmic_enable()
1765 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); in mt6358_dmic_enable()
1771 if (priv->dmic_one_wire_mode) in mt6358_dmic_enable()
1772 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); in mt6358_dmic_enable()
1774 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); in mt6358_dmic_enable()
1777 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); in mt6358_dmic_enable()
1787 dev_info(priv->dev, "%s()\n", __func__); in mt6358_dmic_disable()
1790 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, in mt6358_dmic_disable()
1797 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); in mt6358_dmic_disable()
1801 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); in mt6358_dmic_disable()
1804 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, in mt6358_dmic_disable()
1808 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_dmic_disable()
1815 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; in mt6358_restore_pga()
1816 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; in mt6358_restore_pga()
1818 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, in mt6358_restore_pga()
1821 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, in mt6358_restore_pga()
1830 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_mic_type_event()
1832 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_mic_type_event()
1834 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_mic_type_event()
1839 priv->mux_select[MUX_MIC_TYPE] = mux; in mt_mic_type_event()
1854 switch (priv->mux_select[MUX_MIC_TYPE]) { in mt_mic_type_event()
1863 priv->mux_select[MUX_MIC_TYPE] = mux; in mt_mic_type_event()
1876 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_l_event()
1878 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_l_event()
1880 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_l_event()
1883 priv->mux_select[MUX_ADC_L] = mux; in mt_adc_l_event()
1892 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_adc_r_event()
1894 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_r_event()
1896 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_r_event()
1899 priv->mux_select[MUX_ADC_R] = mux; in mt_adc_r_event()
1908 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_pga_left_event()
1910 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_left_event()
1912 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_left_event()
1915 priv->mux_select[MUX_PGA_L] = mux; in mt_pga_left_event()
1924 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in mt_pga_right_event()
1926 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_right_event()
1928 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_right_event()
1931 priv->mux_select[MUX_PGA_R] = mux; in mt_pga_right_event()
2067 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2068 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2239 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2240 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2252 struct snd_soc_component *cmpnt = dai->component; in mt6358_codec_dai_hw_params()
2256 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", in mt6358_codec_dai_hw_params()
2258 substream->stream, in mt6358_codec_dai_hw_params()
2260 substream->number); in mt6358_codec_dai_hw_params()
2262 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in mt6358_codec_dai_hw_params()
2263 priv->dl_rate = rate; in mt6358_codec_dai_hw_params()
2264 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in mt6358_codec_dai_hw_params()
2265 priv->ul_rate = rate; in mt6358_codec_dai_hw_params()
2280 .name = "mt6358-snd-codec-aif1",
2307 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt6358_codec_init_reg()
2310 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, in mt6358_codec_init_reg()
2314 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, in mt6358_codec_init_reg()
2318 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, in mt6358_codec_init_reg()
2323 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, in mt6358_codec_init_reg()
2327 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); in mt6358_codec_init_reg()
2339 snd_soc_component_init_regmap(cmpnt, priv->regmap); in mt6358_codec_probe()
2343 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); in mt6358_codec_probe()
2344 if (IS_ERR(priv->avdd_reg)) { in mt6358_codec_probe()
2345 dev_err(priv->dev, "%s() have no Avdd supply", __func__); in mt6358_codec_probe()
2346 return PTR_ERR(priv->avdd_reg); in mt6358_codec_probe()
2349 ret = regulator_enable(priv->avdd_reg); in mt6358_codec_probe()
2370 struct device *dev = priv->dev; in mt6358_parse_dt()
2372 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode", in mt6358_parse_dt()
2373 &priv->dmic_one_wire_mode); in mt6358_parse_dt()
2375 dev_warn(priv->dev, "%s() failed to read dmic-mode\n", in mt6358_parse_dt()
2377 priv->dmic_one_wire_mode = 0; in mt6358_parse_dt()
2384 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); in mt6358_platform_driver_probe()
2386 priv = devm_kzalloc(&pdev->dev, in mt6358_platform_driver_probe()
2390 return -ENOMEM; in mt6358_platform_driver_probe()
2392 dev_set_drvdata(&pdev->dev, priv); in mt6358_platform_driver_probe()
2394 priv->dev = &pdev->dev; in mt6358_platform_driver_probe()
2396 priv->regmap = mt6397->regmap; in mt6358_platform_driver_probe()
2397 if (IS_ERR(priv->regmap)) in mt6358_platform_driver_probe()
2398 return PTR_ERR(priv->regmap); in mt6358_platform_driver_probe()
2402 dev_info(priv->dev, "%s(), dev name %s\n", in mt6358_platform_driver_probe()
2403 __func__, dev_name(&pdev->dev)); in mt6358_platform_driver_probe()
2405 return devm_snd_soc_register_component(&pdev->dev, in mt6358_platform_driver_probe()
2412 {.compatible = "mediatek,mt6358-sound",},
2413 {.compatible = "mediatek,mt6366-sound",},
2420 .name = "mt6358-sound",