Lines Matching full:lane
21 unsigned int lane; member
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
64 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
156 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
162 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
184 t_data.lane = params->lane; in sdw_compute_master_ports()
199 /* reset hstop for each lane */ in _sdw_compute_port_params()
202 if (params[i].lane != l) in _sdw_compute_port_params()
229 params[i].lane = group->lanes[i]; in sdw_compute_group_params()
254 if (rate == params[i].rate && p_rt->lane == params[i].lane) in sdw_compute_group_params()
263 /* reset column_needed for each lane */ in sdw_compute_group_params()
266 if (params[i].lane != l) in sdw_compute_group_params()
273 /* There is no control column for lane 1 and above */ in sdw_compute_group_params()
276 /* Column 0 is control column on lane 0 */ in sdw_compute_group_params()
277 if (params[i].lane == 0 && column_needed > sel_col - 1) in sdw_compute_group_params()
287 unsigned int rate, unsigned int lane) in sdw_add_element_group_count() argument
293 if (rate == group->rates[i] && lane == group->lanes[i]) in sdw_add_element_group_count()
322 group->lanes[group->count++] = lane; in sdw_add_element_group_count()
360 * Different ports could use different lane, add group element in sdw_get_group_count()
364 ret = sdw_add_element_group_count(group, rate, p_rt->lane); in sdw_get_group_count()
455 * is_lane_connected_to_all_peripherals: Check if the given manager lane connects to all peripherals
456 * So that all peripherals can use the manager lane.
459 * @lane: Lane number
461 static bool is_lane_connected_to_all_peripherals(struct sdw_master_runtime *m_rt, unsigned int lane) in is_lane_connected_to_all_peripherals() argument
470 if (slave_prop->lane_maps[i] == lane) { in is_lane_connected_to_all_peripherals()
472 "M lane %d is connected to P lane %d\n", in is_lane_connected_to_all_peripherals()
473 lane, i); in is_lane_connected_to_all_peripherals()
478 dev_dbg(&s_rt->slave->dev, "M lane %d is not connected\n", lane); in is_lane_connected_to_all_peripherals()
510 "Not all Peripherals are connected to M lane %d\n", in get_manager_lane()
515 dev_dbg(&s_rt->slave->dev, "M lane %d is used\n", m_lane); in get_manager_lane()
518 * Use non-zero manager lane, subtract the lane 0 in get_manager_lane()
526 /* No available multi lane found, only lane 0 can be used */ in get_manager_lane()
579 * Get the first s_rt that will be used to find the available lane that in sdw_compute_bus_params()
581 * multi-lane if we can't find any available lane for the first Peripheral. in sdw_compute_bus_params()
587 * Find the available Manager lane that connected to the first Peripheral. in sdw_compute_bus_params()
615 s_p_rt->lane = l; in sdw_compute_bus_params()
617 "Set P lane %d for port %d\n", in sdw_compute_bus_params()
629 m_p_rt->lane = m_lane; in sdw_compute_bus_params()