Lines Matching +full:nand +full:- +full:is +full:- +full:boot +full:- +full:medium
1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
19 #include <linux/dma/mxs-dma.h>
21 #include "gpmi-nand.h"
22 #include "gpmi-regs.h"
23 #include "bch-regs.h"
25 /* Resource names for the GPMI NAND driver. */
26 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
36 * Clear the bit and poll it cleared. This is usually called with
54 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
68 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
70 * the next hard reset. This case occurs in the NAND boot mode. When the board
71 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
98 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
118 return -ETIMEDOUT; in gpmi_reset_block()
128 clk = this->resources.clock[i]; in __gpmi_enable_clk()
143 for (; i > 0; i--) in __gpmi_enable_clk()
144 clk_disable_unprepare(this->resources.clock[i - 1]); in __gpmi_enable_clk()
150 struct resources *r = &this->resources; in gpmi_init()
153 ret = pm_runtime_resume_and_get(this->dev); in gpmi_init()
157 ret = gpmi_reset_block(r->gpmi_regs, false); in gpmi_init()
165 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); in gpmi_init()
169 /* Choose NAND mode. */ in gpmi_init()
170 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR); in gpmi_init()
174 r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
176 /* Disable Write-Protection. */ in gpmi_init()
177 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
180 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
184 * the chips, force all NAND RDY_BUSY inputs to be sourced from in gpmi_init()
188 r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
191 pm_runtime_mark_last_busy(this->dev); in gpmi_init()
192 pm_runtime_put_autosuspend(this->dev); in gpmi_init()
196 /* This function is very useful. It is called only when the bug occur. */
199 struct resources *r = &this->resources; in gpmi_dump_info()
200 struct bch_geometry *geo = &this->bch_geometry; in gpmi_dump_info()
204 dev_err(this->dev, "Show GPMI registers :\n"); in gpmi_dump_info()
206 reg = readl(r->gpmi_regs + i * 0x10); in gpmi_dump_info()
207 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); in gpmi_dump_info()
211 dev_err(this->dev, "Show BCH registers :\n"); in gpmi_dump_info()
213 reg = readl(r->bch_regs + i * 0x10); in gpmi_dump_info()
214 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); in gpmi_dump_info()
216 dev_err(this->dev, "BCH Geometry :\n" in gpmi_dump_info()
229 geo->gf_len, in gpmi_dump_info()
230 geo->ecc_strength, in gpmi_dump_info()
231 geo->page_size, in gpmi_dump_info()
232 geo->metadata_size, in gpmi_dump_info()
233 geo->ecc0_chunk_size, in gpmi_dump_info()
234 geo->eccn_chunk_size, in gpmi_dump_info()
235 geo->ecc_chunk_count, in gpmi_dump_info()
236 geo->payload_size, in gpmi_dump_info()
237 geo->auxiliary_size, in gpmi_dump_info()
238 geo->auxiliary_status_offset, in gpmi_dump_info()
239 geo->block_mark_byte_offset, in gpmi_dump_info()
240 geo->block_mark_bit_offset); in gpmi_dump_info()
245 struct nand_chip *chip = &this->nand; in gpmi_check_ecc()
246 struct bch_geometry *geo = &this->bch_geometry; in gpmi_check_ecc()
247 struct nand_device *nand = &chip->base; in gpmi_check_ecc() local
248 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in gpmi_check_ecc()
250 conf->step_size = geo->eccn_chunk_size; in gpmi_check_ecc()
251 conf->strength = geo->ecc_strength; in gpmi_check_ecc()
256 if (geo->gf_len == 14) in gpmi_check_ecc()
260 if (geo->ecc_strength > this->devdata->bch_max_ecc_strength) in gpmi_check_ecc()
263 if (!nand_ecc_is_strong_enough(nand)) in gpmi_check_ecc()
273 struct bch_geometry *geo = &this->bch_geometry; in bbm_in_data_chunk()
274 struct nand_chip *chip = &this->nand; in bbm_in_data_chunk()
278 if (geo->ecc0_chunk_size != geo->eccn_chunk_size) { in bbm_in_data_chunk()
279 dev_err(this->dev, in bbm_in_data_chunk()
284 i = (mtd->writesize * 8 - geo->metadata_size * 8) / in bbm_in_data_chunk()
285 (geo->gf_len * geo->ecc_strength + in bbm_in_data_chunk()
286 geo->eccn_chunk_size * 8); in bbm_in_data_chunk()
288 j = (mtd->writesize * 8 - geo->metadata_size * 8) - in bbm_in_data_chunk()
289 (geo->gf_len * geo->ecc_strength + in bbm_in_data_chunk()
290 geo->eccn_chunk_size * 8) * i; in bbm_in_data_chunk()
292 if (j < geo->eccn_chunk_size * 8) { in bbm_in_data_chunk()
294 dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n", in bbm_in_data_chunk()
295 geo->ecc_strength, *chunk_num); in bbm_in_data_chunk()
303 * If we can get the ECC information from the nand chip, we do not
312 struct bch_geometry *geo = &this->bch_geometry; in set_geometry_by_ecc_info()
313 struct nand_chip *chip = &this->nand; in set_geometry_by_ecc_info()
319 geo->gf_len = 13; in set_geometry_by_ecc_info()
322 geo->gf_len = 14; in set_geometry_by_ecc_info()
325 dev_err(this->dev, in set_geometry_by_ecc_info()
326 "unsupported nand chip. ecc bits : %d, ecc size : %d\n", in set_geometry_by_ecc_info()
327 nanddev_get_ecc_requirements(&chip->base)->strength, in set_geometry_by_ecc_info()
328 nanddev_get_ecc_requirements(&chip->base)->step_size); in set_geometry_by_ecc_info()
329 return -EINVAL; in set_geometry_by_ecc_info()
331 geo->ecc0_chunk_size = ecc_step; in set_geometry_by_ecc_info()
332 geo->eccn_chunk_size = ecc_step; in set_geometry_by_ecc_info()
333 geo->ecc_strength = round_up(ecc_strength, 2); in set_geometry_by_ecc_info()
335 return -EINVAL; in set_geometry_by_ecc_info()
338 if (geo->eccn_chunk_size < mtd->oobsize) { in set_geometry_by_ecc_info()
339 dev_err(this->dev, in set_geometry_by_ecc_info()
340 "unsupported nand chip. ecc size: %d, oob size : %d\n", in set_geometry_by_ecc_info()
341 ecc_step, mtd->oobsize); in set_geometry_by_ecc_info()
342 return -EINVAL; in set_geometry_by_ecc_info()
346 geo->metadata_size = 10; in set_geometry_by_ecc_info()
348 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in set_geometry_by_ecc_info()
351 * Now, the NAND chip with 2K page(data chunk is 512byte) shows below: in set_geometry_by_ecc_info()
354 * |<----------------------------------------------------->| in set_geometry_by_ecc_info()
358 * |<-------------------------------------------->| D | | O' | in set_geometry_by_ecc_info()
359 * | |<---->| |<--->| in set_geometry_by_ecc_info()
361 * +---+----------+-+----------+-+----------+-+----------+-+-----+ in set_geometry_by_ecc_info()
363 * +---+----------+-+----------+-+----------+-+----------+-+-----+ in set_geometry_by_ecc_info()
366 * |<------------>| in set_geometry_by_ecc_info()
375 * P': the nand chip's page size. in set_geometry_by_ecc_info()
376 * O : the nand chip's oob size. in set_geometry_by_ecc_info()
379 * The formula for P is : in set_geometry_by_ecc_info()
382 * P = ------------ + P' + M in set_geometry_by_ecc_info()
385 * The position of block mark moves forward in the ECC-based view in set_geometry_by_ecc_info()
386 * of page, and the delta is: in set_geometry_by_ecc_info()
388 * E * G * (N - 1) in set_geometry_by_ecc_info()
389 * D = (---------------- + M) in set_geometry_by_ecc_info()
394 * So the bit position of the physical block mark within the ECC-based in set_geometry_by_ecc_info()
395 * view of the page is : in set_geometry_by_ecc_info()
396 * (P' - D) * 8 in set_geometry_by_ecc_info()
398 geo->page_size = mtd->writesize + geo->metadata_size + in set_geometry_by_ecc_info()
399 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in set_geometry_by_ecc_info()
401 geo->payload_size = mtd->writesize; in set_geometry_by_ecc_info()
403 geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4); in set_geometry_by_ecc_info()
404 geo->auxiliary_size = ALIGN(geo->metadata_size, 4) in set_geometry_by_ecc_info()
405 + ALIGN(geo->ecc_chunk_count, 4); in set_geometry_by_ecc_info()
407 if (!this->swap_block_mark) in set_geometry_by_ecc_info()
411 block_mark_bit_offset = mtd->writesize * 8 - in set_geometry_by_ecc_info()
412 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) in set_geometry_by_ecc_info()
413 + geo->metadata_size * 8); in set_geometry_by_ecc_info()
415 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in set_geometry_by_ecc_info()
416 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in set_geometry_by_ecc_info()
425 * O : the oobsize of the NAND chip.
428 * The formula is :
430 * ------------ <= (O - M)
434 * (O - M) * 8
435 * E <= -------------
440 struct bch_geometry *geo = &this->bch_geometry; in get_ecc_strength()
441 struct mtd_info *mtd = nand_to_mtd(&this->nand); in get_ecc_strength()
444 ecc_strength = ((mtd->oobsize - geo->metadata_size) * 8) in get_ecc_strength()
445 / (geo->gf_len * geo->ecc_chunk_count); in get_ecc_strength()
453 struct bch_geometry *geo = &this->bch_geometry; in set_geometry_for_large_oob()
454 struct nand_chip *chip = &this->nand; in set_geometry_for_large_oob()
457 nanddev_get_ecc_requirements(&chip->base); in set_geometry_for_large_oob()
463 /* sanity check for the minimum ecc nand required */ in set_geometry_for_large_oob()
464 if (!(requirements->strength > 0 && in set_geometry_for_large_oob()
465 requirements->step_size > 0)) in set_geometry_for_large_oob()
466 return -EINVAL; in set_geometry_for_large_oob()
467 geo->ecc_strength = requirements->strength; in set_geometry_for_large_oob()
469 /* check if platform can support this nand */ in set_geometry_for_large_oob()
471 dev_err(this->dev, in set_geometry_for_large_oob()
472 "unsupported NAND chip, minimum ecc required %d\n", in set_geometry_for_large_oob()
473 geo->ecc_strength); in set_geometry_for_large_oob()
474 return -EINVAL; in set_geometry_for_large_oob()
478 geo->metadata_size = 10; in set_geometry_for_large_oob()
479 geo->gf_len = 14; in set_geometry_for_large_oob()
480 geo->ecc0_chunk_size = 1024; in set_geometry_for_large_oob()
481 geo->eccn_chunk_size = 1024; in set_geometry_for_large_oob()
482 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in set_geometry_for_large_oob()
484 this->devdata->bch_max_ecc_strength); in set_geometry_for_large_oob()
490 geo->ecc_strength = max_ecc; in set_geometry_for_large_oob()
491 while (!(geo->ecc_strength < requirements->strength)) { in set_geometry_for_large_oob()
494 geo->ecc_strength -= 2; in set_geometry_for_large_oob()
498 /* nand required but changing ecc page layout */ in set_geometry_for_large_oob()
499 geo->ecc_strength = requirements->strength; in set_geometry_for_large_oob()
501 geo->ecc0_chunk_size = 0; in set_geometry_for_large_oob()
502 geo->ecc_chunk_count = (mtd->writesize / geo->eccn_chunk_size) + 1; in set_geometry_for_large_oob()
503 geo->ecc_for_meta = 1; in set_geometry_for_large_oob()
505 if (mtd->oobsize * 8 < geo->metadata_size * 8 + in set_geometry_for_large_oob()
506 geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) { in set_geometry_for_large_oob()
507 dev_err(this->dev, "unsupported NAND chip with new layout\n"); in set_geometry_for_large_oob()
508 return -EINVAL; in set_geometry_for_large_oob()
512 bbm_chunk = (mtd->writesize * 8 - geo->metadata_size * 8 - in set_geometry_for_large_oob()
513 geo->gf_len * geo->ecc_strength) / in set_geometry_for_large_oob()
514 (geo->gf_len * geo->ecc_strength + in set_geometry_for_large_oob()
515 geo->eccn_chunk_size * 8) + 1; in set_geometry_for_large_oob()
519 geo->page_size = mtd->writesize + geo->metadata_size + in set_geometry_for_large_oob()
520 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in set_geometry_for_large_oob()
521 geo->payload_size = mtd->writesize; in set_geometry_for_large_oob()
525 * metadata is padded to the nearest 32-bit boundary. The ECC status in set_geometry_for_large_oob()
526 * contains one byte for every ECC chunk, and is also padded to the in set_geometry_for_large_oob()
527 * nearest 32-bit boundary. in set_geometry_for_large_oob()
529 geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4); in set_geometry_for_large_oob()
530 geo->auxiliary_size = ALIGN(geo->metadata_size, 4) in set_geometry_for_large_oob()
531 + ALIGN(geo->ecc_chunk_count, 4); in set_geometry_for_large_oob()
533 if (!this->swap_block_mark) in set_geometry_for_large_oob()
537 i = (mtd->writesize / geo->eccn_chunk_size) - bbm_chunk + 1; in set_geometry_for_large_oob()
539 block_mark_bit_offset = mtd->writesize * 8 - in set_geometry_for_large_oob()
540 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i) in set_geometry_for_large_oob()
541 + geo->metadata_size * 8); in set_geometry_for_large_oob()
543 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in set_geometry_for_large_oob()
544 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in set_geometry_for_large_oob()
546 dev_dbg(this->dev, "BCH Geometry :\n" in set_geometry_for_large_oob()
561 geo->gf_len, in set_geometry_for_large_oob()
562 geo->ecc_strength, in set_geometry_for_large_oob()
563 geo->page_size, in set_geometry_for_large_oob()
564 geo->metadata_size, in set_geometry_for_large_oob()
565 geo->ecc0_chunk_size, in set_geometry_for_large_oob()
566 geo->eccn_chunk_size, in set_geometry_for_large_oob()
567 geo->ecc_chunk_count, in set_geometry_for_large_oob()
568 geo->payload_size, in set_geometry_for_large_oob()
569 geo->auxiliary_size, in set_geometry_for_large_oob()
570 geo->auxiliary_status_offset, in set_geometry_for_large_oob()
571 geo->block_mark_byte_offset, in set_geometry_for_large_oob()
572 geo->block_mark_bit_offset, in set_geometry_for_large_oob()
574 geo->ecc_for_meta); in set_geometry_for_large_oob()
581 struct bch_geometry *geo = &this->bch_geometry; in legacy_set_geometry()
582 struct mtd_info *mtd = nand_to_mtd(&this->nand); in legacy_set_geometry()
592 geo->metadata_size = 10; in legacy_set_geometry()
595 geo->gf_len = 13; in legacy_set_geometry()
598 geo->ecc0_chunk_size = 512; in legacy_set_geometry()
599 geo->eccn_chunk_size = 512; in legacy_set_geometry()
600 while (geo->eccn_chunk_size < mtd->oobsize) { in legacy_set_geometry()
601 geo->ecc0_chunk_size *= 2; /* keep C >= O */ in legacy_set_geometry()
602 geo->eccn_chunk_size *= 2; /* keep C >= O */ in legacy_set_geometry()
603 geo->gf_len = 14; in legacy_set_geometry()
606 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in legacy_set_geometry()
609 geo->ecc_strength = get_ecc_strength(this); in legacy_set_geometry()
611 dev_err(this->dev, in legacy_set_geometry()
613 "try to use minimum ecc strength that NAND chip required\n", in legacy_set_geometry()
614 geo->ecc_strength, in legacy_set_geometry()
615 this->devdata->bch_max_ecc_strength); in legacy_set_geometry()
616 return -EINVAL; in legacy_set_geometry()
619 geo->page_size = mtd->writesize + geo->metadata_size + in legacy_set_geometry()
620 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in legacy_set_geometry()
621 geo->payload_size = mtd->writesize; in legacy_set_geometry()
625 * metadata is padded to the nearest 32-bit boundary. The ECC status in legacy_set_geometry()
626 * contains one byte for every ECC chunk, and is also padded to the in legacy_set_geometry()
627 * nearest 32-bit boundary. in legacy_set_geometry()
629 metadata_size = ALIGN(geo->metadata_size, 4); in legacy_set_geometry()
630 status_size = ALIGN(geo->ecc_chunk_count, 4); in legacy_set_geometry()
632 geo->auxiliary_size = metadata_size + status_size; in legacy_set_geometry()
633 geo->auxiliary_status_offset = metadata_size; in legacy_set_geometry()
635 if (!this->swap_block_mark) in legacy_set_geometry()
640 * the physical block mark within the ECC-based view of the page. in legacy_set_geometry()
642 * NAND chip with 2K page shows below: in legacy_set_geometry()
646 * |<---->| in legacy_set_geometry()
648 * +---+----------+-+----------+-+----------+-+----------+-+ in legacy_set_geometry()
650 * +---+----------+-+----------+-+----------+-+----------+-+ in legacy_set_geometry()
652 * The position of block mark moves forward in the ECC-based view in legacy_set_geometry()
653 * of page, and the delta is: in legacy_set_geometry()
655 * E * G * (N - 1) in legacy_set_geometry()
656 * D = (---------------- + M) in legacy_set_geometry()
660 * : C >= O (C is the ecc chunk size) in legacy_set_geometry()
664 * E * G (O - M) C - M C - M in legacy_set_geometry()
665 * ----------- <= ------- <= -------- < --------- in legacy_set_geometry()
666 * 8 N N (N - 1) in legacy_set_geometry()
670 * E * G * (N - 1) in legacy_set_geometry()
671 * D = (---------------- + M) < C in legacy_set_geometry()
675 * within the ECC-based view of the page is still in the data chunk, in legacy_set_geometry()
679 * physical block mark within the ECC-based view of the page: in legacy_set_geometry()
680 * (page_size - D) * 8 in legacy_set_geometry()
682 * --Huang Shijie in legacy_set_geometry()
684 block_mark_bit_offset = mtd->writesize * 8 - in legacy_set_geometry()
685 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) in legacy_set_geometry()
686 + geo->metadata_size * 8); in legacy_set_geometry()
688 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in legacy_set_geometry()
689 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in legacy_set_geometry()
695 struct nand_chip *chip = &this->nand; in common_nfc_set_geometry()
696 struct mtd_info *mtd = nand_to_mtd(&this->nand); in common_nfc_set_geometry()
698 nanddev_get_ecc_requirements(&chip->base); in common_nfc_set_geometry()
702 use_minimun_ecc = of_property_read_bool(this->dev->of_node, in common_nfc_set_geometry()
703 "fsl,use-minimum-ecc"); in common_nfc_set_geometry()
706 if ((!use_minimun_ecc && mtd->oobsize < 1024) || in common_nfc_set_geometry()
707 !(requirements->strength > 0 && requirements->step_size > 0)) { in common_nfc_set_geometry()
708 dev_dbg(this->dev, "use legacy bch geometry\n"); in common_nfc_set_geometry()
714 /* for large oob nand */ in common_nfc_set_geometry()
715 if (mtd->oobsize > 1024) { in common_nfc_set_geometry()
716 dev_dbg(this->dev, "use large oob bch geometry\n"); in common_nfc_set_geometry()
722 /* otherwise use the minimum ecc nand chip required */ in common_nfc_set_geometry()
723 dev_dbg(this->dev, "use minimum ecc bch geometry\n"); in common_nfc_set_geometry()
724 err = set_geometry_by_ecc_info(this, requirements->strength, in common_nfc_set_geometry()
725 requirements->step_size); in common_nfc_set_geometry()
727 dev_err(this->dev, "none of the bch geometry setting works\n"); in common_nfc_set_geometry()
735 struct resources *r = &this->resources; in bch_set_geometry()
742 ret = pm_runtime_resume_and_get(this->dev); in bch_set_geometry()
752 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); in bch_set_geometry()
757 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT); in bch_set_geometry()
761 pm_runtime_mark_last_busy(this->dev); in bch_set_geometry()
762 pm_runtime_put_autosuspend(this->dev); in bch_set_geometry()
768 * <1> Firstly, we should know what's the GPMI-clock means.
769 * The GPMI-clock is the internal clock in the gpmi nand controller.
770 * If you set 100MHz to gpmi nand controller, the GPMI-clock's period
771 * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
773 * <2> Secondly, we should know what's the frequency on the nand chip pins.
774 * The frequency on the nand chip pins is derived from the GPMI-clock.
779 * F : the frequency on the nand chip pins.
784 * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
785 * the nand EDO(extended Data Out) timing could be applied.
787 * The feedback read strobe can be delayed to support the nand EDO timing
788 * where the read strobe may deasserts before the read data is valid, and
789 * read data is valid for some time after read strobe.
791 * The following figure illustrates some aspects of a NAND Flash read:
793 * |<---tREA---->|
796 * |<--tRP-->| |
801 * /---------\
802 * Read Data --------------< >---------
803 * \---------/
805 * |<-D->|
814 * 4.1) From the aspect of the nand chip pins:
815 * Delay = (tREA + C - tRP) {1}
818 * C : a constant to adjust the delay. default is 4000ps.
819 * tRP : the read pulse width, which is exactly:
820 * tRP = (GPMI-clock-period) * DATA_SETUP
822 * 4.2) From the aspect of the GPMI nand controller:
826 * if (GPMI-clock-period > DLL_THRETHOLD)
827 * RP = GPMI-clock-period / 2;
829 * RP = GPMI-clock-period;
831 * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
832 * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
833 * is 16000ps, but in mx6q, we use 12000ps.
837 * (tREA + 4000 - tRP) * 8
838 * RDN_DELAY = ----------------------- {3}
844 struct gpmi_nfc_hardware_timing *hw = &this->hw; in gpmi_nfc_compute_timings()
845 struct resources *r = &this->resources; in gpmi_nfc_compute_timings()
846 unsigned int dll_threshold_ps = this->devdata->max_chain_delay; in gpmi_nfc_compute_timings()
857 if (sdr->tRC_min >= 30000) { in gpmi_nfc_compute_timings()
858 /* ONFI non-EDO modes [0-3] */ in gpmi_nfc_compute_timings()
859 hw->clk_rate = 22000000; in gpmi_nfc_compute_timings()
862 } else if (sdr->tRC_min >= 25000) { in gpmi_nfc_compute_timings()
864 hw->clk_rate = 80000000; in gpmi_nfc_compute_timings()
869 hw->clk_rate = 100000000; in gpmi_nfc_compute_timings()
874 clk_rate = clk_round_rate(r->clock[0], hw->clk_rate); in gpmi_nfc_compute_timings()
876 dev_err(this->dev, "clock setting: expected %ld, got %ld\n", in gpmi_nfc_compute_timings()
877 hw->clk_rate, clk_rate); in gpmi_nfc_compute_timings()
878 return -ENOTSUPP; in gpmi_nfc_compute_timings()
881 hw->clk_rate = clk_rate; in gpmi_nfc_compute_timings()
883 period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); in gpmi_nfc_compute_timings()
885 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); in gpmi_nfc_compute_timings()
886 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); in gpmi_nfc_compute_timings()
887 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); in gpmi_nfc_compute_timings()
888 busy_timeout_ps = max(sdr->tBERS_max, sdr->tPROG_max); in gpmi_nfc_compute_timings()
891 hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) | in gpmi_nfc_compute_timings()
894 hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(DIV_ROUND_UP(busy_timeout_cycles, 4096)); in gpmi_nfc_compute_timings()
899 * (tREA + 4000 - tRP) * 8 in gpmi_nfc_compute_timings()
900 * RDN_DELAY = ----------------------- in gpmi_nfc_compute_timings()
912 sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8; in gpmi_nfc_compute_timings()
918 hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel); in gpmi_nfc_compute_timings()
920 hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) | in gpmi_nfc_compute_timings()
928 struct gpmi_nfc_hardware_timing *hw = &this->hw; in gpmi_nfc_apply_timings()
929 struct resources *r = &this->resources; in gpmi_nfc_apply_timings()
930 void __iomem *gpmi_regs = r->gpmi_regs; in gpmi_nfc_apply_timings()
939 clk_disable_unprepare(r->clock[0]); in gpmi_nfc_apply_timings()
941 ret = clk_set_rate(r->clock[0], hw->clk_rate); in gpmi_nfc_apply_timings()
943 dev_err(this->dev, "cannot set clock rate to %lu Hz: %d\n", hw->clk_rate, ret); in gpmi_nfc_apply_timings()
948 ret = clk_prepare_enable(r->clock[0]); in gpmi_nfc_apply_timings()
953 writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0); in gpmi_nfc_apply_timings()
954 writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1); in gpmi_nfc_apply_timings()
961 writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_nfc_apply_timings()
964 dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64; in gpmi_nfc_apply_timings()
981 /* Retrieve required NAND timings */ in gpmi_setup_interface()
987 if (sdr->tRC_min <= 25000 && !this->devdata->support_edo_timing) in gpmi_setup_interface()
988 return -ENOTSUPP; in gpmi_setup_interface()
999 this->hw.must_apply_timings = true; in gpmi_setup_interface()
1007 struct resources *r = &this->resources; in gpmi_clear_bch()
1008 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR); in gpmi_clear_bch()
1013 /* We use the DMA channel 0 to access all the nand chips. */ in get_dma_chan()
1014 return this->dma_chans[0]; in get_dma_chan()
1017 /* This will be called after the DMA operation is finished. */
1021 struct completion *dma_c = &this->dma_done; in dma_irq_callback()
1031 complete(&this->bch_done); in bch_irq()
1038 * raw_len is the length to read/write including bch data which in gpmi_raw_len_to_len()
1041 if (this->bch) in gpmi_raw_len_to_len()
1042 return ALIGN_DOWN(raw_len, this->bch_geometry.eccn_chunk_size); in gpmi_raw_len_to_len()
1058 ret = dma_map_sg(this->dev, sgl, 1, dr); in prepare_data_dma()
1067 sg_init_one(sgl, this->data_buffer_dma, len); in prepare_data_dma()
1069 if (dr == DMA_TO_DEVICE && buf != this->data_buffer_dma) in prepare_data_dma()
1070 memcpy(this->data_buffer_dma, buf, len); in prepare_data_dma()
1072 dma_map_sg(this->dev, sgl, 1, dr); in prepare_data_dma()
1095 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_ecc()
1098 return -ERANGE; in gpmi_ooblayout_ecc()
1100 oobregion->offset = 0; in gpmi_ooblayout_ecc()
1101 oobregion->length = geo->page_size - mtd->writesize; in gpmi_ooblayout_ecc()
1111 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_free()
1114 return -ERANGE; in gpmi_ooblayout_free()
1117 if (geo->page_size < mtd->writesize + mtd->oobsize) { in gpmi_ooblayout_free()
1118 oobregion->offset = geo->page_size - mtd->writesize; in gpmi_ooblayout_free()
1119 oobregion->length = mtd->oobsize - oobregion->offset; in gpmi_ooblayout_free()
1202 struct platform_device *pdev = this->pdev; in acquire_register_block()
1203 struct resources *res = &this->resources; in acquire_register_block()
1211 res->gpmi_regs = p; in acquire_register_block()
1213 res->bch_regs = p; in acquire_register_block()
1215 dev_err(this->dev, "unknown resource name : %s\n", res_name); in acquire_register_block()
1222 struct platform_device *pdev = this->pdev; in acquire_bch_irq()
1230 err = devm_request_irq(this->dev, err, irq_h, 0, res_name, this); in acquire_bch_irq()
1232 dev_err(this->dev, "error requesting BCH IRQ\n"); in acquire_bch_irq()
1241 if (this->dma_chans[i]) { in release_dma_channels()
1242 dma_release_channel(this->dma_chans[i]); in release_dma_channels()
1243 this->dma_chans[i] = NULL; in release_dma_channels()
1249 struct platform_device *pdev = this->pdev; in acquire_dma_channels()
1254 dma_chan = dma_request_chan(&pdev->dev, "rx-tx"); in acquire_dma_channels()
1256 ret = dev_err_probe(this->dev, PTR_ERR(dma_chan), in acquire_dma_channels()
1260 this->dma_chans[0] = dma_chan; in acquire_dma_channels()
1268 struct resources *r = &this->resources; in gpmi_get_clks()
1272 for (i = 0; i < this->devdata->clks_count; i++) { in gpmi_get_clks()
1273 clk = devm_clk_get(this->dev, this->devdata->clks[i]); in gpmi_get_clks()
1279 r->clock[i] = clk; in gpmi_get_clks()
1285 dev_dbg(this->dev, "failed in finding the clocks.\n"); in gpmi_get_clks()
1327 struct device *dev = this->dev; in gpmi_free_dma_buffer()
1328 struct bch_geometry *geo = &this->bch_geometry; in gpmi_free_dma_buffer()
1330 if (this->auxiliary_virt && virt_addr_valid(this->auxiliary_virt)) in gpmi_free_dma_buffer()
1331 dma_free_coherent(dev, geo->auxiliary_size, in gpmi_free_dma_buffer()
1332 this->auxiliary_virt, in gpmi_free_dma_buffer()
1333 this->auxiliary_phys); in gpmi_free_dma_buffer()
1334 kfree(this->data_buffer_dma); in gpmi_free_dma_buffer()
1335 kfree(this->raw_buffer); in gpmi_free_dma_buffer()
1337 this->data_buffer_dma = NULL; in gpmi_free_dma_buffer()
1338 this->raw_buffer = NULL; in gpmi_free_dma_buffer()
1344 struct bch_geometry *geo = &this->bch_geometry; in gpmi_alloc_dma_buffer()
1345 struct device *dev = this->dev; in gpmi_alloc_dma_buffer()
1346 struct mtd_info *mtd = nand_to_mtd(&this->nand); in gpmi_alloc_dma_buffer()
1352 * is called before the NAND identification; and we allocate a in gpmi_alloc_dma_buffer()
1353 * buffer of the real NAND page size when the gpmi_alloc_dma_buffer in gpmi_alloc_dma_buffer()
1354 * is called after. in gpmi_alloc_dma_buffer()
1356 this->data_buffer_dma = kzalloc(mtd->writesize ?: PAGE_SIZE, in gpmi_alloc_dma_buffer()
1358 if (this->data_buffer_dma == NULL) in gpmi_alloc_dma_buffer()
1361 this->auxiliary_virt = dma_alloc_coherent(dev, geo->auxiliary_size, in gpmi_alloc_dma_buffer()
1362 &this->auxiliary_phys, GFP_DMA); in gpmi_alloc_dma_buffer()
1363 if (!this->auxiliary_virt) in gpmi_alloc_dma_buffer()
1366 this->raw_buffer = kzalloc((mtd->writesize ?: PAGE_SIZE) + mtd->oobsize, GFP_KERNEL); in gpmi_alloc_dma_buffer()
1367 if (!this->raw_buffer) in gpmi_alloc_dma_buffer()
1374 return -ENOMEM; in gpmi_alloc_dma_buffer()
1385 struct bch_geometry *nfc_geo = &this->bch_geometry; in block_mark_swapping()
1393 if (!this->swap_block_mark) in block_mark_swapping()
1400 bit = nfc_geo->block_mark_bit_offset; in block_mark_swapping()
1401 p = payload + nfc_geo->block_mark_byte_offset; in block_mark_swapping()
1410 from_data = (p[0] >> bit) | (p[1] << (8 - bit)); in block_mark_swapping()
1418 mask = (0x1 << bit) - 1; in block_mark_swapping()
1422 p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); in block_mark_swapping()
1429 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_count_bitflips()
1436 status = this->auxiliary_virt + ALIGN(meta, 4); in gpmi_count_bitflips()
1443 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_count_bitflips()
1444 u8 *eccbuf = this->raw_buffer; in gpmi_count_bitflips()
1450 offset = nfc_geo->metadata_size * 8; in gpmi_count_bitflips()
1451 offset += ((8 * nfc_geo->eccn_chunk_size) + eccbits) * (i + 1); in gpmi_count_bitflips()
1452 offset -= eccbits; in gpmi_count_bitflips()
1456 eccbytes -= offset; in gpmi_count_bitflips()
1462 * in-band data in the first and last byte of in gpmi_count_bitflips()
1463 * eccbuf. Set non-eccbits to one so that in gpmi_count_bitflips()
1468 eccbuf[0] |= GENMASK(bitoffset - 1, 0); in gpmi_count_bitflips()
1472 eccbuf[eccbytes - 1] |= GENMASK(7, bitoffset); in gpmi_count_bitflips()
1477 * nothing was written into this subpage the ECC is in gpmi_count_bitflips()
1481 * ecc_strength bitflips. If this is a page with random in gpmi_count_bitflips()
1488 buf + i * nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1489 nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1491 this->auxiliary_virt, in gpmi_count_bitflips()
1492 nfc_geo->metadata_size, in gpmi_count_bitflips()
1493 nfc_geo->ecc_strength); in gpmi_count_bitflips()
1496 buf + i * nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1497 nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1500 nfc_geo->ecc_strength); in gpmi_count_bitflips()
1506 mtd->ecc_stats.corrected += flips; in gpmi_count_bitflips()
1510 mtd->ecc_stats.failed++; in gpmi_count_bitflips()
1514 mtd->ecc_stats.corrected += *status; in gpmi_count_bitflips()
1523 struct bch_geometry *geo = &this->bch_geometry; in gpmi_bch_layout_std()
1524 unsigned int ecc_strength = geo->ecc_strength >> 1; in gpmi_bch_layout_std()
1525 unsigned int gf_len = geo->gf_len; in gpmi_bch_layout_std()
1526 unsigned int block0_size = geo->ecc0_chunk_size; in gpmi_bch_layout_std()
1527 unsigned int blockn_size = geo->eccn_chunk_size; in gpmi_bch_layout_std()
1529 this->bch_flashlayout0 = in gpmi_bch_layout_std()
1530 BF_BCH_FLASH0LAYOUT0_NBLOCKS(geo->ecc_chunk_count - 1) | in gpmi_bch_layout_std()
1531 BF_BCH_FLASH0LAYOUT0_META_SIZE(geo->metadata_size) | in gpmi_bch_layout_std()
1536 this->bch_flashlayout1 = in gpmi_bch_layout_std()
1537 BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(geo->page_size) | in gpmi_bch_layout_std()
1548 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ecc_read_page()
1553 this->bch = true; in gpmi_ecc_read_page()
1555 ret = nand_read_page_op(chip, page, 0, buf, geo->page_size); in gpmi_ecc_read_page()
1560 geo->ecc_chunk_count, in gpmi_ecc_read_page()
1561 geo->auxiliary_status_offset); in gpmi_ecc_read_page()
1564 block_mark_swapping(this, buf, this->auxiliary_virt); in gpmi_ecc_read_page()
1577 memset(chip->oob_poi, ~0, mtd->oobsize); in gpmi_ecc_read_page()
1578 chip->oob_poi[0] = ((uint8_t *)this->auxiliary_virt)[0]; in gpmi_ecc_read_page()
1589 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ecc_read_subpage()
1590 int size = chip->ecc.size; /* ECC chunk size */ in gpmi_ecc_read_subpage()
1600 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8; in gpmi_ecc_read_subpage()
1604 last = (offs + len - 1) / size; in gpmi_ecc_read_subpage()
1606 if (this->swap_block_mark) { in gpmi_ecc_read_subpage()
1609 * If this chunk is in the range of [first, last], in gpmi_ecc_read_subpage()
1612 * Marker to the metadata which is bound with the chunk 0. in gpmi_ecc_read_subpage()
1614 marker_pos = geo->block_mark_byte_offset / size; in gpmi_ecc_read_subpage()
1616 dev_dbg(this->dev, in gpmi_ecc_read_subpage()
1624 * if there is an ECC dedicate for meta: in gpmi_ecc_read_subpage()
1625 * - need to add an extra ECC size when calculating col and page_size, in gpmi_ecc_read_subpage()
1626 * if the meta size is NOT zero. in gpmi_ecc_read_subpage()
1627 * - ecc0_chunk size need to set to the same size as other chunks, in gpmi_ecc_read_subpage()
1628 * if the meta size is zero. in gpmi_ecc_read_subpage()
1631 meta = geo->metadata_size; in gpmi_ecc_read_subpage()
1633 if (geo->ecc_for_meta) in gpmi_ecc_read_subpage()
1643 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8; in gpmi_ecc_read_subpage()
1644 n = last - first + 1; in gpmi_ecc_read_subpage()
1646 if (geo->ecc_for_meta && meta) in gpmi_ecc_read_subpage()
1652 ecc_strength = geo->ecc_strength >> 1; in gpmi_ecc_read_subpage()
1654 this->bch_flashlayout0 = BF_BCH_FLASH0LAYOUT0_NBLOCKS( in gpmi_ecc_read_subpage()
1655 (geo->ecc_for_meta ? n : n - 1)) | in gpmi_ecc_read_subpage()
1658 BF_BCH_FLASH0LAYOUT0_GF(geo->gf_len, this) | in gpmi_ecc_read_subpage()
1659 BF_BCH_FLASH0LAYOUT0_DATA0_SIZE((geo->ecc_for_meta ? in gpmi_ecc_read_subpage()
1660 0 : geo->ecc0_chunk_size), this); in gpmi_ecc_read_subpage()
1662 this->bch_flashlayout1 = BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | in gpmi_ecc_read_subpage()
1664 BF_BCH_FLASH0LAYOUT1_GF(geo->gf_len, this) | in gpmi_ecc_read_subpage()
1665 BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(geo->eccn_chunk_size, this); in gpmi_ecc_read_subpage()
1667 this->bch = true; in gpmi_ecc_read_subpage()
1673 dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n", in gpmi_ecc_read_subpage()
1686 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_write_page()
1688 dev_dbg(this->dev, "ecc write page.\n"); in gpmi_ecc_write_page()
1691 this->bch = true; in gpmi_ecc_write_page()
1693 memcpy(this->auxiliary_virt, chip->oob_poi, nfc_geo->auxiliary_size); in gpmi_ecc_write_page()
1695 if (this->swap_block_mark) { in gpmi_ecc_write_page()
1700 memcpy(this->data_buffer_dma, buf, mtd->writesize); in gpmi_ecc_write_page()
1701 buf = this->data_buffer_dma; in gpmi_ecc_write_page()
1702 block_mark_swapping(this, this->data_buffer_dma, in gpmi_ecc_write_page()
1703 this->auxiliary_virt); in gpmi_ecc_write_page()
1706 return nand_prog_page_op(chip, page, 0, buf, nfc_geo->page_size); in gpmi_ecc_write_page()
1711 * block marks. This is the function where things are the most complicated, so
1712 * this is where we try to explain it all. All the other places refer back to
1723 * 3) ECC-based read operations return an OOB full of set bits (since we never
1724 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1735 * 1) Are we doing a "raw" read, or an ECC-based read?
1741 * | Raw | ECC-based |
1742 * -------------+-------------------------+-------------------------+
1748 * -------------+-------------------------+ return it in a buffer |
1756 * -------------+-------------------------+-------------------------+
1763 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1764 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1766 * ECC-based or raw view of the page is implicit in which function it calls
1767 * (there is a similar pair of ECC-based/raw functions for writing).
1776 memset(chip->oob_poi, ~0, mtd->oobsize); in gpmi_ecc_read_oob()
1779 ret = nand_read_page_op(chip, page, mtd->writesize, chip->oob_poi, in gpmi_ecc_read_oob()
1780 mtd->oobsize); in gpmi_ecc_read_oob()
1785 * Now, we want to make sure the block mark is correct. In the in gpmi_ecc_read_oob()
1786 * non-transcribing case (!GPMI_IS_MX23()), we already have it. in gpmi_ecc_read_oob()
1791 ret = nand_read_page_op(chip, page, 0, chip->oob_poi, 1); in gpmi_ecc_read_oob()
1807 return -EPERM; in gpmi_ecc_write_oob()
1810 return -EPERM; in gpmi_ecc_write_oob()
1812 return nand_prog_page_op(chip, page, mtd->writesize + of.offset, in gpmi_ecc_write_oob()
1813 chip->oob_poi + of.offset, of.length); in gpmi_ecc_write_oob()
1817 * This function reads a NAND page without involving the ECC engine (no HW
1819 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1823 * page into the provided buffers, which is why we're using nand_extract_bits().
1833 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_read_page_raw()
1834 int eccsize = nfc_geo->eccn_chunk_size; in gpmi_ecc_read_page_raw()
1835 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_ecc_read_page_raw()
1836 u8 *tmp_buf = this->raw_buffer; in gpmi_ecc_read_page_raw()
1840 uint8_t *oob = chip->oob_poi; in gpmi_ecc_read_page_raw()
1845 mtd->writesize + mtd->oobsize); in gpmi_ecc_read_page_raw()
1854 * is needed. in gpmi_ecc_read_page_raw()
1856 if (this->swap_block_mark) in gpmi_ecc_read_page_raw()
1857 swap(tmp_buf[0], tmp_buf[mtd->writesize]); in gpmi_ecc_read_page_raw()
1860 * Copy the metadata section into the oob buffer (this section is in gpmi_ecc_read_page_raw()
1864 memcpy(oob, tmp_buf, nfc_geo->metadata_size); in gpmi_ecc_read_page_raw()
1866 oob_bit_off = nfc_geo->metadata_size * 8; in gpmi_ecc_read_page_raw()
1870 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) { in gpmi_ecc_read_page_raw()
1877 if (step == nfc_geo->ecc_chunk_count - 1 && in gpmi_ecc_read_page_raw()
1879 eccbits += 8 - ((oob_bit_off + eccbits) % 8); in gpmi_ecc_read_page_raw()
1892 if (oob_byte_off < mtd->oobsize) in gpmi_ecc_read_page_raw()
1894 tmp_buf + mtd->writesize + oob_byte_off, in gpmi_ecc_read_page_raw()
1895 mtd->oobsize - oob_byte_off); in gpmi_ecc_read_page_raw()
1902 * This function writes a NAND page without involving the ECC engine (no HW
1904 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1908 * final page, which is why we're using nand_extract_bits().
1918 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_write_page_raw()
1919 int eccsize = nfc_geo->eccn_chunk_size; in gpmi_ecc_write_page_raw()
1920 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_ecc_write_page_raw()
1921 u8 *tmp_buf = this->raw_buffer; in gpmi_ecc_write_page_raw()
1922 uint8_t *oob = chip->oob_poi; in gpmi_ecc_write_page_raw()
1934 memset(tmp_buf, 0xff, mtd->writesize + mtd->oobsize); in gpmi_ecc_write_page_raw()
1940 memcpy(tmp_buf, oob, nfc_geo->metadata_size); in gpmi_ecc_write_page_raw()
1941 oob_bit_off = nfc_geo->metadata_size * 8; in gpmi_ecc_write_page_raw()
1945 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) { in gpmi_ecc_write_page_raw()
1952 if (step == nfc_geo->ecc_chunk_count - 1 && in gpmi_ecc_write_page_raw()
1954 eccbits += 8 - ((oob_bit_off + eccbits) % 8); in gpmi_ecc_write_page_raw()
1966 if (oob_required && oob_byte_off < mtd->oobsize) in gpmi_ecc_write_page_raw()
1967 memcpy(tmp_buf + mtd->writesize + oob_byte_off, in gpmi_ecc_write_page_raw()
1968 oob + oob_byte_off, mtd->oobsize - oob_byte_off); in gpmi_ecc_write_page_raw()
1975 * is needed. in gpmi_ecc_write_page_raw()
1977 if (this->swap_block_mark) in gpmi_ecc_write_page_raw()
1978 swap(tmp_buf[0], tmp_buf[mtd->writesize]); in gpmi_ecc_write_page_raw()
1981 mtd->writesize + mtd->oobsize); in gpmi_ecc_write_page_raw()
2002 chipnr = (int)(ofs >> chip->chip_shift); in gpmi_block_markbad()
2005 column = !GPMI_IS_MX23(this) ? mtd->writesize : 0; in gpmi_block_markbad()
2008 block_mark = this->data_buffer_dma; in gpmi_block_markbad()
2012 page = (int)(ofs >> chip->page_shift); in gpmi_block_markbad()
2023 struct boot_rom_geometry *geometry = &this->rom_geometry; in nand_boot_set_geometry()
2026 * Set the boot block stride size. in nand_boot_set_geometry()
2029 * that's where the ROM is going to get it. In fact, we don't have any in nand_boot_set_geometry()
2033 geometry->stride_size_in_pages = 64; in nand_boot_set_geometry()
2039 * that's where the ROM is going to get it. In fact, we don't have any in nand_boot_set_geometry()
2043 geometry->search_area_stride_exponent = 2; in nand_boot_set_geometry()
2050 struct boot_rom_geometry *rom_geo = &this->rom_geometry; in mx23_check_transcription_stamp()
2051 struct device *dev = this->dev; in mx23_check_transcription_stamp()
2052 struct nand_chip *chip = &this->nand; in mx23_check_transcription_stamp()
2061 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; in mx23_check_transcription_stamp()
2072 page = stride * rom_geo->stride_size_in_pages; in mx23_check_transcription_stamp()
2077 * Read the NCB fingerprint. The fingerprint is four bytes long in mx23_check_transcription_stamp()
2105 struct device *dev = this->dev; in mx23_write_transcription_stamp()
2106 struct boot_rom_geometry *rom_geo = &this->rom_geometry; in mx23_write_transcription_stamp()
2107 struct nand_chip *chip = &this->nand; in mx23_write_transcription_stamp()
2120 block_size_in_pages = mtd->erasesize / mtd->writesize; in mx23_write_transcription_stamp()
2121 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; in mx23_write_transcription_stamp()
2123 rom_geo->stride_size_in_pages; in mx23_write_transcription_stamp()
2125 (search_area_size_in_pages + (block_size_in_pages - 1)) / in mx23_write_transcription_stamp()
2147 memset(buffer, ~0, mtd->writesize); in mx23_write_transcription_stamp()
2154 page = stride * rom_geo->stride_size_in_pages; in mx23_write_transcription_stamp()
2159 status = chip->ecc.write_page_raw(chip, buffer, 0, page); in mx23_write_transcription_stamp()
2171 struct device *dev = this->dev; in mx23_boot_init()
2172 struct nand_chip *chip = &this->nand; in mx23_boot_init()
2186 * anything -- the block marks are already transcribed. in mx23_boot_init()
2197 /* Compute the number of blocks in the entire medium. */ in mx23_boot_init()
2198 block_count = nanddev_eraseblocks_per_target(&chip->base); in mx23_boot_init()
2201 * Loop over all the blocks in the medium, transcribing block marks as in mx23_boot_init()
2209 chipnr = block >> (chip->chip_shift - chip->phys_erase_shift); in mx23_boot_init()
2210 page = block << (chip->phys_erase_shift - chip->page_shift); in mx23_boot_init()
2211 byte = block << chip->phys_erase_shift; in mx23_boot_init()
2215 ret = nand_read_page_op(chip, page, mtd->writesize, &block_mark, in mx23_boot_init()
2223 * Check if the block is marked bad. If so, we need to mark it in mx23_boot_init()
2229 ret = chip->legacy.block_markbad(chip, byte); in mx23_boot_init()
2246 /* This is ROM arch-specific initilization before the BBT scanning. */ in nand_boot_init()
2259 /* Set up the NFC geometry which is used by BCH. */ in gpmi_set_geometry()
2262 dev_err(this->dev, "Error setting BCH geometry : %d\n", ret); in gpmi_set_geometry()
2272 struct nand_chip *chip = &this->nand; in gpmi_init_last()
2274 struct nand_ecc_ctrl *ecc = &chip->ecc; in gpmi_init_last()
2275 struct bch_geometry *bch_geo = &this->bch_geometry; in gpmi_init_last()
2278 /* Set up the medium geometry */ in gpmi_init_last()
2284 ecc->read_page = gpmi_ecc_read_page; in gpmi_init_last()
2285 ecc->write_page = gpmi_ecc_write_page; in gpmi_init_last()
2286 ecc->read_oob = gpmi_ecc_read_oob; in gpmi_init_last()
2287 ecc->write_oob = gpmi_ecc_write_oob; in gpmi_init_last()
2288 ecc->read_page_raw = gpmi_ecc_read_page_raw; in gpmi_init_last()
2289 ecc->write_page_raw = gpmi_ecc_write_page_raw; in gpmi_init_last()
2290 ecc->read_oob_raw = gpmi_ecc_read_oob_raw; in gpmi_init_last()
2291 ecc->write_oob_raw = gpmi_ecc_write_oob_raw; in gpmi_init_last()
2292 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in gpmi_init_last()
2293 ecc->size = bch_geo->eccn_chunk_size; in gpmi_init_last()
2294 ecc->strength = bch_geo->ecc_strength; in gpmi_init_last()
2299 * (1) the chip is imx6, and in gpmi_init_last()
2300 * (2) the size of the ECC parity is byte aligned. in gpmi_init_last()
2303 ((bch_geo->gf_len * bch_geo->ecc_strength) % 8) == 0) { in gpmi_init_last()
2304 ecc->read_subpage = gpmi_ecc_read_subpage; in gpmi_init_last()
2305 chip->options |= NAND_SUBPAGE_READ; in gpmi_init_last()
2316 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in gpmi_nand_attach_chip()
2317 chip->bbt_options |= NAND_BBT_NO_OOB; in gpmi_nand_attach_chip()
2319 if (of_property_read_bool(this->dev->of_node, in gpmi_nand_attach_chip()
2320 "fsl,no-blockmark-swap")) in gpmi_nand_attach_chip()
2321 this->swap_block_mark = false; in gpmi_nand_attach_chip()
2323 dev_dbg(this->dev, "Blockmark swapping %s\n", in gpmi_nand_attach_chip()
2324 str_enabled_disabled(this->swap_block_mark)); in gpmi_nand_attach_chip()
2330 chip->options |= NAND_SKIP_BBTSCAN; in gpmi_nand_attach_chip()
2337 struct gpmi_transfer *transfer = &this->transfers[this->ntransfers]; in get_next_transfer()
2339 this->ntransfers++; in get_next_transfer()
2341 if (this->ntransfers == GPMI_MAX_TRANSFERS) in get_next_transfer()
2353 int chip = this->nand.cur_cs; in gpmi_chain_command()
2375 transfer->cmdbuf[0] = cmd; in gpmi_chain_command()
2377 memcpy(&transfer->cmdbuf[1], addr, naddr); in gpmi_chain_command()
2379 sg_init_one(&transfer->sgl, transfer->cmdbuf, naddr + 1); in gpmi_chain_command()
2380 dma_map_sg(this->dev, &transfer->sgl, 1, DMA_TO_DEVICE); in gpmi_chain_command()
2382 transfer->direction = DMA_TO_DEVICE; in gpmi_chain_command()
2384 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, DMA_MEM_TO_DEV, in gpmi_chain_command()
2397 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_wait_ready()
2419 transfer->direction = DMA_FROM_DEVICE; in gpmi_chain_data_read()
2421 *direct = prepare_data_dma(this, buf, raw_len, &transfer->sgl, in gpmi_chain_data_read()
2426 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_data_read()
2431 if (this->bch) { in gpmi_chain_data_read()
2437 pio[4] = transfer->sgl.dma_address; in gpmi_chain_data_read()
2438 pio[5] = this->auxiliary_phys; in gpmi_chain_data_read()
2446 if (!this->bch) in gpmi_chain_data_read()
2447 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, in gpmi_chain_data_read()
2466 transfer->direction = DMA_TO_DEVICE; in gpmi_chain_data_write()
2468 prepare_data_dma(this, buf, raw_len, &transfer->sgl, DMA_TO_DEVICE); in gpmi_chain_data_write()
2472 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_data_write()
2477 if (this->bch) { in gpmi_chain_data_write()
2483 pio[4] = transfer->sgl.dma_address; in gpmi_chain_data_write()
2484 pio[5] = this->auxiliary_phys; in gpmi_chain_data_write()
2489 (this->bch ? MXS_DMA_CTRL_WAIT4END : 0)); in gpmi_chain_data_write()
2493 if (!this->bch) in gpmi_chain_data_write()
2494 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, in gpmi_chain_data_write()
2519 this->ntransfers = 0; in gpmi_nfc_exec_op()
2521 this->transfers[i].direction = DMA_NONE; in gpmi_nfc_exec_op()
2523 ret = pm_runtime_resume_and_get(this->dev); in gpmi_nfc_exec_op()
2528 * This driver currently supports only one NAND chip. Plus, dies share in gpmi_nfc_exec_op()
2533 if (this->hw.must_apply_timings) { in gpmi_nfc_exec_op()
2534 this->hw.must_apply_timings = false; in gpmi_nfc_exec_op()
2540 dev_dbg(this->dev, "%s: %d instructions\n", __func__, op->ninstrs); in gpmi_nfc_exec_op()
2542 for (i = 0; i < op->ninstrs; i++) { in gpmi_nfc_exec_op()
2543 instr = &op->instrs[i]; in gpmi_nfc_exec_op()
2547 switch (instr->type) { in gpmi_nfc_exec_op()
2552 cmd = instr->ctx.cmd.opcode; in gpmi_nfc_exec_op()
2558 if (i + 1 != op->ninstrs && in gpmi_nfc_exec_op()
2559 op->instrs[i + 1].type == NAND_OP_ADDR_INSTR) in gpmi_nfc_exec_op()
2566 desc = gpmi_chain_command(this, cmd, instr->ctx.addr.addrs, in gpmi_nfc_exec_op()
2567 instr->ctx.addr.naddrs); in gpmi_nfc_exec_op()
2570 buf_write = instr->ctx.data.buf.out; in gpmi_nfc_exec_op()
2571 buf_len = instr->ctx.data.len; in gpmi_nfc_exec_op()
2578 if (!instr->ctx.data.len) in gpmi_nfc_exec_op()
2580 buf_read = instr->ctx.data.buf.in; in gpmi_nfc_exec_op()
2581 buf_len = instr->ctx.data.len; in gpmi_nfc_exec_op()
2590 ret = -ENXIO; in gpmi_nfc_exec_op()
2595 dev_dbg(this->dev, "%s setup done\n", __func__); in gpmi_nfc_exec_op()
2598 dev_err(this->dev, "Multiple data instructions not supported\n"); in gpmi_nfc_exec_op()
2599 ret = -EINVAL; in gpmi_nfc_exec_op()
2603 if (this->bch) { in gpmi_nfc_exec_op()
2604 writel(this->bch_flashlayout0, in gpmi_nfc_exec_op()
2605 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT0); in gpmi_nfc_exec_op()
2606 writel(this->bch_flashlayout1, in gpmi_nfc_exec_op()
2607 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT1); in gpmi_nfc_exec_op()
2610 desc->callback = dma_irq_callback; in gpmi_nfc_exec_op()
2611 desc->callback_param = this; in gpmi_nfc_exec_op()
2612 dma_completion = &this->dma_done; in gpmi_nfc_exec_op()
2617 if (this->bch && buf_read) { in gpmi_nfc_exec_op()
2619 this->resources.bch_regs + HW_BCH_CTRL_SET); in gpmi_nfc_exec_op()
2620 bch_completion = &this->bch_done; in gpmi_nfc_exec_op()
2629 dev_err(this->dev, "DMA timeout, last DMA\n"); in gpmi_nfc_exec_op()
2631 ret = -ETIMEDOUT; in gpmi_nfc_exec_op()
2635 if (this->bch && buf_read) { in gpmi_nfc_exec_op()
2638 dev_err(this->dev, "BCH timeout, last DMA\n"); in gpmi_nfc_exec_op()
2640 ret = -ETIMEDOUT; in gpmi_nfc_exec_op()
2646 this->resources.bch_regs + HW_BCH_CTRL_CLR); in gpmi_nfc_exec_op()
2652 for (i = 0; i < this->ntransfers; i++) { in gpmi_nfc_exec_op()
2653 struct gpmi_transfer *transfer = &this->transfers[i]; in gpmi_nfc_exec_op()
2655 if (transfer->direction != DMA_NONE) in gpmi_nfc_exec_op()
2656 dma_unmap_sg(this->dev, &transfer->sgl, 1, in gpmi_nfc_exec_op()
2657 transfer->direction); in gpmi_nfc_exec_op()
2661 memcpy(buf_read, this->data_buffer_dma, in gpmi_nfc_exec_op()
2664 this->bch = false; in gpmi_nfc_exec_op()
2667 pm_runtime_mark_last_busy(this->dev); in gpmi_nfc_exec_op()
2668 pm_runtime_put_autosuspend(this->dev); in gpmi_nfc_exec_op()
2681 struct nand_chip *chip = &this->nand; in gpmi_nand_init()
2686 mtd->name = "gpmi-nand"; in gpmi_nand_init()
2687 mtd->dev.parent = this->dev; in gpmi_nand_init()
2689 /* init the nand_chip{}, we don't support a 16-bit NAND Flash bus. */ in gpmi_nand_init()
2691 nand_set_flash_node(chip, this->pdev->dev.of_node); in gpmi_nand_init()
2692 chip->legacy.block_markbad = gpmi_block_markbad; in gpmi_nand_init()
2693 chip->badblock_pattern = &gpmi_bbt_descr; in gpmi_nand_init()
2694 chip->options |= NAND_NO_SUBPAGE_WRITE; in gpmi_nand_init()
2697 this->swap_block_mark = !GPMI_IS_MX23(this); in gpmi_nand_init()
2703 this->bch_geometry.payload_size = 1024; in gpmi_nand_init()
2704 this->bch_geometry.auxiliary_size = 128; in gpmi_nand_init()
2709 nand_controller_init(&this->base); in gpmi_nand_init()
2710 this->base.ops = &gpmi_nand_controller_ops; in gpmi_nand_init()
2711 chip->controller = &this->base; in gpmi_nand_init()
2737 { .compatible = "fsl,imx23-gpmi-nand", .data = &gpmi_devdata_imx23, },
2738 { .compatible = "fsl,imx28-gpmi-nand", .data = &gpmi_devdata_imx28, },
2739 { .compatible = "fsl,imx6q-gpmi-nand", .data = &gpmi_devdata_imx6q, },
2740 { .compatible = "fsl,imx6sx-gpmi-nand", .data = &gpmi_devdata_imx6sx, },
2741 { .compatible = "fsl,imx7d-gpmi-nand", .data = &gpmi_devdata_imx7d,},
2742 { .compatible = "fsl,imx8qxp-gpmi-nand", .data = &gpmi_devdata_imx8qxp, },
2752 this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL); in gpmi_nand_probe()
2754 return -ENOMEM; in gpmi_nand_probe()
2756 this->devdata = of_device_get_match_data(&pdev->dev); in gpmi_nand_probe()
2758 this->pdev = pdev; in gpmi_nand_probe()
2759 this->dev = &pdev->dev; in gpmi_nand_probe()
2765 pm_runtime_enable(&pdev->dev); in gpmi_nand_probe()
2766 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); in gpmi_nand_probe()
2767 pm_runtime_use_autosuspend(&pdev->dev); in gpmi_nand_probe()
2777 dev_info(this->dev, "driver registered.\n"); in gpmi_nand_probe()
2782 pm_runtime_dont_use_autosuspend(&pdev->dev); in gpmi_nand_probe()
2783 pm_runtime_disable(&pdev->dev); in gpmi_nand_probe()
2793 struct nand_chip *chip = &this->nand; in gpmi_nand_remove()
2801 pm_runtime_dont_use_autosuspend(&pdev->dev); in gpmi_nand_remove()
2802 pm_runtime_disable(&pdev->dev); in gpmi_nand_remove()
2822 dev_err(this->dev, "Error in resume %d\n", ret); in gpmi_pm_resume()
2828 /* re-init the GPMI registers */ in gpmi_pm_resume()
2831 dev_err(this->dev, "Error setting GPMI : %d\n", ret); in gpmi_pm_resume()
2836 if (this->hw.clk_rate) in gpmi_pm_resume()
2837 this->hw.must_apply_timings = true; in gpmi_pm_resume()
2839 /* re-init the BCH registers */ in gpmi_pm_resume()
2842 dev_err(this->dev, "Error setting BCH : %d\n", ret); in gpmi_pm_resume()
2881 .name = "gpmi-nand",
2891 MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");