drivers/irqchip/irq-renesas-rzv2h.c

1 // SPDX-License-Identifier: GPL-2.0
5  * Based on irq-renesas-rzg2l.c
12 #include <linux/bitfield.h>
71 		ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
77 		BIT((_field_width) - 1) << ((n) * (_field_width)); \
93  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
97  * @field_width:	TSSR field width
107  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
122 	return data->domain->host_data;  in irq_data_to_priv()
132 	scoped_guard(raw_spinlock, &priv->lock) {  in rzv2h_icu_eoi()
134 			tintirq_nr = hw_irq - ICU_TINT_START;  in rzv2h_icu_eoi()
137 				writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);  in rzv2h_icu_eoi()
139 			tintirq_nr = hw_irq - ICU_IRQ_START;  in rzv2h_icu_eoi()
142 				writel_relaxed(bit, priv->base + ICU_ISCLR);  in rzv2h_icu_eoi()
144 			writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);  in rzv2h_icu_eoi()
161 	tint_nr = hw_irq - ICU_TINT_START;  in rzv2h_tint_irq_endisable()
162 	nr_tint = 32 / priv->info->field_width;  in rzv2h_tint_irq_endisable()
166 	guard(raw_spinlock)(&priv->lock);  in rzv2h_tint_irq_endisable()
167 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));  in rzv2h_tint_irq_endisable()
169 		tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width);  in rzv2h_tint_irq_endisable()
171 		tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);  in rzv2h_tint_irq_endisable()
172 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));  in rzv2h_tint_irq_endisable()
180 	writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);  in rzv2h_tint_irq_endisable()
198 	u32 sense;  in rzv2h_nmi_set_type()  local
202 		sense = ICU_NMI_EDGE_FALLING;  in rzv2h_nmi_set_type()
206 		sense = ICU_NMI_EDGE_RISING;  in rzv2h_nmi_set_type()
210 		return -EINVAL;  in rzv2h_nmi_set_type()
213 	writel_relaxed(sense, priv->base + ICU_NITSR);  in rzv2h_nmi_set_type()
220 	unsigned int irq_nr = hwirq - ICU_IRQ_START;  in rzv2h_clear_irq_int()
224 	isctr = readl_relaxed(priv->base + ICU_ISCTR);  in rzv2h_clear_irq_int()
225 	iitsr = readl_relaxed(priv->base + ICU_IITSR);  in rzv2h_clear_irq_int()
230 	 * interrupt signal is de-asserted by the source of the interrupt request, therefore clear  in rzv2h_clear_irq_int()
234 		writel_relaxed(bit, priv->base + ICU_ISCLR);  in rzv2h_clear_irq_int()
241 	u32 irq_nr = hwirq - ICU_IRQ_START;  in rzv2h_irq_set_type()
242 	u32 iitsr, sense;  in rzv2h_irq_set_type()  local
246 		sense = ICU_IRQ_LEVEL_LOW;  in rzv2h_irq_set_type()
250 		sense = ICU_IRQ_EDGE_FALLING;  in rzv2h_irq_set_type()
254 		sense = ICU_IRQ_EDGE_RISING;  in rzv2h_irq_set_type()
258 		sense = ICU_IRQ_EDGE_BOTH;  in rzv2h_irq_set_type()
262 		return -EINVAL;  in rzv2h_irq_set_type()
265 	guard(raw_spinlock)(&priv->lock);  in rzv2h_irq_set_type()
266 	iitsr = readl_relaxed(priv->base + ICU_IITSR);  in rzv2h_irq_set_type()
268 	iitsr |= ICU_IITSR_IITSEL_PREP(sense, irq_nr);  in rzv2h_irq_set_type()
270 	writel_relaxed(iitsr, priv->base + ICU_IITSR);  in rzv2h_irq_set_type()
277 	unsigned int tint_nr = hwirq - ICU_TINT_START;  in rzv2h_clear_tint_int()
283 	tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);  in rzv2h_clear_tint_int()
284 	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));  in rzv2h_clear_tint_int()
293 		writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);  in rzv2h_clear_tint_int()
302 	u32 tint, sense;  in rzv2h_tint_set_type()  local
308 		sense = ICU_TINT_LEVEL_LOW;  in rzv2h_tint_set_type()
312 		sense = ICU_TINT_LEVEL_HIGH;  in rzv2h_tint_set_type()
316 		sense = ICU_TINT_EDGE_RISING;  in rzv2h_tint_set_type()
320 		sense = ICU_TINT_EDGE_FALLING;  in rzv2h_tint_set_type()
324 		return -EINVAL;  in rzv2h_tint_set_type()
329 	if (tint > priv->info->max_tssel)  in rzv2h_tint_set_type()
330 		return -EINVAL;  in rzv2h_tint_set_type()
332 	if (priv->info->tssel_lut)  in rzv2h_tint_set_type()
333 		tint = priv->info->tssel_lut[tint];  in rzv2h_tint_set_type()
336 	tint_nr = hwirq - ICU_TINT_START;  in rzv2h_tint_set_type()
338 	nr_tint = 32 / priv->info->field_width;  in rzv2h_tint_set_type()
341 	tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width);  in rzv2h_tint_set_type()
346 	guard(raw_spinlock)(&priv->lock);  in rzv2h_tint_set_type()
348 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
349 	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);  in rzv2h_tint_set_type()
350 	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);  in rzv2h_tint_set_type()
352 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
354 	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));  in rzv2h_tint_set_type()
356 	titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);  in rzv2h_tint_set_type()
358 	writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));  in rzv2h_tint_set_type()
362 	writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));  in rzv2h_tint_set_type()
386 	.name			= "rzv2h-icu",
403 	struct rzv2h_icu_priv *priv = domain->host_data;  in rzv2h_icu_alloc()
415 	 * fwspec->param[0].  in rzv2h_icu_alloc()
416 	 * hwirq is embedded in bits 0-15.  in rzv2h_icu_alloc()
417 	 * TINT is embedded in bits 16-31.  in rzv2h_icu_alloc()
424 			return -EINVAL;  in rzv2h_icu_alloc()
427 	if (hwirq > (ICU_NUM_IRQ - 1))  in rzv2h_icu_alloc()
428 		return -EINVAL;  in rzv2h_icu_alloc()
435 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);  in rzv2h_icu_alloc()
455 		of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);  in rzv2h_icu_parse_interrupts()
477 		return -ENODEV;  in rzv2h_icu_init_common()
479 	ret = devm_add_action_or_reset(&pdev->dev, rzv2h_icu_put_device,  in rzv2h_icu_init_common()
480 				       &pdev->dev);  in rzv2h_icu_init_common()
486 		dev_err(&pdev->dev, "cannot find parent domain\n");  in rzv2h_icu_init_common()
487 		return -ENODEV;  in rzv2h_icu_init_common()
490 	rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);  in rzv2h_icu_init_common()
492 		return -ENOMEM;  in rzv2h_icu_init_common()
494 	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);  in rzv2h_icu_init_common()
495 	if (IS_ERR(rzv2h_icu_data->base))  in rzv2h_icu_init_common()
496 		return PTR_ERR(rzv2h_icu_data->base);  in rzv2h_icu_init_common()
500 		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);  in rzv2h_icu_init_common()
504 	resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);  in rzv2h_icu_init_common()
507 		dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret);  in rzv2h_icu_init_common()
511 	ret = devm_pm_runtime_enable(&pdev->dev);  in rzv2h_icu_init_common()
513 		dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret);  in rzv2h_icu_init_common()
517 	ret = pm_runtime_resume_and_get(&pdev->dev);  in rzv2h_icu_init_common()
519 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);  in rzv2h_icu_init_common()
523 	raw_spin_lock_init(&rzv2h_icu_data->lock);  in rzv2h_icu_init_common()
528 		dev_err(&pdev->dev, "failed to add irq domain\n");  in rzv2h_icu_init_common()
529 		ret = -ENOMEM;  in rzv2h_icu_init_common()
533 	rzv2h_icu_data->info = hw_info;  in rzv2h_icu_init_common()
537 	 * positive. We still need &pdev->dev after successfully returning from this function.  in rzv2h_icu_init_common()
542 	pm_runtime_put(&pdev->dev);  in rzv2h_icu_init_common()
547 /* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
549 	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
550 	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
551 	111, 112,				/* P20-P21 */
552 	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
553 	105, 106, 107, 108, 109, 110,		/* P40-P45 */
554 	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
555 	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
556 	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
557 	135, 136, 137, 138, 139, 140,		/* P80-P85 */
558 	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
559 	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
560 	59, 60,	61,				/* PC0-PC2 */
561 	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
562 	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
563 	78, 79, 80,				/* PF0-PF2 */
564 	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
565 	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
566 	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
567 	39, 40, 41, 42,				/* PK0-PK3 */
568 	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
569 	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
570 	0, 1, 2, 3				/* PS0-PS3 */
597 IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
598 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)