Lines Matching +full:back +full:- +full:to +full:- +full:back
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Digital to Analog converter driver, High Speed version
20 #include "ad3552r-hs.h"
29 * access to both the regions.
31 * Due to the fact that ad3541/2r do not implement QSPI, for proper device
35 * DAC appropriately, together with the backend API to configure the bus mode
38 * Also, important to note that none of the three modes allow to read in DDR.
40 * In non-buffering operations, mode is set to simple SPI SDR for all primary
41 * and secondary region r/w accesses, to avoid to switch the mode each time DAC
42 * register is accessed (raw accesses, r/w), and to be able to dump registers
51 struct iio_backend *back; member
63 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
65 return st->data->bus_reg_read(st->back, reg, val, xfer_size); in ad3552r_hs_reg_read()
80 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); in ad3552r_hs_update_reg_bits()
89 int ch = chan->channel; in ad3552r_hs_read_raw()
99 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * in ad3552r_hs_read_raw()
100 st->model_data->num_spi_data_lanes * 2, in ad3552r_hs_read_raw()
101 chan->scan_type.realbits); in ad3552r_hs_read_raw()
106 /* For RAW accesses, stay always in simple-spi. */ in ad3552r_hs_read_raw()
108 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), in ad3552r_hs_read_raw()
115 *val = st->ch_data[ch].scale_int; in ad3552r_hs_read_raw()
116 *val2 = st->ch_data[ch].scale_dec; in ad3552r_hs_read_raw()
119 *val = st->ch_data[ch].offset_int; in ad3552r_hs_read_raw()
120 *val2 = st->ch_data[ch].offset_dec; in ad3552r_hs_read_raw()
123 return -EINVAL; in ad3552r_hs_read_raw()
137 return -EBUSY; in ad3552r_hs_write_raw()
138 /* For RAW accesses, stay always in simple-spi. */ in ad3552r_hs_write_raw()
139 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_write_raw()
140 AD3552R_REG_ADDR_CH_DAC_16B(chan->channel), in ad3552r_hs_write_raw()
146 return -EINVAL; in ad3552r_hs_write_raw()
154 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_bus_io_mode_hs()
159 return st->data->bus_set_io_mode(st->back, bus_mode); in ad3552r_hs_set_bus_io_mode_hs()
170 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_target_io_mode_hs()
176 * Better to not use update here, since generally it is already in ad3552r_hs_set_target_io_mode_hs()
177 * set as DDR mode, and it's not possible to read in DDR mode. in ad3552r_hs_set_target_io_mode_hs()
179 return st->data->bus_reg_write(st->back, in ad3552r_hs_set_target_io_mode_hs()
194 switch (*indio_dev->active_scan_mask) { in ad3552r_hs_buffer_postenable()
196 st->single_channel = true; in ad3552r_hs_buffer_postenable()
201 st->single_channel = true; in ad3552r_hs_buffer_postenable()
206 st->single_channel = false; in ad3552r_hs_buffer_postenable()
211 return -EINVAL; in ad3552r_hs_buffer_postenable()
238 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
244 st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
245 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
247 st->config_d, 1); in ad3552r_hs_buffer_postenable()
251 ret = iio_backend_ddr_enable(st->back); in ad3552r_hs_buffer_postenable()
260 /* Set target to best high speed mode (D or QSPI). */ in ad3552r_hs_buffer_postenable()
265 /* Set bus to best high speed mode (D or QSPI). */ in ad3552r_hs_buffer_postenable()
274 ret = iio_backend_data_transfer_addr(st->back, val); in ad3552r_hs_buffer_postenable()
278 ret = iio_backend_data_format_set(st->back, 0, &fmt); in ad3552r_hs_buffer_postenable()
282 ret = iio_backend_data_stream_enable(st->back); in ad3552r_hs_buffer_postenable()
289 /* Back to simple SPI, not using update to avoid read. */ in ad3552r_hs_buffer_postenable()
290 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
296 * Back bus to simple SPI, this must be executed together with above in ad3552r_hs_buffer_postenable()
299 st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_postenable()
302 iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_postenable()
306 * Back to SDR. In DDR we cannot read, whatever the mode is, so not in ad3552r_hs_buffer_postenable()
309 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
310 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, in ad3552r_hs_buffer_postenable()
311 st->config_d, 1); in ad3552r_hs_buffer_postenable()
314 /* Back to single instruction mode, disabling loop. */ in ad3552r_hs_buffer_postenable()
315 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, in ad3552r_hs_buffer_postenable()
327 ret = iio_backend_data_stream_disable(st->back); in ad3552r_hs_buffer_predisable()
332 * Set us to simple SPI, even if still in ddr, so to be able to write in ad3552r_hs_buffer_predisable()
335 ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_predisable()
340 * Back to SDR (in DDR we cannot read, whatever the mode is, so not in ad3552r_hs_buffer_predisable()
343 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_predisable()
344 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_predisable()
346 st->config_d, 1); in ad3552r_hs_buffer_predisable()
350 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_predisable()
355 * Back to simple SPI for secondary region too now, so to be able to in ad3552r_hs_buffer_predisable()
364 /* Back to single instruction mode, disabling loop. */ in ad3552r_hs_buffer_predisable()
395 st->reset_gpio = devm_gpiod_get_optional(st->dev, in ad3552r_hs_reset()
397 if (IS_ERR(st->reset_gpio)) in ad3552r_hs_reset()
398 return PTR_ERR(st->reset_gpio); in ad3552r_hs_reset()
400 if (st->reset_gpio) { in ad3552r_hs_reset()
402 gpiod_set_value_cansleep(st->reset_gpio, 0); in ad3552r_hs_reset()
420 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
425 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
431 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
435 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
440 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
446 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
458 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), in ad3552r_hs_setup_custom_gain()
463 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), in ad3552r_hs_setup_custom_gain()
479 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_setup()
483 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
495 * Caching config_d, needed to restore it after streaming, in ad3552r_hs_setup()
496 * and also, to detect possible DDR read, that's not allowed. in ad3552r_hs_setup()
498 ret = st->data->bus_reg_read(st->back, in ad3552r_hs_setup()
500 &st->config_d, 1); in ad3552r_hs_setup()
515 if (id != st->model_data->chip_id) in ad3552r_hs_setup()
516 dev_warn(st->dev, in ad3552r_hs_setup()
518 id, st->model_data->chip_id); in ad3552r_hs_setup()
520 dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name); in ad3552r_hs_setup()
523 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, in ad3552r_hs_setup()
528 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
534 ret = iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL); in ad3552r_hs_setup()
538 ret = iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL); in ad3552r_hs_setup()
542 ret = ad3552r_get_ref_voltage(st->dev, &val); in ad3552r_hs_setup()
555 ret = ad3552r_get_drive_strength(st->dev, &val); in ad3552r_hs_setup()
557 st->config_d |= in ad3552r_hs_setup()
560 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
562 st->config_d, 1); in ad3552r_hs_setup()
567 device_for_each_child_node_scoped(st->dev, child) { in ad3552r_hs_setup()
570 return dev_err_probe(st->dev, ret, in ad3552r_hs_setup()
573 ret = ad3552r_get_output_range(st->dev, st->model_data, child, in ad3552r_hs_setup()
575 if (ret && ret != -ENOENT) in ad3552r_hs_setup()
577 if (ret == -ENOENT) { in ad3552r_hs_setup()
578 ret = ad3552r_get_custom_gain(st->dev, child, in ad3552r_hs_setup()
579 &st->ch_data[ch].p, in ad3552r_hs_setup()
580 &st->ch_data[ch].n, in ad3552r_hs_setup()
581 &st->ch_data[ch].rfb, in ad3552r_hs_setup()
582 &st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
586 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, in ad3552r_hs_setup()
587 st->ch_data[ch].n, in ad3552r_hs_setup()
588 st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
589 offset = abs(st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
591 st->ch_data[ch].range_override = 1; in ad3552r_hs_setup()
598 st->ch_data[ch].range = range; in ad3552r_hs_setup()
605 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); in ad3552r_hs_setup()
650 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); in ad3552r_hs_probe()
652 return -ENOMEM; in ad3552r_hs_probe()
655 st->dev = &pdev->dev; in ad3552r_hs_probe()
657 st->data = dev_get_platdata(st->dev); in ad3552r_hs_probe()
658 if (!st->data) in ad3552r_hs_probe()
659 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); in ad3552r_hs_probe()
661 st->back = devm_iio_backend_get(&pdev->dev, NULL); in ad3552r_hs_probe()
662 if (IS_ERR(st->back)) in ad3552r_hs_probe()
663 return PTR_ERR(st->back); in ad3552r_hs_probe()
665 ret = devm_iio_backend_enable(&pdev->dev, st->back); in ad3552r_hs_probe()
669 st->model_data = device_get_match_data(&pdev->dev); in ad3552r_hs_probe()
670 if (!st->model_data) in ad3552r_hs_probe()
671 return -ENODEV; in ad3552r_hs_probe()
673 indio_dev->name = "ad3552r"; in ad3552r_hs_probe()
674 indio_dev->modes = INDIO_DIRECT_MODE; in ad3552r_hs_probe()
675 indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops; in ad3552r_hs_probe()
676 indio_dev->channels = ad3552r_hs_channels; in ad3552r_hs_probe()
677 indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels); in ad3552r_hs_probe()
678 indio_dev->info = &ad3552r_hs_info; in ad3552r_hs_probe()
680 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); in ad3552r_hs_probe()
688 return devm_iio_device_register(&pdev->dev, indio_dev); in ad3552r_hs_probe()
702 .name = "ad3552r-hs",
711 MODULE_DESCRIPTION("AD3552R Driver - High Speed version");