Lines Matching +full:1 +full:st
59 static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val, in ad3552r_hs_reg_read() argument
63 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
65 return st->data->bus_reg_read(st->back, reg, val, xfer_size); in ad3552r_hs_reg_read()
68 static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg, in ad3552r_hs_update_reg_bits() argument
74 ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size); in ad3552r_hs_update_reg_bits()
80 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); in ad3552r_hs_update_reg_bits()
87 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_read_raw() local
99 *val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz * in ad3552r_hs_read_raw()
100 st->model_data->num_spi_data_lanes * 2, in ad3552r_hs_read_raw()
107 ret = ad3552r_hs_reg_read(st, in ad3552r_hs_read_raw()
115 *val = st->ch_data[ch].scale_int; in ad3552r_hs_read_raw()
116 *val2 = st->ch_data[ch].scale_dec; in ad3552r_hs_read_raw()
119 *val = st->ch_data[ch].offset_int; in ad3552r_hs_read_raw()
120 *val2 = st->ch_data[ch].offset_dec; in ad3552r_hs_read_raw()
131 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_write_raw() local
139 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_write_raw()
150 static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st) in ad3552r_hs_set_bus_io_mode_hs() argument
154 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_bus_io_mode_hs()
159 return st->data->bus_set_io_mode(st->back, bus_mode); in ad3552r_hs_set_bus_io_mode_hs()
162 static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st) in ad3552r_hs_set_target_io_mode_hs() argument
170 if (st->model_data->num_spi_data_lanes == 4) in ad3552r_hs_set_target_io_mode_hs()
179 return st->data->bus_reg_write(st->back, in ad3552r_hs_set_target_io_mode_hs()
183 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); in ad3552r_hs_set_target_io_mode_hs()
188 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_buffer_postenable() local
196 st->single_channel = true; in ad3552r_hs_buffer_postenable()
201 st->single_channel = true; in ad3552r_hs_buffer_postenable()
203 val = AD3552R_REG_ADDR_CH_DAC_16B(1); in ad3552r_hs_buffer_postenable()
206 st->single_channel = false; in ad3552r_hs_buffer_postenable()
208 val = AD3552R_REG_ADDR_CH_DAC_16B(1); in ad3552r_hs_buffer_postenable()
220 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_buffer_postenable()
222 AD3552R_MASK_SINGLE_INST, 0, 1); in ad3552r_hs_buffer_postenable()
231 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
234 1); in ad3552r_hs_buffer_postenable()
238 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
240 loop_len, 1); in ad3552r_hs_buffer_postenable()
244 st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
245 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_postenable()
247 st->config_d, 1); in ad3552r_hs_buffer_postenable()
251 ret = iio_backend_ddr_enable(st->back); in ad3552r_hs_buffer_postenable()
261 ret = ad3552r_hs_set_target_io_mode_hs(st); in ad3552r_hs_buffer_postenable()
266 ret = ad3552r_hs_set_bus_io_mode_hs(st); in ad3552r_hs_buffer_postenable()
274 ret = iio_backend_data_transfer_addr(st->back, val); in ad3552r_hs_buffer_postenable()
278 ret = iio_backend_data_format_set(st->back, 0, &fmt); in ad3552r_hs_buffer_postenable()
282 ret = iio_backend_data_stream_enable(st->back); in ad3552r_hs_buffer_postenable()
290 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_postenable()
293 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1); in ad3552r_hs_buffer_postenable()
299 st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_postenable()
302 iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_postenable()
309 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_postenable()
310 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D, in ad3552r_hs_buffer_postenable()
311 st->config_d, 1); in ad3552r_hs_buffer_postenable()
315 st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B, in ad3552r_hs_buffer_postenable()
317 AD3552R_MASK_SHORT_INSTRUCTION, 1); in ad3552r_hs_buffer_postenable()
324 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_buffer_predisable() local
327 ret = iio_backend_data_stream_disable(st->back); in ad3552r_hs_buffer_predisable()
335 ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI); in ad3552r_hs_buffer_predisable()
343 st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR; in ad3552r_hs_buffer_predisable()
344 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_buffer_predisable()
346 st->config_d, 1); in ad3552r_hs_buffer_predisable()
350 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_buffer_predisable()
358 ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER, in ad3552r_hs_buffer_predisable()
360 AD3552R_SPI, 1); in ad3552r_hs_buffer_predisable()
365 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_buffer_predisable()
368 AD3552R_MASK_SINGLE_INST, 1); in ad3552r_hs_buffer_predisable()
375 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st, in ad3552r_hs_set_output_range() argument
385 return ad3552r_hs_update_reg_bits(st, in ad3552r_hs_set_output_range()
388 val, 1); in ad3552r_hs_set_output_range()
391 static int ad3552r_hs_reset(struct ad3552r_hs_state *st) in ad3552r_hs_reset() argument
395 st->reset_gpio = devm_gpiod_get_optional(st->dev, in ad3552r_hs_reset()
397 if (IS_ERR(st->reset_gpio)) in ad3552r_hs_reset()
398 return PTR_ERR(st->reset_gpio); in ad3552r_hs_reset()
400 if (st->reset_gpio) { in ad3552r_hs_reset()
402 gpiod_set_value_cansleep(st->reset_gpio, 0); in ad3552r_hs_reset()
404 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_reset()
407 AD3552R_MASK_SOFTWARE_RESET, 1); in ad3552r_hs_reset()
416 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st) in ad3552r_hs_scratch_pad_test() argument
420 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
421 AD3552R_SCRATCH_PAD_TEST_VAL1, 1); in ad3552r_hs_scratch_pad_test()
425 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
426 &val, 1); in ad3552r_hs_scratch_pad_test()
431 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
435 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
436 AD3552R_SCRATCH_PAD_TEST_VAL2, 1); in ad3552r_hs_scratch_pad_test()
440 ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD, in ad3552r_hs_scratch_pad_test()
441 &val, 1); in ad3552r_hs_scratch_pad_test()
446 return dev_err_probe(st->dev, -EIO, in ad3552r_hs_scratch_pad_test()
453 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st, in ad3552r_hs_setup_custom_gain() argument
458 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch), in ad3552r_hs_setup_custom_gain()
459 offset, 1); in ad3552r_hs_setup_custom_gain()
463 return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch), in ad3552r_hs_setup_custom_gain()
464 gain, 1); in ad3552r_hs_setup_custom_gain()
467 static int ad3552r_hs_setup(struct ad3552r_hs_state *st) in ad3552r_hs_setup() argument
474 ret = ad3552r_hs_reset(st); in ad3552r_hs_setup()
479 ret = iio_backend_ddr_disable(st->back); in ad3552r_hs_setup()
483 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
486 AD3552R_MASK_SHORT_INSTRUCTION, 1); in ad3552r_hs_setup()
490 ret = ad3552r_hs_scratch_pad_test(st); in ad3552r_hs_setup()
498 ret = st->data->bus_reg_read(st->back, in ad3552r_hs_setup()
500 &st->config_d, 1); in ad3552r_hs_setup()
504 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1); in ad3552r_hs_setup()
510 ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1); in ad3552r_hs_setup()
515 if (id != st->model_data->chip_id) in ad3552r_hs_setup()
516 dev_warn(st->dev, in ad3552r_hs_setup()
518 id, st->model_data->chip_id); in ad3552r_hs_setup()
520 dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name); in ad3552r_hs_setup()
523 ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS, in ad3552r_hs_setup()
524 AD3552R_MASK_RESET_STATUS, 1); in ad3552r_hs_setup()
528 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
530 0, 1); in ad3552r_hs_setup()
534 ret = iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL); in ad3552r_hs_setup()
538 ret = iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL); in ad3552r_hs_setup()
542 ret = ad3552r_get_ref_voltage(st->dev, &val); in ad3552r_hs_setup()
548 ret = ad3552r_hs_update_reg_bits(st, in ad3552r_hs_setup()
551 val, 1); in ad3552r_hs_setup()
555 ret = ad3552r_get_drive_strength(st->dev, &val); in ad3552r_hs_setup()
557 st->config_d |= in ad3552r_hs_setup()
560 ret = st->data->bus_reg_write(st->back, in ad3552r_hs_setup()
562 st->config_d, 1); in ad3552r_hs_setup()
567 device_for_each_child_node_scoped(st->dev, child) { in ad3552r_hs_setup()
570 return dev_err_probe(st->dev, ret, in ad3552r_hs_setup()
573 ret = ad3552r_get_output_range(st->dev, st->model_data, child, in ad3552r_hs_setup()
578 ret = ad3552r_get_custom_gain(st->dev, child, in ad3552r_hs_setup()
579 &st->ch_data[ch].p, in ad3552r_hs_setup()
580 &st->ch_data[ch].n, in ad3552r_hs_setup()
581 &st->ch_data[ch].rfb, in ad3552r_hs_setup()
582 &st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
586 gain = ad3552r_calc_custom_gain(st->ch_data[ch].p, in ad3552r_hs_setup()
587 st->ch_data[ch].n, in ad3552r_hs_setup()
588 st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
589 offset = abs(st->ch_data[ch].gain_offset); in ad3552r_hs_setup()
591 st->ch_data[ch].range_override = 1; in ad3552r_hs_setup()
593 ret = ad3552r_hs_setup_custom_gain(st, ch, gain, in ad3552r_hs_setup()
598 st->ch_data[ch].range = range; in ad3552r_hs_setup()
600 ret = ad3552r_hs_set_output_range(st, ch, range); in ad3552r_hs_setup()
605 ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data); in ad3552r_hs_setup()
622 .output = 1, \
623 .indexed = 1, \
636 AD3552R_CHANNEL(1),
646 struct ad3552r_hs_state *st; in ad3552r_hs_probe() local
650 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); in ad3552r_hs_probe()
654 st = iio_priv(indio_dev); in ad3552r_hs_probe()
655 st->dev = &pdev->dev; in ad3552r_hs_probe()
657 st->data = dev_get_platdata(st->dev); in ad3552r_hs_probe()
658 if (!st->data) in ad3552r_hs_probe()
659 return dev_err_probe(st->dev, -ENODEV, "No platform data !"); in ad3552r_hs_probe()
661 st->back = devm_iio_backend_get(&pdev->dev, NULL); in ad3552r_hs_probe()
662 if (IS_ERR(st->back)) in ad3552r_hs_probe()
663 return PTR_ERR(st->back); in ad3552r_hs_probe()
665 ret = devm_iio_backend_enable(&pdev->dev, st->back); in ad3552r_hs_probe()
669 st->model_data = device_get_match_data(&pdev->dev); in ad3552r_hs_probe()
670 if (!st->model_data) in ad3552r_hs_probe()
680 ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev); in ad3552r_hs_probe()
684 ret = ad3552r_hs_setup(st); in ad3552r_hs_probe()