iio/adc/ad7944.c

33 	/* Normal mode max conversion time (t_{CONV}). */
35 	/* TURBO mode max conversion time (t_{CONV}). */
93 /* minimum CNV high time to trigger conversion */
122  * @_bits: The number of bits in the conversion result
199 	 * conversion, so place CNV low for t_QUIET to prepare for this.  in ad7944_3wire_cs_mode_init_msg()
205 	 * CS has to be high for full conversion time to avoid triggering the  in ad7944_3wire_cs_mode_init_msg()
236 	 * CS has to be high for full conversion time to avoid triggering the  in ad7944_4wire_mode_init_msg()
268 	 * to be high during the transfer to trigger the conversion.  in ad7944_chain_mode_init_msg()
274 	/* CNV has to be high for full conversion time before reading data. */  in ad7944_chain_mode_init_msg()
289  * during the conversion phase instead of the acquisition phase when reading
292  * high enough SCLK rate to read the sample during the conversion phase.
303 	 * conversion, so place CNV low for t_QUIET to prepare for this.  in ad7944_3wire_cs_mode_init_offload_msg()
307 	/* CNV has to be high for a minimum time to trigger conversion. */  in ad7944_3wire_cs_mode_init_offload_msg()
312 	/* Then we can read the previous sample during the conversion phase */  in ad7944_3wire_cs_mode_init_offload_msg()
330  * ad7944_convert_and_acquire - Perform a single conversion and acquisition
334  * Perform a conversion and acquisition of a single sample using the
337  * Upon successful return adc->sample.raw will contain the conversion result
345 	 * In 4-wire mode, the CNV line is held high for the entire conversion  in ad7944_convert_and_acquire()