Lines Matching full:gmu
24 /* Check that the GMU is idle */ in _a6xx_check_idle()
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
221 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1049 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
1055 /* Make sure the GMU keeps the GPU on while we set it up */ in hw_init()
1056 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1079 a6xx_sptprac_enable(gmu); in hw_init()
1199 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, in hw_init()
1236 /* Set up the CX GMU counter 0 to count busy ticks */ in hw_init()
1237 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in hw_init()
1240 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); in hw_init()
1241 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in hw_init()
1390 * Tell the GMU that we are done touching the GPU and it can start power in hw_init()
1393 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1395 if (a6xx_gpu->gmu.legacy) { in hw_init()
1396 /* Take the GMU out of its special boot mode */ in hw_init()
1397 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); in hw_init()
1409 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
1411 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_hw_init()
1427 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_recover() local
1469 reinit_completion(&gmu->pd_gate); in a6xx_recover()
1470 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); in a6xx_recover()
1471 dev_pm_genpd_synced_poweroff(gmu->cxpd); in a6xx_recover()
1480 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) in a6xx_recover()
1483 dev_pm_genpd_remove_notifier(gmu->cxpd); in a6xx_recover()
1607 return "GMU"; in a6xx_fault_block()
1695 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); in a6xx_fault_detect_irq()
1874 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_destroy()
1887 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_init()
2031 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_resume()
2033 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_resume()
2048 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_pm_resume() local
2057 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_pm_resume()
2069 pm_runtime_resume_and_get(gmu->dev); in a6xx_pm_resume()
2070 pm_runtime_resume_and_get(gmu->gxpd); in a6xx_pm_resume()
2077 a6xx_sptprac_enable(gmu); in a6xx_pm_resume()
2082 pm_runtime_put(gmu->gxpd); in a6xx_pm_resume()
2083 pm_runtime_put(gmu->dev); in a6xx_pm_resume()
2087 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_pm_resume()
2107 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_suspend()
2109 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_pm_suspend()
2126 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_pm_suspend() local
2133 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_pm_suspend()
2139 a6xx_sptprac_disable(gmu); in a6xx_pm_suspend()
2143 pm_runtime_put_sync(gmu->gxpd); in a6xx_pm_suspend()
2145 pm_runtime_put_sync(gmu->dev); in a6xx_pm_suspend()
2147 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_pm_suspend()
2163 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gmu_get_timestamp()
2166 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); in a6xx_gmu_get_timestamp()
2170 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); in a6xx_gmu_get_timestamp()
2172 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gmu_get_timestamp()
2224 busy_cycles = gmu_read64(&a6xx_gpu->gmu, in a6xx_gpu_busy()
2237 mutex_lock(&a6xx_gpu->gmu.lock); in a6xx_gpu_set_freq()
2239 mutex_unlock(&a6xx_gpu->gmu.lock); in a6xx_gpu_set_freq()
2477 mutex_init(&a6xx_gpu->gmu.lock); in a6xx_gpu_init()
2481 /* Check if there is a GMU phandle and set it up */ in a6xx_gpu_init()
2482 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); in a6xx_gpu_init()
2486 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); in a6xx_gpu_init()