Lines Matching +full:slice +full:- +full:per +full:- +full:line
1 // SPDX-License-Identifier: MIT
26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
50 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
59 int bpc = vdsc_cfg->bits_per_component; in intel_vdsc_set_min_max_qp()
62 vdsc_cfg->rc_range_params[buf].range_min_qp = in intel_vdsc_set_min_max_qp()
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
64 vdsc_cfg->rc_range_params[buf].range_max_qp = in intel_vdsc_set_min_max_qp()
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
71 return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low), in get_range_bpg_offset()
72 (bpp_low - bpp_high)); in get_range_bpg_offset()
76 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
82 * DSCParameterValuesVESA V1-2 spreadsheet).
87 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel); in calculate_rc_params()
88 int bpc = vdsc_cfg->bits_per_component; in calculate_rc_params()
89 int qp_bpc_modifier = (bpc - 8) * 2; in calculate_rc_params()
94 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
96 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; in calculate_rc_params()
98 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
100 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3; in calculate_rc_params()
101 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0, in calculate_rc_params()
102 uncompressed_bpg_rate - 3 * bpp); in calculate_rc_params()
106 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice in calculate_rc_params()
108 * -second_line_offset_adj is 512 as shown by empirical values to yield best chroma in calculate_rc_params()
109 * preservation in second line. in calculate_rc_params()
110 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded in calculate_rc_params()
111 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 in calculate_rc_params()
114 if (vdsc_cfg->native_420) { in calculate_rc_params()
115 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
116 vdsc_cfg->second_line_bpg_offset = 12; in calculate_rc_params()
118 vdsc_cfg->second_line_bpg_offset = in calculate_rc_params()
119 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
121 vdsc_cfg->second_line_offset_adj = 512; in calculate_rc_params()
122 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, in calculate_rc_params()
123 vdsc_cfg->slice_height - 1); in calculate_rc_params()
127 vdsc_cfg->initial_offset = 2048; in calculate_rc_params()
129 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
131 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
133 vdsc_cfg->initial_offset = 6144; in calculate_rc_params()
136 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); in calculate_rc_params()
138 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier; in calculate_rc_params()
139 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier; in calculate_rc_params()
141 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; in calculate_rc_params()
142 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; in calculate_rc_params()
144 if (vdsc_cfg->native_420) { in calculate_rc_params()
146 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 in calculate_rc_params()
149 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
152 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
155 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 in calculate_rc_params()
164 bpp_i = bpp - 8; in calculate_rc_params()
185 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
190 int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel); in calculate_rc_params()
193 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 in calculate_rc_params()
196 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
199 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
202 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 in calculate_rc_params()
211 bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1)); in calculate_rc_params()
233 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
242 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || in intel_dsc_slice_dimensions_valid()
243 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { in intel_dsc_slice_dimensions_valid()
244 if (vdsc_cfg->slice_height > 4095) in intel_dsc_slice_dimensions_valid()
245 return -EINVAL; in intel_dsc_slice_dimensions_valid()
246 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) in intel_dsc_slice_dimensions_valid()
247 return -EINVAL; in intel_dsc_slice_dimensions_valid()
248 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dsc_slice_dimensions_valid()
249 if (vdsc_cfg->slice_width % 2) in intel_dsc_slice_dimensions_valid()
250 return -EINVAL; in intel_dsc_slice_dimensions_valid()
251 if (vdsc_cfg->slice_height % 2) in intel_dsc_slice_dimensions_valid()
252 return -EINVAL; in intel_dsc_slice_dimensions_valid()
253 if (vdsc_cfg->slice_height > 4094) in intel_dsc_slice_dimensions_valid()
254 return -EINVAL; in intel_dsc_slice_dimensions_valid()
255 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) in intel_dsc_slice_dimensions_valid()
256 return -EINVAL; in intel_dsc_slice_dimensions_valid()
265 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
266 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in intel_dsc_compute_params()
270 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
271 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
272 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
277 drm_dbg_kms(display->drm, "Slice dimension requirements not met\n"); in intel_dsc_compute_params()
285 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && in intel_dsc_compute_params()
286 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; in intel_dsc_compute_params()
289 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dsc_compute_params()
290 vdsc_cfg->native_420 = true; in intel_dsc_compute_params()
292 vdsc_cfg->native_422 = false; in intel_dsc_compute_params()
293 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
295 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
297 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16; in intel_dsc_compute_params()
303 if (vdsc_cfg->native_420) in intel_dsc_compute_params()
304 vdsc_cfg->bits_per_pixel <<= 1; in intel_dsc_compute_params()
306 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
308 if (vdsc_cfg->bits_per_component < 8) { in intel_dsc_compute_params()
309 drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n", in intel_dsc_compute_params()
310 vdsc_cfg->bits_per_component); in intel_dsc_compute_params()
311 return -EINVAL; in intel_dsc_compute_params()
318 * upto uncompressed bpp-1, hence add calculations for all the rc in intel_dsc_compute_params()
326 (vdsc_cfg->bits_per_component == 8 || in intel_dsc_compute_params()
327 vdsc_cfg->bits_per_component == 10 || in intel_dsc_compute_params()
328 vdsc_cfg->bits_per_component == 12)) in intel_dsc_compute_params()
342 if (vdsc_cfg->bits_per_component <= 10) in intel_dsc_compute_params()
343 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in intel_dsc_compute_params()
345 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; in intel_dsc_compute_params()
348 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()
349 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
358 enum pipe pipe = crtc->pipe; in intel_dsc_power_domain()
364 * - ICL eDP/DSI transcoder in intel_dsc_power_domain()
365 * - Display version 12 (except RKL) pipe A in intel_dsc_power_domain()
371 if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake && in intel_dsc_power_domain()
382 return crtc_state->dsc.num_streams; in intel_dsc_get_vdsc_per_pipe()
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_get_pps_reg()
399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_get_pps_reg()
400 enum pipe pipe = crtc->pipe; in intel_dsc_get_pps_reg()
425 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); in intel_dsc_pps_write()
436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_pps_configure()
437 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
438 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_pps_configure()
439 enum pipe pipe = crtc->pipe; in intel_dsc_pps_configure()
449 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) | in intel_dsc_pps_configure()
450 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) | in intel_dsc_pps_configure()
451 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth); in intel_dsc_pps_configure()
452 if (vdsc_cfg->dsc_version_minor == 2) { in intel_dsc_pps_configure()
454 if (vdsc_cfg->native_420) in intel_dsc_pps_configure()
456 if (vdsc_cfg->native_422) in intel_dsc_pps_configure()
459 if (vdsc_cfg->block_pred_enable) in intel_dsc_pps_configure()
461 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()
463 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()
465 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()
470 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure()
474 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
475 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
479 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
480 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
484 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | in intel_dsc_pps_configure()
485 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); in intel_dsc_pps_configure()
489 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | in intel_dsc_pps_configure()
490 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); in intel_dsc_pps_configure()
494 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | in intel_dsc_pps_configure()
495 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | in intel_dsc_pps_configure()
496 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | in intel_dsc_pps_configure()
497 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); in intel_dsc_pps_configure()
501 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | in intel_dsc_pps_configure()
502 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); in intel_dsc_pps_configure()
506 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
507 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
511 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | in intel_dsc_pps_configure()
516 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
517 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
523 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
524 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
525 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
526 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
527 vdsc_cfg->slice_height); in intel_dsc_pps_configure()
532 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); in intel_dsc_pps_configure()
536 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | in intel_dsc_pps_configure()
537 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); in intel_dsc_pps_configure()
543 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) in intel_dsc_pps_configure()
545 (u32)(vdsc_cfg->rc_buf_thresh[i] << in intel_dsc_pps_configure()
595 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
597 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
599 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
693 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dsi_pps_write()
699 if (!crtc_state->dsc.compression_enable) in intel_dsc_dsi_pps_write()
704 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsc_dsi_pps_write()
705 dsi = intel_dsi->dsi_hosts[port]->device; in intel_dsc_dsi_pps_write()
716 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dp_pps_write()
719 if (!crtc_state->dsc.compression_enable) in intel_dsc_dp_pps_write()
722 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ in intel_dsc_dp_pps_write()
725 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ in intel_dsc_dp_pps_write()
728 dig_port->write_infoframe(encoder, crtc_state, in intel_dsc_dp_pps_write()
736 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; in dss_ctl1_reg()
742 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; in dss_ctl2_reg()
748 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_uncompressed_joiner_enable()
751 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { in intel_uncompressed_joiner_enable()
757 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), in intel_uncompressed_joiner_enable()
765 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_enable()
770 if (!crtc_state->dsc.compression_enable) in intel_dsc_enable()
786 if (crtc_state->joiner_pipes) { in intel_dsc_enable()
798 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); in intel_dsc_enable()
799 intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); in intel_dsc_enable()
805 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_dsc_disable()
808 if (old_crtc_state->dsc.compression_enable || in intel_dsc_disable()
809 old_crtc_state->joiner_pipes) { in intel_dsc_disable()
810 intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); in intel_dsc_disable()
811 intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); in intel_dsc_disable()
826 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); in intel_dsc_pps_read()
851 drm_WARN_ON(display->drm, !all_equal); in intel_dsc_pps_read_and_verify()
859 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_get_pps_config()
866 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); in intel_dsc_get_pps_config()
867 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); in intel_dsc_get_pps_config()
868 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; in intel_dsc_get_pps_config()
869 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; in intel_dsc_get_pps_config()
870 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; in intel_dsc_get_pps_config()
871 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE; in intel_dsc_get_pps_config()
872 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; in intel_dsc_get_pps_config()
873 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE; in intel_dsc_get_pps_config()
878 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); in intel_dsc_get_pps_config()
880 if (vdsc_cfg->native_420) in intel_dsc_get_pps_config()
881 vdsc_cfg->bits_per_pixel >>= 1; in intel_dsc_get_pps_config()
883 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel; in intel_dsc_get_pps_config()
888 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
889 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
894 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
895 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
900 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
901 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
906 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
907 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
912 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp); in intel_dsc_get_pps_config()
913 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
914 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); in intel_dsc_get_pps_config()
915 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp); in intel_dsc_get_pps_config()
920 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
921 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
926 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
927 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
932 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp); in intel_dsc_get_pps_config()
937 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); in intel_dsc_get_pps_config()
938 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); in intel_dsc_get_pps_config()
943 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); in intel_dsc_get_pps_config()
949 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
954 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
955 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp); in intel_dsc_get_pps_config()
962 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_get_config()
963 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_get_config()
980 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; in intel_dsc_get_config()
981 if (!crtc_state->dsc.compression_enable) in intel_dsc_get_config()
985 crtc_state->dsc.num_streams = 3; in intel_dsc_get_config()
987 crtc_state->dsc.num_streams = 2; in intel_dsc_get_config()
989 crtc_state->dsc.num_streams = 1; in intel_dsc_get_config()
1000 "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", in intel_vdsc_dump_state()
1001 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), in intel_vdsc_dump_state()
1002 crtc_state->dsc.slice_count, in intel_vdsc_dump_state()
1003 crtc_state->dsc.num_streams); in intel_vdsc_dump_state()
1009 if (!crtc_state->dsc.compression_enable) in intel_vdsc_state_dump()
1013 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); in intel_vdsc_state_dump()
1022 if (!crtc_state->dsc.compression_enable) in intel_vdsc_min_cdclk()
1032 min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances); in intel_vdsc_min_cdclk()
1034 if (crtc_state->joiner_pipes) { in intel_vdsc_min_cdclk()
1035 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); in intel_vdsc_min_cdclk()
1051 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * in intel_vdsc_min_cdclk()