49 	/* There's no pipe A DSC engine on ICL */  in is_pipe_dsc()
76  * We are using the method provided in DSC 1.2a C-Model in codec_main.c
77  * Above method use a common formula to derive values for any combination of DSC
105 	 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:  in calculate_rc_params()
265 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;  in intel_dsc_compute_params()
266 	u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);  in intel_dsc_compute_params()
272 					     pipe_config->dsc.slice_count);  in intel_dsc_compute_params()
282 	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0  in intel_dsc_compute_params()
297 	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;  in intel_dsc_compute_params()
300 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set  in intel_dsc_compute_params()
309 		drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",  in intel_dsc_compute_params()
382 	return crtc_state->dsc.num_streams;  in intel_dsc_get_vdsc_per_pipe()
437 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_pps_configure()
693 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_dsi_pps_write()
699 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_dsi_pps_write()
716 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_dp_pps_write()
719 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_dp_pps_write()
725 	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */  in intel_dsc_dp_pps_write()
751 	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {  in intel_uncompressed_joiner_enable()
770 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_enable()
808 	if (old_crtc_state->dsc.compression_enable ||  in intel_dsc_disable()
859 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_get_pps_config()
883 	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;  in intel_dsc_get_pps_config()
980 	crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;  in intel_dsc_get_config()
981 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_get_config()
985 		crtc_state->dsc.num_streams = 3;  in intel_dsc_get_config()
987 		crtc_state->dsc.num_streams = 2;  in intel_dsc_get_config()
989 		crtc_state->dsc.num_streams = 1;  in intel_dsc_get_config()
1000 			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",  in intel_vdsc_dump_state()
1001 			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),  in intel_vdsc_dump_state()
1002 			  crtc_state->dsc.slice_count,  in intel_vdsc_dump_state()
1003 			  crtc_state->dsc.num_streams);  in intel_vdsc_dump_state()
1009 	if (!crtc_state->dsc.compression_enable)  in intel_vdsc_state_dump()
1013 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);  in intel_vdsc_state_dump()
1022 	if (!crtc_state->dsc.compression_enable)  in intel_vdsc_min_cdclk()
1051 			(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *  in intel_vdsc_min_cdclk()