Lines Matching +full:write +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <sound/hdmi-codec.h>
25 #include <media/cec-notifier.h>
27 #include <dt-bindings/display/tda998x.h>
101 * write a given register, we need to make sure CURPAGE register is set
109 #define REG_CURPAGE 0xff /* write */
114 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
115 # define MAIN_CNTRL0_SR (1 << 0)
116 # define MAIN_CNTRL0_DECS (1 << 1)
117 # define MAIN_CNTRL0_DEHS (1 << 2)
118 # define MAIN_CNTRL0_CECS (1 << 3)
119 # define MAIN_CNTRL0_CEHS (1 << 4)
120 # define MAIN_CNTRL0_SCALER (1 << 7)
122 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
123 # define SOFTRESET_AUDIO (1 << 0)
124 # define SOFTRESET_I2C_MASTER (1 << 1)
125 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
126 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
127 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
128 # define I2C_MASTER_DIS_MM (1 << 0)
129 # define I2C_MASTER_DIS_FILT (1 << 1)
130 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
131 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
133 # define FEAT_POWERDOWN_CSC BIT(1)
134 # define FEAT_POWERDOWN_SPDIF (1 << 3)
135 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
136 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
137 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
138 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
139 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
140 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
141 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
142 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
143 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
144 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
145 # define VIP_CNTRL_0_MIRR_A (1 << 7)
147 # define VIP_CNTRL_0_MIRR_B (1 << 3)
149 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
150 # define VIP_CNTRL_1_MIRR_C (1 << 7)
152 # define VIP_CNTRL_1_MIRR_D (1 << 3)
154 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
155 # define VIP_CNTRL_2_MIRR_E (1 << 7)
157 # define VIP_CNTRL_2_MIRR_F (1 << 3)
159 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
160 # define VIP_CNTRL_3_X_TGL (1 << 0)
161 # define VIP_CNTRL_3_H_TGL (1 << 1)
162 # define VIP_CNTRL_3_V_TGL (1 << 2)
163 # define VIP_CNTRL_3_EMB (1 << 3)
164 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
165 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
166 # define VIP_CNTRL_3_DE_INT (1 << 6)
167 # define VIP_CNTRL_3_EDGE (1 << 7)
168 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
171 # define VIP_CNTRL_4_CCIR656 (1 << 4)
172 # define VIP_CNTRL_4_656_ALT (1 << 5)
173 # define VIP_CNTRL_4_TST_656 (1 << 6)
174 # define VIP_CNTRL_4_TST_PAT (1 << 7)
175 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
176 # define VIP_CNTRL_5_CKCASE (1 << 0)
177 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
178 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
181 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
182 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
184 # define MAT_CONTRL_MAT_BP (1 << 2)
185 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
186 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
187 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
188 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
189 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
190 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
191 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
192 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
193 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
194 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
195 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
196 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
197 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
198 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
199 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
200 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
201 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
202 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
203 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
204 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
205 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
206 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
207 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
208 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
209 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
210 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
211 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
212 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
213 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
214 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
215 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
216 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
217 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
218 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
219 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
220 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
221 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
222 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
223 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
224 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
225 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
226 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
227 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
228 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
229 # define TBG_CNTRL_0_DE_EXT (1 << 2)
230 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
231 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
232 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
233 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
234 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
235 # define TBG_CNTRL_1_H_TGL (1 << 0)
236 # define TBG_CNTRL_1_V_TGL (1 << 1)
237 # define TBG_CNTRL_1_TGL_EN (1 << 2)
238 # define TBG_CNTRL_1_X_EXT (1 << 3)
239 # define TBG_CNTRL_1_H_EXT (1 << 4)
240 # define TBG_CNTRL_1_V_EXT (1 << 5)
241 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
242 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
243 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
244 # define HVF_CNTRL_0_SM (1 << 7)
245 # define HVF_CNTRL_0_RWB (1 << 6)
248 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
249 # define HVF_CNTRL_1_FOR (1 << 0)
250 # define HVF_CNTRL_1_YUVBLK (1 << 1)
253 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
254 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
256 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
260 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
262 # define AIP_CLKSEL_AIP_I2S (1 << 3)
264 # define AIP_CLKSEL_FS_MCLK (1 << 0)
268 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
269 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
270 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
271 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
272 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
275 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
276 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
277 # define PLL_SERIAL_3_SRL_DE (1 << 2)
278 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
279 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
280 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
281 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
282 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
283 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
284 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
285 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
286 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
287 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
289 # define AUDIO_DIV_SERCLK_2 1
294 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
295 # define SEL_CLK_SEL_CLK1 (1 << 0)
296 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
297 # define SEL_CLK_ENA_SC_CLK (1 << 3)
298 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
304 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
305 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
306 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
307 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
308 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
312 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
313 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
314 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
315 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
316 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
320 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
321 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
322 # define AIP_CNTRL_0_SWAP (1 << 1)
323 # define AIP_CNTRL_0_LAYOUT (1 << 2)
324 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
325 # define AIP_CNTRL_0_RST_CTS (1 << 6)
326 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
328 # define CA_I2S_HBR_CHSTAT (1 << 6)
329 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
330 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
331 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
332 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
333 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
334 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
335 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
336 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
339 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
340 # define ENC_CNTRL_RST_ENC (1 << 0)
341 # define ENC_CNTRL_RST_SEL (1 << 1)
343 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
344 # define DIP_FLAGS_ACR (1 << 0)
345 # define DIP_FLAGS_GC (1 << 1)
346 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
347 # define DIP_IF_FLAGS_IF1 (1 << 1)
348 # define DIP_IF_FLAGS_IF2 (1 << 2)
349 # define DIP_IF_FLAGS_IF3 (1 << 3)
350 # define DIP_IF_FLAGS_IF4 (1 << 4)
351 # define DIP_IF_FLAGS_IF5 (1 << 5)
352 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
356 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
357 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
358 # define TX4_PD_RAM (1 << 1)
359 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
360 # define TX33_HDMI (1 << 1)
370 # define CEC_INTSTATUS_CEC (1 << 0)
371 # define CEC_INTSTATUS_HDMI (1 << 1)
378 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
379 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
380 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
381 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
382 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
383 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
386 # define CEC_RXSHPDINT_HPD BIT(1)
388 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
389 # define CEC_RXSHPDLEV_HPD (1 << 1)
391 #define REG_CEC_ENAMODS 0xff /* read/write */
392 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7)
393 # define CEC_ENAMODS_DIS_FRO (1 << 6)
394 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
395 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
396 # define CEC_ENAMODS_EN_HDMI (1 << 1)
397 # define CEC_ENAMODS_EN_CEC (1 << 0)
411 .addr = priv->cec_addr, in cec_write()
417 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); in cec_write()
419 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", in cec_write()
429 .addr = priv->cec_addr, in cec_read()
430 .len = 1, in cec_read()
433 .addr = priv->cec_addr, in cec_read()
435 .len = 1, in cec_read()
441 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); in cec_read()
443 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", in cec_read()
492 * and then pulse the IRQ line low for a 10ms ± 1% period.
496 struct gpio_desc *calib = priv->calib; in tda998x_cec_calibration()
498 mutex_lock(&priv->edid_mutex); in tda998x_cec_calibration()
499 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
500 disable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
501 gpiod_direction_output(calib, 1); in tda998x_cec_calibration()
507 gpiod_set_value(calib, 1); in tda998x_cec_calibration()
512 if (priv->hdmi->irq > 0) in tda998x_cec_calibration()
513 enable_irq(priv->hdmi->irq); in tda998x_cec_calibration()
514 mutex_unlock(&priv->edid_mutex); in tda998x_cec_calibration()
522 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); in tda998x_cec_hook_init()
524 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", in tda998x_cec_hook_init()
529 priv->calib = calib; in tda998x_cec_hook_init()
538 gpiod_put(priv->calib); in tda998x_cec_hook_exit()
539 priv->calib = NULL; in tda998x_cec_hook_exit()
562 if (REG2PAGE(reg) != priv->current_page) { in set_page()
563 struct i2c_client *client = priv->hdmi; in set_page()
569 dev_err(&client->dev, "%s %04x err %d\n", __func__, in set_page()
574 priv->current_page = REG2PAGE(reg); in set_page()
582 struct i2c_client *client = priv->hdmi; in reg_read_range()
586 mutex_lock(&priv->mutex); in reg_read_range()
602 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); in reg_read_range()
604 mutex_unlock(&priv->mutex); in reg_read_range()
613 struct i2c_client *client = priv->hdmi; in reg_write_range()
615 u8 buf[MAX_WRITE_RANGE_BUF + 1]; in reg_write_range()
619 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", in reg_write_range()
625 memcpy(&buf[1], p, cnt); in reg_write_range()
627 mutex_lock(&priv->mutex); in reg_write_range()
632 ret = i2c_master_send(client, buf, cnt + 1); in reg_write_range()
634 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write_range()
636 mutex_unlock(&priv->mutex); in reg_write_range()
654 struct i2c_client *client = priv->hdmi; in reg_write()
658 mutex_lock(&priv->mutex); in reg_write()
665 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write()
667 mutex_unlock(&priv->mutex); in reg_write()
673 struct i2c_client *client = priv->hdmi; in reg_write16()
677 mutex_lock(&priv->mutex); in reg_write16()
684 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); in reg_write16()
686 mutex_unlock(&priv->mutex); in reg_write16()
724 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
737 /* Write the default value MUX register */ in tda998x_reset()
749 * we have seen a HPD inactive->active transition. This code implements
756 priv->edid_delay_active = false; in tda998x_edid_delay_done()
757 wake_up(&priv->edid_delay_waitq); in tda998x_edid_delay_done()
758 schedule_work(&priv->detect_work); in tda998x_edid_delay_done()
763 priv->edid_delay_active = true; in tda998x_edid_delay_start()
764 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); in tda998x_edid_delay_start()
769 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); in tda998x_edid_delay_wait()
781 struct drm_device *dev = priv->connector.dev; in tda998x_detect_work()
811 schedule_work(&priv->detect_work); in tda998x_irq_thread()
813 priv->cec_notify); in tda998x_irq_thread()
819 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { in tda998x_irq_thread()
820 priv->wq_edid_wait = 0; in tda998x_irq_thread()
821 wake_up(&priv->wq_edid); in tda998x_irq_thread()
838 dev_err(&priv->hdmi->dev, in tda998x_write_if()
840 frame->any.type, len); in tda998x_write_if()
865 &priv->connector, mode); in tda998x_write_avi()
867 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, in tda998x_write_avi()
868 priv->rgb_quant_range); in tda998x_write_avi()
879 &priv->connector, in tda998x_write_vsi()
890 .ena_aclk = 1,
906 s->route = &tda998x_audio_route[route]; in tda998x_derive_routing()
907 s->ena_ap = priv->audio_port_enable[route]; in tda998x_derive_routing()
908 if (s->ena_ap == 0) { in tda998x_derive_routing()
909 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); in tda998x_derive_routing()
910 return -EINVAL; in tda998x_derive_routing()
928 unsigned long ser_clk = priv->tmds_clock * 1000; in tda998x_get_adiv()
931 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) in tda998x_get_adiv()
935 dev_dbg(&priv->hdmi->dev, in tda998x_get_adiv()
943 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
949 * tmdsclk ----> mts -> /m ---> CTS
951 * sclk -> /k -> /N
954 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
960 * When combined with the sink-side equation, and realising that sclk is
972 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); in tda998x_derive_cts_n()
975 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); in tda998x_derive_cts_n()
978 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); in tda998x_derive_cts_n()
981 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); in tda998x_derive_cts_n()
984 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); in tda998x_derive_cts_n()
987 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", in tda998x_derive_cts_n()
989 return -EINVAL; in tda998x_derive_cts_n()
1007 const struct tda998x_audio_settings *settings = &priv->audio; in tda998x_configure_audio()
1012 if (settings->ena_ap == 0) in tda998x_configure_audio()
1015 adiv = tda998x_get_adiv(priv, settings->sample_rate); in tda998x_configure_audio()
1018 reg_write(priv, REG_ENA_AP, settings->ena_ap); in tda998x_configure_audio()
1019 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); in tda998x_configure_audio()
1020 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); in tda998x_configure_audio()
1021 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); in tda998x_configure_audio()
1022 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); in tda998x_configure_audio()
1025 reg_write(priv, REG_CTS_N, settings->cts_n); in tda998x_configure_audio()
1030 * the recommended values for non-coherent clocks. in tda998x_configure_audio()
1032 n = 128 * settings->sample_rate / 1000; in tda998x_configure_audio()
1034 /* Write the CTS and N values */ in tda998x_configure_audio()
1036 buf[1] = 0x42; in tda998x_configure_audio()
1047 /* Write the channel status in tda998x_configure_audio()
1048 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because in tda998x_configure_audio()
1051 buf[0] = settings->status[0]; in tda998x_configure_audio()
1052 buf[1] = settings->status[1]; in tda998x_configure_audio()
1053 buf[2] = settings->status[3]; in tda998x_configure_audio()
1054 buf[3] = settings->status[4]; in tda998x_configure_audio()
1061 tda998x_write_aif(priv, &settings->cea); in tda998x_configure_audio()
1070 bool spdif = daifmt->fmt == HDMI_SPDIF; in tda998x_audio_hw_params()
1073 .sample_rate = params->sample_rate, in tda998x_audio_hw_params()
1074 .cea = params->cea, in tda998x_audio_hw_params()
1077 memcpy(audio.status, params->iec.status, in tda998x_audio_hw_params()
1078 min(sizeof(audio.status), sizeof(params->iec.status))); in tda998x_audio_hw_params()
1080 switch (daifmt->fmt) { in tda998x_audio_hw_params()
1094 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); in tda998x_audio_hw_params()
1095 return -EINVAL; in tda998x_audio_hw_params()
1099 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || in tda998x_audio_hw_params()
1100 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { in tda998x_audio_hw_params()
1102 daifmt->bit_clk_inv, daifmt->frame_clk_inv, in tda998x_audio_hw_params()
1103 daifmt->bit_clk_provider, in tda998x_audio_hw_params()
1104 daifmt->frame_clk_provider); in tda998x_audio_hw_params()
1105 return -EINVAL; in tda998x_audio_hw_params()
1112 bclk_ratio = spdif ? 64 : params->sample_width * 2; in tda998x_audio_hw_params()
1117 mutex_lock(&priv->audio_mutex); in tda998x_audio_hw_params()
1118 priv->audio = audio; in tda998x_audio_hw_params()
1119 if (priv->supports_infoframes && priv->sink_has_audio) in tda998x_audio_hw_params()
1121 mutex_unlock(&priv->audio_mutex); in tda998x_audio_hw_params()
1130 mutex_lock(&priv->audio_mutex); in tda998x_audio_shutdown()
1133 priv->audio.ena_ap = 0; in tda998x_audio_shutdown()
1135 mutex_unlock(&priv->audio_mutex); in tda998x_audio_shutdown()
1143 mutex_lock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1147 mutex_unlock(&priv->audio_mutex); in tda998x_audio_mute_stream()
1156 mutex_lock(&priv->audio_mutex); in tda998x_audio_get_eld()
1157 memcpy(buf, priv->connector.eld, in tda998x_audio_get_eld()
1158 min(sizeof(priv->connector.eld), len)); in tda998x_audio_get_eld()
1159 mutex_unlock(&priv->audio_mutex); in tda998x_audio_get_eld()
1177 .no_i2s_capture = 1, in tda998x_audio_codec_init()
1178 .no_spdif_capture = 1, in tda998x_audio_codec_init()
1179 .no_capture_mute = 1, in tda998x_audio_codec_init()
1182 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) in tda998x_audio_codec_init()
1183 codec_data.i2s = 1; in tda998x_audio_codec_init()
1184 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_audio_codec_init()
1185 codec_data.spdif = 1; in tda998x_audio_codec_init()
1187 priv->audio_pdev = platform_device_register_data( in tda998x_audio_codec_init()
1191 return PTR_ERR_OR_ZERO(priv->audio_pdev); in tda998x_audio_codec_init()
1226 offset = (blk & 1) ? 128 : 0; in read_edid_block()
1229 mutex_lock(&priv->edid_mutex); in read_edid_block()
1237 priv->wq_edid_wait = 1; in read_edid_block()
1244 if (priv->hdmi->irq) { in read_edid_block()
1245 i = wait_event_timeout(priv->wq_edid, in read_edid_block()
1246 !priv->wq_edid_wait, in read_edid_block()
1249 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); in read_edid_block()
1254 for (i = 100; i > 0; i--) { in read_edid_block()
1255 msleep(1); in read_edid_block()
1265 dev_err(&priv->hdmi->dev, "read edid timeout\n"); in read_edid_block()
1266 ret = -ETIMEDOUT; in read_edid_block()
1272 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", in read_edid_block()
1280 mutex_unlock(&priv->edid_mutex); in read_edid_block()
1298 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1303 if (priv->rev == TDA19988) in tda998x_connector_get_modes()
1307 cec_notifier_set_phys_addr(priv->cec_notify, in tda998x_connector_get_modes()
1308 connector->display_info.source_physical_address); in tda998x_connector_get_modes()
1311 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); in tda998x_connector_get_modes()
1315 mutex_lock(&priv->audio_mutex); in tda998x_connector_get_modes()
1317 priv->sink_has_audio = connector->display_info.has_audio; in tda998x_connector_get_modes()
1318 mutex_unlock(&priv->audio_mutex); in tda998x_connector_get_modes()
1330 return priv->bridge.encoder; in tda998x_connector_best_encoder()
1342 struct drm_connector *connector = &priv->connector; in tda998x_connector_init()
1345 connector->interlace_allowed = 1; in tda998x_connector_init()
1347 if (priv->hdmi->irq) in tda998x_connector_init()
1348 connector->polled = DRM_CONNECTOR_POLL_HPD; in tda998x_connector_init()
1350 connector->polled = DRM_CONNECTOR_POLL_CONNECT | in tda998x_connector_init()
1359 drm_connector_attach_encoder(&priv->connector, in tda998x_connector_init()
1360 priv->bridge.encoder); in tda998x_connector_init()
1374 return -EINVAL; in tda998x_bridge_attach()
1377 return tda998x_connector_init(priv, bridge->dev); in tda998x_bridge_attach()
1384 drm_connector_cleanup(&priv->connector); in tda998x_bridge_detach()
1394 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) in tda998x_bridge_mode_valid()
1396 if (mode->htotal >= BIT(13)) in tda998x_bridge_mode_valid()
1398 if (mode->vtotal >= BIT(11)) in tda998x_bridge_mode_valid()
1407 if (!priv->is_on) { in tda998x_bridge_enable()
1413 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); in tda998x_bridge_enable()
1414 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); in tda998x_bridge_enable()
1415 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); in tda998x_bridge_enable()
1417 priv->is_on = true; in tda998x_bridge_enable()
1425 if (priv->is_on) { in tda998x_bridge_disable()
1431 priv->is_on = false; in tda998x_bridge_disable()
1452 * full-range RGB. If the monitor supports full-range, then use in tda998x_bridge_mode_set()
1453 * it, otherwise reduce to limited-range. in tda998x_bridge_mode_set()
1455 priv->rgb_quant_range = in tda998x_bridge_mode_set()
1456 priv->connector.display_info.rgb_quant_range_selectable ? in tda998x_bridge_mode_set()
1461 * Internally TDA998x is using ITU-R BT.656 style sync but in tda998x_bridge_mode_set()
1469 * - HDMI data islands require sync-before-active in tda998x_bridge_mode_set()
1470 * - TDA998x register values must be > 0 to be enabled in tda998x_bridge_mode_set()
1471 * - REFLINE needs an additional offset of +1 in tda998x_bridge_mode_set()
1472 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB in tda998x_bridge_mode_set()
1474 * So we add +1 to all horizontal and vertical register values, in tda998x_bridge_mode_set()
1477 n_pix = mode->htotal; in tda998x_bridge_mode_set()
1478 n_line = mode->vtotal; in tda998x_bridge_mode_set()
1480 hs_pix_e = mode->hsync_end - mode->hdisplay; in tda998x_bridge_mode_set()
1481 hs_pix_s = mode->hsync_start - mode->hdisplay; in tda998x_bridge_mode_set()
1482 de_pix_e = mode->htotal; in tda998x_bridge_mode_set()
1483 de_pix_s = mode->htotal - mode->hdisplay; in tda998x_bridge_mode_set()
1491 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) in tda998x_bridge_mode_set()
1492 ref_pix += adjusted_mode->hskew; in tda998x_bridge_mode_set()
1494 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { in tda998x_bridge_mode_set()
1495 ref_line = 1 + mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1496 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; in tda998x_bridge_mode_set()
1497 vwin1_line_e = vwin1_line_s + mode->vdisplay; in tda998x_bridge_mode_set()
1499 vs1_line_s = mode->vsync_start - mode->vdisplay; in tda998x_bridge_mode_set()
1501 mode->vsync_end - mode->vsync_start; in tda998x_bridge_mode_set()
1506 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1507 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1508 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1510 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; in tda998x_bridge_mode_set()
1512 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1513 vwin2_line_s = vwin1_line_s + mode->vtotal/2; in tda998x_bridge_mode_set()
1514 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; in tda998x_bridge_mode_set()
1515 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; in tda998x_bridge_mode_set()
1516 vs2_line_s = vs1_line_s + mode->vtotal/2 ; in tda998x_bridge_mode_set()
1518 (mode->vsync_end - mode->vsync_start)/2; in tda998x_bridge_mode_set()
1522 * Select pixel repeat depending on the double-clock flag in tda998x_bridge_mode_set()
1525 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; in tda998x_bridge_mode_set()
1530 tmds_clock = mode->clock * (1 + rep); in tda998x_bridge_mode_set()
1533 * The divisor is power-of-2. The TDA9983B datasheet gives in tda998x_bridge_mode_set()
1535 * 0 - 800 to 1500 Msample/s in tda998x_bridge_mode_set()
1536 * 1 - 400 to 800 Msample/s in tda998x_bridge_mode_set()
1537 * 2 - 200 to 400 Msample/s in tda998x_bridge_mode_set()
1538 * 3 - as 2 above in tda998x_bridge_mode_set()
1544 mutex_lock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1546 priv->tmds_clock = tmds_clock; in tda998x_bridge_mode_set()
1556 /* no pre-filter or interpolator: */ in tda998x_bridge_mode_set()
1576 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { in tda998x_bridge_mode_set()
1591 MAT_CONTRL_MAT_SC(1)); in tda998x_bridge_mode_set()
1604 * TDA19988 requires high-active sync at input stage, in tda998x_bridge_mode_set()
1605 * so invert low-active sync provided by master encoder here in tda998x_bridge_mode_set()
1607 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1609 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1635 if (priv->rev == TDA19988) { in tda998x_bridge_mode_set()
1645 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tda998x_bridge_mode_set()
1647 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tda998x_bridge_mode_set()
1654 /* CEA-861B section 6 says that: in tda998x_bridge_mode_set()
1655 * CEA version 1 (CEA-861) has no support for infoframes. in tda998x_bridge_mode_set()
1656 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, in tda998x_bridge_mode_set()
1658 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, in tda998x_bridge_mode_set()
1663 * CEA-861 source.) in tda998x_bridge_mode_set()
1665 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; in tda998x_bridge_mode_set()
1667 if (priv->supports_infoframes) { in tda998x_bridge_mode_set()
1671 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); in tda998x_bridge_mode_set()
1677 if (priv->sink_has_audio) in tda998x_bridge_mode_set()
1681 mutex_unlock(&priv->audio_mutex); in tda998x_bridge_mode_set()
1702 port_data = of_get_property(np, "audio-ports", &size); in tda998x_get_audio_ports()
1707 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { in tda998x_get_audio_ports()
1708 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1709 "Bad number of elements in audio-ports dt-property\n"); in tda998x_get_audio_ports()
1710 return -EINVAL; in tda998x_get_audio_ports()
1718 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); in tda998x_get_audio_ports()
1728 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1730 return -EINVAL; in tda998x_get_audio_ports()
1734 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); in tda998x_get_audio_ports()
1738 if (priv->audio_port_enable[route]) { in tda998x_get_audio_ports()
1739 dev_err(&priv->hdmi->dev, in tda998x_get_audio_ports()
1742 return -EINVAL; in tda998x_get_audio_ports()
1745 priv->audio_port_enable[route] = ena_ap; in tda998x_get_audio_ports()
1754 drm_bridge_remove(&priv->bridge); in tda998x_destroy()
1760 if (priv->audio_pdev) in tda998x_destroy()
1761 platform_device_unregister(priv->audio_pdev); in tda998x_destroy()
1763 if (priv->hdmi->irq) in tda998x_destroy()
1764 free_irq(priv->hdmi->irq, priv); in tda998x_destroy()
1766 timer_delete_sync(&priv->edid_delay_timer); in tda998x_destroy()
1767 cancel_work_sync(&priv->detect_work); in tda998x_destroy()
1769 i2c_unregister_device(priv->cec); in tda998x_destroy()
1771 cec_notifier_conn_unregister(priv->cec_notify); in tda998x_destroy()
1777 struct device_node *np = client->dev.of_node; in tda998x_create()
1785 return -ENOMEM; in tda998x_create()
1789 mutex_init(&priv->mutex); /* protect the page access */ in tda998x_create()
1790 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ in tda998x_create()
1791 mutex_init(&priv->edid_mutex); in tda998x_create()
1792 INIT_LIST_HEAD(&priv->bridge.list); in tda998x_create()
1793 init_waitqueue_head(&priv->edid_delay_waitq); in tda998x_create()
1794 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); in tda998x_create()
1795 INIT_WORK(&priv->detect_work, tda998x_detect_work); in tda998x_create()
1797 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); in tda998x_create()
1798 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); in tda998x_create()
1799 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); in tda998x_create()
1802 priv->cec_addr = 0x34 + (client->addr & 0x03); in tda998x_create()
1803 priv->current_page = 0xff; in tda998x_create()
1804 priv->hdmi = client; in tda998x_create()
1825 priv->rev = rev_lo | rev_hi << 8; in tda998x_create()
1828 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ in tda998x_create()
1830 switch (priv->rev) { in tda998x_create()
1844 dev_err(dev, "found unsupported device: %04x\n", priv->rev); in tda998x_create()
1845 return -ENXIO; in tda998x_create()
1854 /* if necessary, disable multi-master: */ in tda998x_create()
1855 if (priv->rev == TDA19989) in tda998x_create()
1871 if (client->irq) { in tda998x_create()
1875 init_waitqueue_head(&priv->wq_edid); in tda998x_create()
1878 irqd_get_trigger_type(irq_get_irq_data(client->irq)); in tda998x_create()
1880 priv->cec_glue.irq_flags = irq_flags; in tda998x_create()
1883 ret = request_threaded_irq(client->irq, NULL, in tda998x_create()
1888 client->irq, ret); in tda998x_create()
1896 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); in tda998x_create()
1897 if (!priv->cec_notify) { in tda998x_create()
1898 ret = -ENOMEM; in tda998x_create()
1902 priv->cec_glue.parent = dev; in tda998x_create()
1903 priv->cec_glue.data = priv; in tda998x_create()
1904 priv->cec_glue.init = tda998x_cec_hook_init; in tda998x_create()
1905 priv->cec_glue.exit = tda998x_cec_hook_exit; in tda998x_create()
1906 priv->cec_glue.open = tda998x_cec_hook_open; in tda998x_create()
1907 priv->cec_glue.release = tda998x_cec_hook_release; in tda998x_create()
1919 cec_info.addr = priv->cec_addr; in tda998x_create()
1920 cec_info.platform_data = &priv->cec_glue; in tda998x_create()
1921 cec_info.irq = client->irq; in tda998x_create()
1923 priv->cec = i2c_new_client_device(client->adapter, &cec_info); in tda998x_create()
1924 if (IS_ERR(priv->cec)) { in tda998x_create()
1925 ret = PTR_ERR(priv->cec); in tda998x_create()
1934 ret = of_property_read_u32(np, "video-ports", &video); in tda998x_create()
1936 priv->vip_cntrl_0 = video >> 16; in tda998x_create()
1937 priv->vip_cntrl_1 = video >> 8; in tda998x_create()
1938 priv->vip_cntrl_2 = video; in tda998x_create()
1945 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || in tda998x_create()
1946 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) in tda998x_create()
1947 tda998x_audio_codec_init(priv, &client->dev); in tda998x_create()
1950 priv->bridge.funcs = &tda998x_bridge_funcs; in tda998x_create()
1952 priv->bridge.of_node = dev->of_node; in tda998x_create()
1955 drm_bridge_add(&priv->bridge); in tda998x_create()
1973 if (dev->of_node) in tda998x_encoder_init()
1974 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in tda998x_encoder_init()
1979 crtcs = 1 << 0; in tda998x_encoder_init()
1982 priv->encoder.possible_crtcs = crtcs; in tda998x_encoder_init()
1984 ret = drm_simple_encoder_init(drm, &priv->encoder, in tda998x_encoder_init()
1989 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0); in tda998x_encoder_init()
1996 drm_encoder_cleanup(&priv->encoder); in tda998x_encoder_init()
2013 drm_encoder_cleanup(&priv->encoder); in tda998x_unbind()
2026 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { in tda998x_probe()
2027 dev_warn(&client->dev, "adapter does not support I2C\n"); in tda998x_probe()
2028 return -EIO; in tda998x_probe()
2031 ret = tda998x_create(&client->dev); in tda998x_probe()
2035 ret = component_add(&client->dev, &tda998x_ops); in tda998x_probe()
2037 tda998x_destroy(&client->dev); in tda998x_probe()
2043 component_del(&client->dev, &tda998x_ops); in tda998x_remove()
2044 tda998x_destroy(&client->dev); in tda998x_remove()