Lines Matching +full:master +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
105 #define DSIERRCNT 0x0300 /* DSI Error Count */
172 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
173 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
176 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
186 #define I2CMADDR 0x0544 /* I2C Master Addressing */
271 struct mipi_dsi_device *dsi; member
278 u8 lvds_link; /* single-link or dual-link */
292 struct device *dev = &tc->dsi->dev; in tc_bridge_pre_enable()
295 ret = regulator_enable(tc->vddio); in tc_bridge_pre_enable()
300 ret = regulator_enable(tc->vdd); in tc_bridge_pre_enable()
305 gpiod_set_value(tc->stby_gpio, 0); in tc_bridge_pre_enable()
308 gpiod_set_value(tc->reset_gpio, 0); in tc_bridge_pre_enable()
315 struct device *dev = &tc->dsi->dev; in tc_bridge_post_disable()
318 gpiod_set_value(tc->reset_gpio, 1); in tc_bridge_post_disable()
321 gpiod_set_value(tc->stby_gpio, 1); in tc_bridge_post_disable()
324 ret = regulator_disable(tc->vdd); in tc_bridge_post_disable()
329 ret = regulator_disable(tc->vddio); in tc_bridge_post_disable()
353 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", in d2l_read()
367 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", in d2l_write()
374 struct drm_device *dev = encoder->dev; in get_connector()
377 list_for_each_entry(connector, &dev->mode_config.connector_list, head) in get_connector()
378 if (connector->encoder == encoder) in get_connector()
392 struct drm_connector *connector = get_connector(bridge->encoder); in tc_bridge_enable()
394 mode = &bridge->encoder->crtc->state->adjusted_mode; in tc_bridge_enable()
396 hback_porch = mode->htotal - mode->hsync_end; in tc_bridge_enable()
397 hsync_len = mode->hsync_end - mode->hsync_start; in tc_bridge_enable()
398 vback_porch = mode->vtotal - mode->vsync_end; in tc_bridge_enable()
399 vsync_len = mode->vsync_end - mode->vsync_start; in tc_bridge_enable()
404 hfront_porch = mode->hsync_start - mode->hdisplay; in tc_bridge_enable()
405 hactive = mode->hdisplay; in tc_bridge_enable()
406 vfront_porch = mode->vsync_start - mode->vdisplay; in tc_bridge_enable()
407 vactive = mode->vdisplay; in tc_bridge_enable()
412 d2l_read(tc->i2c, IDREG, &val); in tc_bridge_enable()
414 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", in tc_bridge_enable()
417 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | in tc_bridge_enable()
421 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_bridge_enable()
422 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_bridge_enable()
423 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
424 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
425 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
426 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
428 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; in tc_bridge_enable()
429 d2l_write(tc->i2c, PPI_LANEENABLE, val); in tc_bridge_enable()
430 d2l_write(tc->i2c, DSI_LANEENABLE, val); in tc_bridge_enable()
432 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); in tc_bridge_enable()
433 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); in tc_bridge_enable()
436 if (tc->type == TC358765) in tc_bridge_enable()
441 if (tc->bpc == 8) in tc_bridge_enable()
446 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
447 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); in tc_bridge_enable()
449 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; in tc_bridge_enable()
451 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / in tc_bridge_enable()
452 tc->num_dsi_lanes); in tc_bridge_enable()
454 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; in tc_bridge_enable()
457 d2l_write(tc->i2c, VPCTRL, val); in tc_bridge_enable()
459 d2l_write(tc->i2c, HTIM1, htime1); in tc_bridge_enable()
460 d2l_write(tc->i2c, VTIM1, vtime1); in tc_bridge_enable()
461 d2l_write(tc->i2c, HTIM2, htime2); in tc_bridge_enable()
462 d2l_write(tc->i2c, VTIM2, vtime2); in tc_bridge_enable()
464 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
465 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); in tc_bridge_enable()
466 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); in tc_bridge_enable()
468 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", in tc_bridge_enable()
469 connector->display_info.bus_formats[0], in tc_bridge_enable()
470 tc->bpc); in tc_bridge_enable()
471 if (connector->display_info.bus_formats[0] == in tc_bridge_enable()
473 /* VESA-24 */ in tc_bridge_enable()
474 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
475 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); in tc_bridge_enable()
476 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); in tc_bridge_enable()
477 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
478 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); in tc_bridge_enable()
479 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
480 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); in tc_bridge_enable()
482 /* JEIDA-18 and JEIDA-24 */ in tc_bridge_enable()
483 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5)); in tc_bridge_enable()
484 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2)); in tc_bridge_enable()
485 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1)); in tc_bridge_enable()
486 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2)); in tc_bridge_enable()
487 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4)); in tc_bridge_enable()
488 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0)); in tc_bridge_enable()
489 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0)); in tc_bridge_enable()
492 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
495 if (tc->lvds_link == DUAL_LINK) { in tc_bridge_enable()
501 d2l_write(tc->i2c, LVCFG, val); in tc_bridge_enable()
512 * Maximum pixel clock speed 135MHz for single-link in tc_mode_valid()
513 * 270MHz for dual-link in tc_mode_valid()
515 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || in tc_mode_valid()
516 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) in tc_mode_valid()
519 switch (info->bus_formats[0]) { in tc_mode_valid()
523 tc->bpc = 8; in tc_mode_valid()
527 tc->bpc = 6; in tc_mode_valid()
530 dev_warn(tc->dev, in tc_mode_valid()
532 info->bus_formats[0]); in tc_mode_valid()
543 int dsi_lanes = -1; in tc358775_parse_dt()
545 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
546 TC358775_DSI_IN, -1); in tc358775_parse_dt()
549 /* Quirk old dtb: Use data lanes from the DSI host side instead of bridge */ in tc358775_parse_dt()
550 if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) { in tc358775_parse_dt()
555 dev_warn(tc->dev, "no dsi-lanes for the bridge, using host lanes\n"); in tc358775_parse_dt()
563 tc->num_dsi_lanes = dsi_lanes; in tc358775_parse_dt()
565 tc->host_node = of_graph_get_remote_node(np, 0, 0); in tc358775_parse_dt()
566 if (!tc->host_node) in tc358775_parse_dt()
567 return -ENODEV; in tc358775_parse_dt()
569 of_node_put(tc->host_node); in tc358775_parse_dt()
571 tc->lvds_link = SINGLE_LINK; in tc358775_parse_dt()
572 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
573 TC358775_LVDS_OUT1, -1); in tc358775_parse_dt()
580 tc->lvds_link = DUAL_LINK; in tc358775_parse_dt()
585 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); in tc358775_parse_dt()
586 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); in tc358775_parse_dt()
596 /* Attach the panel-bridge to the dsi bridge */ in tc_bridge_attach()
597 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, in tc_bridge_attach()
598 &tc->bridge, flags); in tc_bridge_attach()
611 struct device *dev = &tc->i2c->dev; in tc_attach_host()
613 struct mipi_dsi_device *dsi; in tc_attach_host() local
620 host = of_find_mipi_dsi_host_by_node(tc->host_node); in tc_attach_host()
622 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n"); in tc_attach_host()
624 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); in tc_attach_host()
625 if (IS_ERR(dsi)) { in tc_attach_host()
626 dev_err(dev, "failed to create dsi device\n"); in tc_attach_host()
627 return PTR_ERR(dsi); in tc_attach_host()
630 tc->dsi = dsi; in tc_attach_host()
632 dsi->lanes = tc->num_dsi_lanes; in tc_attach_host()
633 dsi->format = MIPI_DSI_FMT_RGB888; in tc_attach_host()
634 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | in tc_attach_host()
640 * uses DDR, the DSI clock frequency is half the hs_rate. The 10 Mbs in tc_attach_host()
642 * but seems to be part of the MIPI DSI spec. in tc_attach_host()
644 if (tc->type == TC358765) in tc_attach_host()
645 dsi->hs_rate = 800000000; in tc_attach_host()
647 dsi->hs_rate = 1000000000; in tc_attach_host()
648 dsi->lp_rate = 10000000; in tc_attach_host()
650 ret = devm_mipi_dsi_attach(dev, dsi); in tc_attach_host()
652 dev_err(dev, "failed to attach dsi to host\n"); in tc_attach_host()
661 struct device *dev = &client->dev; in tc_probe()
667 return -ENOMEM; in tc_probe()
669 tc->dev = dev; in tc_probe()
670 tc->i2c = client; in tc_probe()
671 tc->type = (enum tc3587x5_type)(unsigned long)of_device_get_match_data(dev); in tc_probe()
673 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, in tc_probe()
675 if (IS_ERR(tc->panel_bridge)) in tc_probe()
676 return PTR_ERR(tc->panel_bridge); in tc_probe()
678 ret = tc358775_parse_dt(dev->of_node, tc); in tc_probe()
682 tc->vddio = devm_regulator_get(dev, "vddio-supply"); in tc_probe()
683 if (IS_ERR(tc->vddio)) { in tc_probe()
684 ret = PTR_ERR(tc->vddio); in tc_probe()
685 dev_err(dev, "vddio-supply not found\n"); in tc_probe()
689 tc->vdd = devm_regulator_get(dev, "vdd-supply"); in tc_probe()
690 if (IS_ERR(tc->vdd)) { in tc_probe()
691 ret = PTR_ERR(tc->vdd); in tc_probe()
692 dev_err(dev, "vdd-supply not found\n"); in tc_probe()
696 tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH); in tc_probe()
697 if (IS_ERR(tc->stby_gpio)) in tc_probe()
698 return PTR_ERR(tc->stby_gpio); in tc_probe()
700 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); in tc_probe()
701 if (IS_ERR(tc->reset_gpio)) { in tc_probe()
702 ret = PTR_ERR(tc->reset_gpio); in tc_probe()
703 dev_err(dev, "cannot get reset-gpios %d\n", ret); in tc_probe()
707 tc->bridge.funcs = &tc_bridge_funcs; in tc_probe()
708 tc->bridge.of_node = dev->of_node; in tc_probe()
709 tc->bridge.pre_enable_prev_first = true; in tc_probe()
710 drm_bridge_add(&tc->bridge); in tc_probe()
721 drm_bridge_remove(&tc->bridge); in tc_probe()
729 drm_bridge_remove(&tc->bridge); in tc_remove()
758 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");