58  * jpeg_v2_0_early_init - set function pointers
66 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_early_init()
68 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v2_0_early_init()
69 	adev->jpeg.num_jpeg_rings = 1;  in jpeg_v2_0_early_init()
78  * jpeg_v2_0_sw_init - sw init for JPEG block
86 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_sw_init()
92 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v2_0_sw_init()
104 	ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_sw_init()
105 	ring->use_doorbell = true;  in jpeg_v2_0_sw_init()
106 	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;  in jpeg_v2_0_sw_init()
107 	ring->vm_hub = AMDGPU_MMHUB0(0);  in jpeg_v2_0_sw_init()
108 	sprintf(ring->name, "jpeg_dec");  in jpeg_v2_0_sw_init()
109 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,  in jpeg_v2_0_sw_init()
114 	adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v2_0_sw_init()
115 	adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);  in jpeg_v2_0_sw_init()
121 	adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;  in jpeg_v2_0_sw_init()
128  * jpeg_v2_0_sw_fini - sw fini for JPEG block
137 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_sw_fini()
151  * jpeg_v2_0_hw_init - start and test JPEG block
158 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_hw_init()
159 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_hw_init()
161 	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,  in jpeg_v2_0_hw_init()
162 		(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);  in jpeg_v2_0_hw_init()
168  * jpeg_v2_0_hw_fini - stop the hardware block
176 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_hw_fini()
178 	cancel_delayed_work_sync(&adev->jpeg.idle_work);  in jpeg_v2_0_hw_fini()
180 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v2_0_hw_fini()
188  * jpeg_v2_0_suspend - suspend JPEG block
202 	r = amdgpu_jpeg_suspend(ip_block->adev);  in jpeg_v2_0_suspend()
208  * jpeg_v2_0_resume - resume JPEG block
218 	r = amdgpu_jpeg_resume(ip_block->adev);  in jpeg_v2_0_resume()
232 	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {  in jpeg_v2_0_disable_power_gating()
255 	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {  in jpeg_v2_0_enable_power_gating()
285 	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)  in jpeg_v2_0_disable_clock_gating()
308 	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)  in jpeg_v2_0_enable_clock_gating()
327  * jpeg_v2_0_start - start JPEG block
335 	struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;  in jpeg_v2_0_start()
338 	if (adev->pm.dpm_enabled)  in jpeg_v2_0_start()
349 	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in jpeg_v2_0_start()
363 		lower_32_bits(ring->gpu_addr));  in jpeg_v2_0_start()
365 		upper_32_bits(ring->gpu_addr));  in jpeg_v2_0_start()
369 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v2_0_start()
370 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v2_0_start()
376  * jpeg_v2_0_stop - stop JPEG block
399 	if (adev->pm.dpm_enabled)  in jpeg_v2_0_stop()
406  * jpeg_v2_0_dec_ring_get_rptr - get read pointer
414 	struct amdgpu_device *adev = ring->adev;  in jpeg_v2_0_dec_ring_get_rptr()
420  * jpeg_v2_0_dec_ring_get_wptr - get write pointer
428 	struct amdgpu_device *adev = ring->adev;  in jpeg_v2_0_dec_ring_get_wptr()
430 	if (ring->use_doorbell)  in jpeg_v2_0_dec_ring_get_wptr()
431 		return *ring->wptr_cpu_addr;  in jpeg_v2_0_dec_ring_get_wptr()
437  * jpeg_v2_0_dec_ring_set_wptr - set write pointer
445 	struct amdgpu_device *adev = ring->adev;  in jpeg_v2_0_dec_ring_set_wptr()
447 	if (ring->use_doorbell) {  in jpeg_v2_0_dec_ring_set_wptr()
448 		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);  in jpeg_v2_0_dec_ring_set_wptr()
449 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));  in jpeg_v2_0_dec_ring_set_wptr()
451 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v2_0_dec_ring_set_wptr()
456  * jpeg_v2_0_dec_ring_insert_start - insert a start command
474  * jpeg_v2_0_dec_ring_insert_end - insert a end command
492  * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
543  * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
566 	if (ring->funcs->parse_cs)  in jpeg_v2_0_dec_ring_emit_ib()
577 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in jpeg_v2_0_dec_ring_emit_ib()
581 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in jpeg_v2_0_dec_ring_emit_ib()
585 	amdgpu_ring_write(ring, ib->length_dw);  in jpeg_v2_0_dec_ring_emit_ib()
589 	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));  in jpeg_v2_0_dec_ring_emit_ib()
593 	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));  in jpeg_v2_0_dec_ring_emit_ib()
641 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];  in jpeg_v2_0_dec_ring_emit_vm_flush()
647 	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;  in jpeg_v2_0_dec_ring_emit_vm_flush()
675 	WARN_ON(ring->wptr % 2 || count % 2);  in jpeg_v2_0_dec_ring_nop()
685 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_is_idle()
694 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_wait_for_idle()
706 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_set_clockgating_state()
711 			return -EBUSY;  in jpeg_v2_0_set_clockgating_state()
723 	struct amdgpu_device *adev = ip_block->adev;  in jpeg_v2_0_set_powergating_state()
726 	if (state == adev->jpeg.cur_state)  in jpeg_v2_0_set_powergating_state()
735 		adev->jpeg.cur_state = state;  in jpeg_v2_0_set_powergating_state()
754 	switch (entry->src_id) {  in jpeg_v2_0_process_interrupt()
756 		amdgpu_fence_process(adev->jpeg.inst->ring_dec);  in jpeg_v2_0_process_interrupt()
760 			  entry->src_id, entry->src_data[0]);  in jpeg_v2_0_process_interrupt()
769 	jpeg_v2_0_stop(ring->adev);  in jpeg_v2_0_ring_reset()
770 	jpeg_v2_0_start(ring->adev);  in jpeg_v2_0_ring_reset()
824 	adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;  in jpeg_v2_0_set_dec_ring_funcs()
834 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v2_0_set_irq_funcs()
835 	adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;  in jpeg_v2_0_set_irq_funcs()
847  * jpeg_v2_dec_ring_parse_cs - command submission parser
853  * Parse the command stream, return -EINVAL for invalid packet,
860 	u32 i, reg, res, cond, type;  in jpeg_v2_dec_ring_parse_cs()  local
861 	struct amdgpu_device *adev = parser->adev;  in jpeg_v2_dec_ring_parse_cs()
863 	for (i = 0; i < ib->length_dw ; i += 2) {  in jpeg_v2_dec_ring_parse_cs()
864 		reg  = CP_PACKETJ_GET_REG(ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
865 		res  = CP_PACKETJ_GET_RES(ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
866 		cond = CP_PACKETJ_GET_COND(ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
867 		type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
870 			return -EINVAL;  in jpeg_v2_dec_ring_parse_cs()
874 			if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||  in jpeg_v2_dec_ring_parse_cs()
876 				dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
877 				return -EINVAL;  in jpeg_v2_dec_ring_parse_cs()
881 			if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||  in jpeg_v2_dec_ring_parse_cs()
883 				dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
884 				return -EINVAL;  in jpeg_v2_dec_ring_parse_cs()
888 			if (ib->ptr[i] == CP_PACKETJ_NOP)  in jpeg_v2_dec_ring_parse_cs()
890 			dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);  in jpeg_v2_dec_ring_parse_cs()
891 			return -EINVAL;  in jpeg_v2_dec_ring_parse_cs()
893 			dev_err(adev->dev, "Unknown packet type %d !\n", type);  in jpeg_v2_dec_ring_parse_cs()
894 			return -EINVAL;  in jpeg_v2_dec_ring_parse_cs()