Lines Matching +full:0 +full:x8c20
52 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
53 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
54 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
93 #define MICRO_TILE_MODE(x) ((x) << 0)
102 (0x8000 << 16) | (0x98f4 >> 2),
103 0x00000000,
104 (0x8040 << 16) | (0x98f4 >> 2),
105 0x00000000,
106 (0x8000 << 16) | (0xe80 >> 2),
107 0x00000000,
108 (0x8040 << 16) | (0xe80 >> 2),
109 0x00000000,
110 (0x8000 << 16) | (0x89bc >> 2),
111 0x00000000,
112 (0x8040 << 16) | (0x89bc >> 2),
113 0x00000000,
114 (0x8000 << 16) | (0x8c1c >> 2),
115 0x00000000,
116 (0x8040 << 16) | (0x8c1c >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0x98f0 >> 2),
119 0x00000000,
120 (0x9c00 << 16) | (0xe7c >> 2),
121 0x00000000,
122 (0x8000 << 16) | (0x9148 >> 2),
123 0x00000000,
124 (0x8040 << 16) | (0x9148 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9150 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x897c >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x8d8c >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0xac54 >> 2),
133 0X00000000,
134 0x3,
135 (0x9c00 << 16) | (0x98f8 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x9910 >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9914 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x9918 >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x991c >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x9920 >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9924 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x9928 >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x992c >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x9930 >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9934 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x9938 >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x993c >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x9940 >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9944 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x9948 >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x994c >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x9950 >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9954 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x9958 >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x995c >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x9960 >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x9964 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x9968 >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x996c >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0x9970 >> 2),
186 0x00000000,
187 (0x9c00 << 16) | (0x9974 >> 2),
188 0x00000000,
189 (0x9c00 << 16) | (0x9978 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x997c >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x9980 >> 2),
194 0x00000000,
195 (0x9c00 << 16) | (0x9984 >> 2),
196 0x00000000,
197 (0x9c00 << 16) | (0x9988 >> 2),
198 0x00000000,
199 (0x9c00 << 16) | (0x998c >> 2),
200 0x00000000,
201 (0x9c00 << 16) | (0x8c00 >> 2),
202 0x00000000,
203 (0x9c00 << 16) | (0x8c14 >> 2),
204 0x00000000,
205 (0x9c00 << 16) | (0x8c04 >> 2),
206 0x00000000,
207 (0x9c00 << 16) | (0x8c08 >> 2),
208 0x00000000,
209 (0x8000 << 16) | (0x9b7c >> 2),
210 0x00000000,
211 (0x8040 << 16) | (0x9b7c >> 2),
212 0x00000000,
213 (0x8000 << 16) | (0xe84 >> 2),
214 0x00000000,
215 (0x8040 << 16) | (0xe84 >> 2),
216 0x00000000,
217 (0x8000 << 16) | (0x89c0 >> 2),
218 0x00000000,
219 (0x8040 << 16) | (0x89c0 >> 2),
220 0x00000000,
221 (0x8000 << 16) | (0x914c >> 2),
222 0x00000000,
223 (0x8040 << 16) | (0x914c >> 2),
224 0x00000000,
225 (0x8000 << 16) | (0x8c20 >> 2),
226 0x00000000,
227 (0x8040 << 16) | (0x8c20 >> 2),
228 0x00000000,
229 (0x8000 << 16) | (0x9354 >> 2),
230 0x00000000,
231 (0x8040 << 16) | (0x9354 >> 2),
232 0x00000000,
233 (0x9c00 << 16) | (0x9060 >> 2),
234 0x00000000,
235 (0x9c00 << 16) | (0x9364 >> 2),
236 0x00000000,
237 (0x9c00 << 16) | (0x9100 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x913c >> 2),
240 0x00000000,
241 (0x8000 << 16) | (0x90e0 >> 2),
242 0x00000000,
243 (0x8000 << 16) | (0x90e4 >> 2),
244 0x00000000,
245 (0x8000 << 16) | (0x90e8 >> 2),
246 0x00000000,
247 (0x8040 << 16) | (0x90e0 >> 2),
248 0x00000000,
249 (0x8040 << 16) | (0x90e4 >> 2),
250 0x00000000,
251 (0x8040 << 16) | (0x90e8 >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x8bcc >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x8b24 >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x88c4 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0x8e50 >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0x8c0c >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0x8e58 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0x8e5c >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0x9508 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x950c >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x9494 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0xac0c >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0xac10 >> 2),
276 0x00000000,
277 (0x9c00 << 16) | (0xac14 >> 2),
278 0x00000000,
279 (0x9c00 << 16) | (0xae00 >> 2),
280 0x00000000,
281 (0x9c00 << 16) | (0xac08 >> 2),
282 0x00000000,
283 (0x9c00 << 16) | (0x88d4 >> 2),
284 0x00000000,
285 (0x9c00 << 16) | (0x88c8 >> 2),
286 0x00000000,
287 (0x9c00 << 16) | (0x88cc >> 2),
288 0x00000000,
289 (0x9c00 << 16) | (0x89b0 >> 2),
290 0x00000000,
291 (0x9c00 << 16) | (0x8b10 >> 2),
292 0x00000000,
293 (0x9c00 << 16) | (0x8a14 >> 2),
294 0x00000000,
295 (0x9c00 << 16) | (0x9830 >> 2),
296 0x00000000,
297 (0x9c00 << 16) | (0x9834 >> 2),
298 0x00000000,
299 (0x9c00 << 16) | (0x9838 >> 2),
300 0x00000000,
301 (0x9c00 << 16) | (0x9a10 >> 2),
302 0x00000000,
303 (0x8000 << 16) | (0x9870 >> 2),
304 0x00000000,
305 (0x8000 << 16) | (0x9874 >> 2),
306 0x00000000,
307 (0x8001 << 16) | (0x9870 >> 2),
308 0x00000000,
309 (0x8001 << 16) | (0x9874 >> 2),
310 0x00000000,
311 (0x8040 << 16) | (0x9870 >> 2),
312 0x00000000,
313 (0x8040 << 16) | (0x9874 >> 2),
314 0x00000000,
315 (0x8041 << 16) | (0x9870 >> 2),
316 0x00000000,
317 (0x8041 << 16) | (0x9874 >> 2),
318 0x00000000,
319 0x00000000
402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
419 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
640 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
643 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
846 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
849 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
1070 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1073 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | in gfx_v6_0_tiling_mode_table_init()
1294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1297 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v6_0_tiling_mode_table_init()
1306 if (instance == 0xffffffff) in gfx_v6_0_select_se_sh()
1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v6_0_select_se_sh()
1309 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v6_0_select_se_sh()
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1314 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1317 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1365 *rconf |= 0x0; in gfx_v6_0_raster_config()
1368 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v6_0_raster_config()
1384 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1385 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1393 for (se = 0; se < num_se; se++) { in gfx_v6_0_write_harvested_raster_configs()
1455 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_write_harvested_raster_configs()
1460 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_write_harvested_raster_configs()
1467 u32 raster_config = 0; in gfx_v6_0_setup_rb()
1468 u32 active_rbs = 0; in gfx_v6_0_setup_rb()
1474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1476 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1483 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1504 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1513 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_rb()
1547 u32 active_cu = 0; in gfx_v6_0_setup_spi()
1550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_spi()
1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1552 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_setup_spi()
1557 for (k = 0; k < 16; k++) { in gfx_v6_0_setup_spi()
1567 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_setup_spi()
1573 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v6_0_config_init()
1578 u32 gb_addr_config = 0; in gfx_v6_0_constants_init()
1596 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1597 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1598 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1599 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1613 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1614 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1615 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1616 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1630 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1631 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1632 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1633 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1647 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1648 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1649 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1650 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1665 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1666 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1667 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1675 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); in gfx_v6_0_constants_init()
1698 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1719 #if 0 in gfx_v6_0_constants_init()
1735 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | in gfx_v6_0_constants_init()
1736 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); in gfx_v6_0_constants_init()
1737 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | in gfx_v6_0_constants_init()
1738 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); in gfx_v6_0_constants_init()
1751 WREG32(mmCP_PERFMON_CNTL, 0); in gfx_v6_0_constants_init()
1752 WREG32(mmSQ_CONFIG, 0); in gfx_v6_0_constants_init()
1761 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); in gfx_v6_0_constants_init()
1763 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); in gfx_v6_0_constants_init()
1764 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); in gfx_v6_0_constants_init()
1765 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); in gfx_v6_0_constants_init()
1766 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); in gfx_v6_0_constants_init()
1767 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); in gfx_v6_0_constants_init()
1768 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); in gfx_v6_0_constants_init()
1769 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); in gfx_v6_0_constants_init()
1770 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); in gfx_v6_0_constants_init()
1784 uint32_t tmp = 0; in gfx_v6_0_ring_test_ring()
1788 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ring()
1796 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1799 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_ring_test_ring()
1801 if (tmp == 0xDEADBEEF) in gfx_v6_0_ring_test_ring()
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1815 EVENT_INDEX(0)); in gfx_v6_0_ring_emit_vgt_flush()
1826 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1832 amdgpu_ring_write(ring, 0xFFFFFFFF); in gfx_v6_0_ring_emit_fence()
1833 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1838 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v6_0_ring_emit_fence()
1839 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v6_0_ring_emit_fence()
1841 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
1852 u32 header, control = 0; in gfx_v6_0_ring_emit_ib()
1856 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1857 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_ib()
1870 (2 << 0) | in gfx_v6_0_ring_emit_ib()
1872 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v6_0_ring_emit_ib()
1873 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v6_0_ring_emit_ib()
1885 * Returns 0 on success, error on failure.
1892 uint32_t tmp = 0; in gfx_v6_0_ring_test_ib()
1895 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ib()
1896 memset(&ib, 0, sizeof(ib)); in gfx_v6_0_ring_test_ib()
1901 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
1903 ib.ptr[2] = 0xDEADBEEF; in gfx_v6_0_ring_test_ib()
1911 if (r == 0) { in gfx_v6_0_ring_test_ib()
1914 } else if (r < 0) { in gfx_v6_0_ring_test_ib()
1918 if (tmp == 0xDEADBEEF) in gfx_v6_0_ring_test_ib()
1919 r = 0; in gfx_v6_0_ring_test_ib()
1932 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable()
1937 WREG32(mmSCRATCH_UMSK, 0); in gfx_v6_0_cp_gfx_enable()
1967 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1968 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1970 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1976 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1977 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1979 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1985 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1986 for (i = 0; i < fw_size; i++) in gfx_v6_0_cp_gfx_load_microcode()
1988 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1990 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1991 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1992 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1993 WREG32(mmCP_ME_RAM_RADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1994 return 0; in gfx_v6_0_cp_gfx_load_microcode()
2001 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_start()
2010 amdgpu_ring_write(ring, 0x1); in gfx_v6_0_cp_gfx_start()
2011 amdgpu_ring_write(ring, 0x0); in gfx_v6_0_cp_gfx_start()
2014 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2015 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2019 amdgpu_ring_write(ring, 0xc000); in gfx_v6_0_cp_gfx_start()
2020 amdgpu_ring_write(ring, 0xe000); in gfx_v6_0_cp_gfx_start()
2031 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
2040 for (i = 0; i < ext->reg_count; i++) in gfx_v6_0_cp_gfx_start()
2046 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_cp_gfx_start()
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2050 amdgpu_ring_write(ring, 0); in gfx_v6_0_cp_gfx_start()
2053 amdgpu_ring_write(ring, 0x00000316); in gfx_v6_0_cp_gfx_start()
2054 amdgpu_ring_write(ring, 0x0000000e); in gfx_v6_0_cp_gfx_start()
2055 amdgpu_ring_write(ring, 0x00000010); in gfx_v6_0_cp_gfx_start()
2059 return 0; in gfx_v6_0_cp_gfx_start()
2070 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v6_0_cp_gfx_resume()
2071 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in gfx_v6_0_cp_gfx_resume()
2074 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v6_0_cp_gfx_resume()
2076 WREG32(mmCP_DEBUG, 0); in gfx_v6_0_cp_gfx_resume()
2077 WREG32(mmSCRATCH_ADDR, 0); in gfx_v6_0_cp_gfx_resume()
2079 /* ring 0 - compute and gfx */ in gfx_v6_0_cp_gfx_resume()
2081 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_resume()
2092 ring->wptr = 0; in gfx_v6_0_cp_gfx_resume()
2098 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_gfx_resume()
2100 WREG32(mmSCRATCH_UMSK, 0); in gfx_v6_0_cp_gfx_resume()
2113 return 0; in gfx_v6_0_cp_gfx_resume()
2125 if (ring == &adev->gfx.gfx_ring[0]) in gfx_v6_0_ring_get_wptr()
2127 else if (ring == &adev->gfx.compute_ring[0]) in gfx_v6_0_ring_get_wptr()
2147 if (ring == &adev->gfx.compute_ring[0]) { in gfx_v6_0_ring_set_wptr_compute()
2170 ring = &adev->gfx.compute_ring[0]; in gfx_v6_0_cp_compute_resume()
2179 ring->wptr = 0; in gfx_v6_0_cp_compute_resume()
2184 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume()
2199 ring->wptr = 0; in gfx_v6_0_cp_compute_resume()
2203 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume()
2210 for (i = 0; i < 2; i++) { in gfx_v6_0_cp_compute_resume()
2216 return 0; in gfx_v6_0_cp_compute_resume()
2249 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_enable_gui_idle_interrupt()
2276 return 0; in gfx_v6_0_cp_resume()
2289 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v6_0_ring_emit_pipeline_sync()
2290 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v6_0_ring_emit_pipeline_sync()
2292 amdgpu_ring_write(ring, 0xffffffff); in gfx_v6_0_ring_emit_pipeline_sync()
2297 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_pipeline_sync()
2298 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_pipeline_sync()
2299 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_pipeline_sync()
2300 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_pipeline_sync()
2313 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v6_0_ring_emit_vm_flush()
2314 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v6_0_ring_emit_vm_flush()
2316 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2317 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v6_0_ring_emit_vm_flush()
2318 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v6_0_ring_emit_vm_flush()
2319 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v6_0_ring_emit_vm_flush()
2323 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v6_0_ring_emit_vm_flush()
2324 amdgpu_ring_write(ring, 0x0); in gfx_v6_0_ring_emit_vm_flush()
2327 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_vm_flush()
2328 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2329 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_vm_flush()
2330 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_vm_flush()
2341 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
2343 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_wreg()
2392 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); in gfx_v6_0_rlc_init()
2400 return 0; in gfx_v6_0_rlc_init()
2405 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2408 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_enable_lbpw()
2409 WREG32(mmSPI_LB_CU_MASK, 0x00ff); in gfx_v6_0_enable_lbpw()
2417 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_rlc_serdes()
2418 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) in gfx_v6_0_wait_for_rlc_serdes()
2423 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_rlc_serdes()
2424 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) in gfx_v6_0_wait_for_rlc_serdes()
2457 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2476 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2486 if ((tmp & 0xF0000000) == 0xB0000000) in gfx_v6_0_lbpw_supported()
2511 WREG32(mmRLC_RL_BASE, 0); in gfx_v6_0_rlc_resume()
2512 WREG32(mmRLC_RL_SIZE, 0); in gfx_v6_0_rlc_resume()
2513 WREG32(mmRLC_LB_CNTL, 0); in gfx_v6_0_rlc_resume()
2514 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); in gfx_v6_0_rlc_resume()
2515 WREG32(mmRLC_LB_CNTR_INIT, 0); in gfx_v6_0_rlc_resume()
2516 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v6_0_rlc_resume()
2518 WREG32(mmRLC_MC_CNTL, 0); in gfx_v6_0_rlc_resume()
2519 WREG32(mmRLC_UCODE_CNTL, 0); in gfx_v6_0_rlc_resume()
2528 for (i = 0; i < fw_size; i++) { in gfx_v6_0_rlc_resume()
2532 WREG32(mmRLC_UCODE_ADDR, 0); in gfx_v6_0_rlc_resume()
2537 return 0; in gfx_v6_0_rlc_resume()
2549 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); in gfx_v6_0_enable_cgcg()
2553 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_cgcg()
2554 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_cgcg()
2555 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); in gfx_v6_0_enable_cgcg()
2560 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); in gfx_v6_0_enable_cgcg()
2582 u32 data, orig, tmp = 0; in gfx_v6_0_enable_mgcg()
2586 data = 0x96940200; in gfx_v6_0_enable_mgcg()
2598 data &= 0xffffffc0; in gfx_v6_0_enable_mgcg()
2604 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_mgcg()
2605 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_mgcg()
2606 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); in gfx_v6_0_enable_mgcg()
2611 data |= 0x00000003; in gfx_v6_0_enable_mgcg()
2627 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in gfx_v6_0_enable_mgcg()
2628 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in gfx_v6_0_enable_mgcg()
2629 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); in gfx_v6_0_enable_mgcg()
2666 data &= ~0x8000; in gfx_v6_0_enable_cp_pg()
2668 data |= 0x8000; in gfx_v6_0_enable_cp_pg()
2682 u32 bo_offset = 0;
2692 for (me = 0; me < max_me; me++) {
2693 if (me == 0) {
2735 for (i = 0; i < table_size; i ++) {
2748 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); in gfx_v6_0_enable_gfx_cgpg()
2752 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2807 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); in gfx_v6_0_init_gfx_cgpg()
2821 u32 count = 0; in gfx_v6_0_get_csb_size()
2826 return 0; in gfx_v6_0_get_csb_size()
2838 return 0; in gfx_v6_0_get_csb_size()
2854 u32 count = 0, i; in gfx_v6_0_get_csb_buffer()
2863 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_get_csb_buffer()
2866 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v6_0_get_csb_buffer()
2867 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v6_0_get_csb_buffer()
2874 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); in gfx_v6_0_get_csb_buffer()
2875 for (i = 0; i < ext->reg_count; i++) in gfx_v6_0_get_csb_buffer()
2885 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v6_0_get_csb_buffer()
2887 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v6_0_get_csb_buffer()
2890 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_get_csb_buffer()
2891 buffer[count++] = cpu_to_le32(0); in gfx_v6_0_get_csb_buffer()
2955 amdgpu_ring_write(ring, 0x80000000); in gfx_v6_ring_emit_cntxcntl()
2956 amdgpu_ring_write(ring, 0); in gfx_v6_ring_emit_cntxcntl()
2987 /* type 0 wave data */ in gfx_v6_0_read_wave_data()
2988 dst[(*no_fields)++] = 0; in gfx_v6_0_read_wave_data()
3015 adev, simd, wave, 0, in gfx_v6_0_read_wave_sgprs()
3054 return 0; in gfx_v6_0_early_init()
3087 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v6_0_sw_init()
3099 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()
3109 ring->doorbell_index = 0; in gfx_v6_0_sw_init()
3130 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_sw_fini()
3132 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()
3137 return 0; in gfx_v6_0_sw_fini()
3155 adev->gfx.ce_ram_size = 0x8000; in gfx_v6_0_hw_init()
3168 return 0; in gfx_v6_0_hw_fini()
3196 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v6_0_wait_for_idle()
3198 return 0; in gfx_v6_0_wait_for_idle()
3232 if (ring == 0) { in gfx_v6_0_set_compute_eop_interrupt_state()
3245 if (ring == 0) { in gfx_v6_0_set_compute_eop_interrupt_state()
3287 return 0; in gfx_v6_0_set_priv_reg_fault_state()
3312 return 0; in gfx_v6_0_set_priv_inst_fault_state()
3325 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); in gfx_v6_0_set_eop_interrupt_state()
3333 return 0; in gfx_v6_0_set_eop_interrupt_state()
3341 case 0: in gfx_v6_0_eop_irq()
3342 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v6_0_eop_irq()
3351 return 0; in gfx_v6_0_eop_irq()
3360 case 0: in gfx_v6_0_fault()
3361 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_fault()
3379 return 0; in gfx_v6_0_priv_reg_irq()
3388 return 0; in gfx_v6_0_priv_inst_irq()
3410 return 0; in gfx_v6_0_set_clockgating_state()
3435 return 0; in gfx_v6_0_set_powergating_state()
3445 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v6_0_emit_mem_sync()
3446 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v6_0_emit_mem_sync()
3447 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v6_0_emit_mem_sync()
3467 .align_mask = 0xff,
3468 .nop = 0x80000000,
3495 .align_mask = 0xff,
3496 .nop = 0x80000000,
3522 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_set_ring_funcs()
3524 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
3557 int i, j, k, counter, active_cu_number = 0; in gfx_v6_0_get_cu_info()
3558 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v6_0_get_cu_info()
3568 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v6_0_get_cu_info()
3573 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_get_cu_info()
3574 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_get_cu_info()
3576 ao_bitmap = 0; in gfx_v6_0_get_cu_info()
3577 counter = 0; in gfx_v6_0_get_cu_info()
3578 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v6_0_get_cu_info()
3583 cu_info->bitmap[0][i][j] = bitmap; in gfx_v6_0_get_cu_info()
3585 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()
3600 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v6_0_get_cu_info()
3611 .minor = 0,
3612 .rev = 0,