Lines Matching full:control
128 * add to control->i2c_address, and then tell I2C layer to read
173 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
178 if (!control) in __get_eeprom_i2c_addr()
191 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
200 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
204 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
206 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
209 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
214 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
216 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
221 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
223 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
229 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) in __write_table_header() argument
265 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_header()
269 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()
274 control->i2c_address + in __write_table_header()
275 control->ras_header_offset, in __write_table_header()
318 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __write_table_ras_info() argument
320 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_ras_info()
330 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); in __write_table_ras_info()
335 control->i2c_address + in __write_table_ras_info()
336 control->ras_info_offset, in __write_table_ras_info()
355 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_hdr_byte_sum() argument
362 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()
363 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()
371 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_ras_info_byte_sum() argument
377 sz = sizeof(control->tbl_rai); in __calc_ras_info_byte_sum()
378 pp = (u8 *) &control->tbl_rai; in __calc_ras_info_byte_sum()
387 struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_correct_header_tag() argument
390 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()
402 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
405 res = __write_table_header(control); in amdgpu_ras_eeprom_correct_header_tag()
406 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
411 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_set_eeprom_table_version() argument
413 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_set_eeprom_table_version()
414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_set_eeprom_table_version()
431 * @control: pointer to control structure
436 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_reset_table() argument
438 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_reset_table()
439 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()
440 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in amdgpu_ras_eeprom_reset_table()
445 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
448 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_reset_table()
467 csum = __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
469 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
472 res = __write_table_header(control); in amdgpu_ras_eeprom_reset_table()
474 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_reset_table()
476 control->ras_num_recs = 0; in amdgpu_ras_eeprom_reset_table()
477 control->ras_num_bad_pages = 0; in amdgpu_ras_eeprom_reset_table()
478 control->ras_fri = 0; in amdgpu_ras_eeprom_reset_table()
480 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); in amdgpu_ras_eeprom_reset_table()
482 control->bad_channel_bitmap = 0; in amdgpu_ras_eeprom_reset_table()
483 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); in amdgpu_ras_eeprom_reset_table()
486 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_reset_table()
488 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
494 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, in __encode_table_record_to_buf() argument
522 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, in __decode_table_record_from_buf() argument
585 * @control: pointer to control structure
590 * The caller must hold the table mutex in @control.
593 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_write() argument
596 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_write()
604 control->i2c_address + in __amdgpu_ras_eeprom_write()
605 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_write()
625 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append_table() argument
629 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); in amdgpu_ras_eeprom_append_table()
630 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append_table()
643 __encode_table_record_to_buf(control, &record[i], pp); in amdgpu_ras_eeprom_append_table()
646 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_append_table()
647 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_append_table()
648 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_append_table()
657 * Let N = control->ras_max_num_record_count, then we have, in amdgpu_ras_eeprom_append_table()
680 a = control->ras_fri + control->ras_num_recs; in amdgpu_ras_eeprom_append_table()
682 if (b < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
683 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
684 } else if (a < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
687 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
688 g1 = b % control->ras_max_record_count + 1; in amdgpu_ras_eeprom_append_table()
689 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
692 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
697 if (g1 > control->ras_fri) in amdgpu_ras_eeprom_append_table()
698 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
700 a %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
701 b %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
705 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
708 if (b >= control->ras_fri) in amdgpu_ras_eeprom_append_table()
709 control->ras_fri = (b + 1) % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
717 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
719 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
722 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
727 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
730 control->ras_num_recs = 1 + (control->ras_max_record_count + b in amdgpu_ras_eeprom_append_table()
731 - control->ras_fri) in amdgpu_ras_eeprom_append_table()
732 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
736 control->ras_num_pa_recs += num; in amdgpu_ras_eeprom_append_table()
738 control->ras_num_mca_recs += num; in amdgpu_ras_eeprom_append_table()
740 control->ras_num_bad_pages = control->ras_num_pa_recs + in amdgpu_ras_eeprom_append_table()
741 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_append_table()
748 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_header() argument
750 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_header()
759 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
762 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
763 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()
764 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()
765 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; in amdgpu_ras_eeprom_update_header()
766 control->tbl_rai.health_percent = 0; in amdgpu_ras_eeprom_update_header()
777 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
778 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
780 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
782 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
783 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
784 control->tbl_hdr.checksum = 0; in amdgpu_ras_eeprom_update_header()
786 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
787 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); in amdgpu_ras_eeprom_update_header()
790 control->tbl_hdr.tbl_size); in amdgpu_ras_eeprom_update_header()
797 control->i2c_address + in amdgpu_ras_eeprom_update_header()
798 control->ras_record_offset, in amdgpu_ras_eeprom_update_header()
817 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && in amdgpu_ras_eeprom_update_header()
818 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
819 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
820 control->ras_num_bad_pages) * 100) / in amdgpu_ras_eeprom_update_header()
829 csum += __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_update_header()
830 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
831 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_update_header()
834 control->tbl_hdr.checksum = csum; in amdgpu_ras_eeprom_update_header()
835 res = __write_table_header(control); in amdgpu_ras_eeprom_update_header()
836 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) in amdgpu_ras_eeprom_update_header()
837 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_update_header()
845 * @control: pointer to control structure
851 * can be appended is between 1 and control->ras_max_record_count,
856 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append() argument
860 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append()
870 } else if (num > control->ras_max_record_count) { in amdgpu_ras_eeprom_append()
872 num, control->ras_max_record_count); in amdgpu_ras_eeprom_append()
883 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
885 res = amdgpu_ras_eeprom_append_table(control, record, num); in amdgpu_ras_eeprom_append()
887 res = amdgpu_ras_eeprom_update_header(control); in amdgpu_ras_eeprom_append()
889 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_append()
891 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
902 * @control: pointer to control structure
907 * The caller must hold the table mutex in @control.
910 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_read() argument
913 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_read()
921 control->i2c_address + in __amdgpu_ras_eeprom_read()
922 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_read()
943 * @control: pointer to control structure
952 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read() argument
956 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read()
968 } else if (num > control->ras_num_recs) { in amdgpu_ras_eeprom_read()
970 num, control->ras_num_recs); in amdgpu_ras_eeprom_read()
998 g0 = control->ras_fri + num - 1; in amdgpu_ras_eeprom_read()
999 g1 = g0 % control->ras_max_record_count; in amdgpu_ras_eeprom_read()
1000 if (g0 < control->ras_max_record_count) { in amdgpu_ras_eeprom_read()
1004 g0 = control->ras_max_record_count - control->ras_fri; in amdgpu_ras_eeprom_read()
1008 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1009 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); in amdgpu_ras_eeprom_read()
1013 res = __amdgpu_ras_eeprom_read(control, in amdgpu_ras_eeprom_read()
1026 __decode_table_record_from_buf(control, &record[i], pp); in amdgpu_ras_eeprom_read()
1029 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_read()
1030 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_read()
1031 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_read()
1037 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1042 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_max_record_count() argument
1045 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_max_record_count()
1047 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_max_record_count()
1059 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read() local
1066 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1070 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); in amdgpu_ras_debugfs_eeprom_size_read()
1107 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_table_size() argument
1110 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; in amdgpu_ras_debugfs_table_size()
1113 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_set_ret_size() argument
1115 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size()
1120 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_set_ret_size()
1128 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read() local
1133 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1155 control->tbl_hdr.header, in amdgpu_ras_debugfs_table_read()
1156 control->tbl_hdr.version, in amdgpu_ras_debugfs_table_read()
1157 control->tbl_hdr.first_rec_offset, in amdgpu_ras_debugfs_table_read()
1158 control->tbl_hdr.tbl_size, in amdgpu_ras_debugfs_table_read()
1159 control->tbl_hdr.checksum); in amdgpu_ras_debugfs_table_read()
1185 data_len = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_table_read()
1201 for ( ; size > 0 && s < control->ras_num_recs; s++) { in amdgpu_ras_debugfs_table_read()
1202 u32 ai = RAS_RI_TO_AI(control, s); in amdgpu_ras_debugfs_table_read()
1205 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); in amdgpu_ras_debugfs_table_read()
1208 __decode_table_record_from_buf(control, &record, dare); in amdgpu_ras_debugfs_table_read()
1211 RAS_INDEX_TO_OFFSET(control, ai), in amdgpu_ras_debugfs_table_read()
1233 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1243 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read() local
1250 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1278 * @control: pointer to control structure
1286 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) in __verify_ras_table_checksum() argument
1288 struct amdgpu_device *adev = to_amdgpu_device(control); in __verify_ras_table_checksum()
1292 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in __verify_ras_table_checksum()
1295 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1298 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1307 control->i2c_address + in __verify_ras_table_checksum()
1308 control->ras_header_offset, in __verify_ras_table_checksum()
1327 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __read_table_ras_info() argument
1329 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in __read_table_ras_info()
1330 struct amdgpu_device *adev = to_amdgpu_device(control); in __read_table_ras_info()
1345 control->i2c_address + control->ras_info_offset, in __read_table_ras_info()
1360 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_init() argument
1362 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_init()
1364 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_init()
1377 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_init()
1380 control->ras_header_offset = RAS_HDR_START; in amdgpu_ras_eeprom_init()
1381 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; in amdgpu_ras_eeprom_init()
1382 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_init()
1386 control->i2c_address + control->ras_header_offset, in amdgpu_ras_eeprom_init()
1396 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); in amdgpu_ras_eeprom_init()
1397 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_init()
1398 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_init()
1400 control->ras_num_recs = RAS_NUM_RECS(hdr); in amdgpu_ras_eeprom_init()
1401 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_init()
1402 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_init()
1404 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); in amdgpu_ras_eeprom_init()
1406 control->ras_num_mca_recs = 0; in amdgpu_ras_eeprom_init()
1407 control->ras_num_pa_recs = 0; in amdgpu_ras_eeprom_init()
1411 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_check() argument
1413 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_check()
1414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_check()
1425 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_check()
1428 control->ras_num_bad_pages = control->ras_num_pa_recs + in amdgpu_ras_eeprom_check()
1429 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_check()
1433 control->ras_num_bad_pages); in amdgpu_ras_eeprom_check()
1436 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1441 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1449 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_check()
1451 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1456 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1461 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1468 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { in amdgpu_ras_eeprom_check()
1471 * ras->bad_page_cnt_threshold - control->num_recs > 0, in amdgpu_ras_eeprom_check()
1478 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1480 res = amdgpu_ras_eeprom_correct_header_tag(control, in amdgpu_ras_eeprom_check()
1485 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_check()
1500 res = amdgpu_ras_eeprom_reset_table(control); in amdgpu_ras_eeprom_check()