clk/rockchip/rst-rk3562.c

14 /* 0xff100000 + 0x0A00 */
15 #define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0xff110000 + 0x0A00 */
17 #define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
18 /* 0xff118000 + 0x0A00 */
19 #define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit)
20 /* 0xff120000 + 0x0A00 */
21 #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
22 /* 0xff128000 + 0x0A00 */
23 #define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit)
24 /* 0xff130000 + 0x0A00 */
25 #define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
30 	RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0),
35 	RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0),
51 	RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0),
69 	RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0),
96 	RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0),
145 	RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0),
161 	RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0),
173 	RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0),
183 	RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0),
192 	RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0),
198 	RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0),
207 	RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0),
219 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0),
220 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1),
221 	RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2),
222 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3),
223 	RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4),
224 	RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5),
225 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6),
226 	RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7),
227 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8),
228 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9),
229 	RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10),
230 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11),
231 	RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12),
234 	RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0),
242 	RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0),
243 	RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2),
244 	RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3),
245 	RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4),
246 	RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7),
247 	RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10),
250 	RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0),
256 	RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0),
263 	RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4),
264 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5),
265 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6),
266 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
267 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9),
268 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10),
271 	RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0),
278 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1),
279 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4),
280 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5),
281 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6),
282 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7),
283 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8),
284 	RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9),
293 	RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0),
309 	RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0),
320 	RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0),
325 	RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0),
331 	RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0),
351 	RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0),
355 	RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0),
363 	RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0),
369 	RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0),
383 	RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0),
392 	RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0),
403 	RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0),
416 	RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0),
427 				      reg_base + RK3562_SOFTRST_CON(0),  in rk3562_rst_init()