Lines Matching +full:8 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
59 {3, 8},
72 {2, 8},
98 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
128 BUS_MSTOP(5, BIT(9))),
151 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
153 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
173 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
175 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
177 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
179 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
181 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
183 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
185 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
187 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
189 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
191 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
192 BUS_MSTOP(1, BIT(8))),
194 BUS_MSTOP(8, BIT(2))),
196 BUS_MSTOP(8, BIT(2))),
198 BUS_MSTOP(8, BIT(2))),
200 BUS_MSTOP(8, BIT(2))),
202 BUS_MSTOP(8, BIT(3))),
203 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
204 BUS_MSTOP(8, BIT(3))),
205 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
206 BUS_MSTOP(8, BIT(3))),
208 BUS_MSTOP(8, BIT(3))),
210 BUS_MSTOP(8, BIT(4))),
212 BUS_MSTOP(8, BIT(4))),
214 BUS_MSTOP(8, BIT(4))),
216 BUS_MSTOP(8, BIT(4))),
218 BUS_MSTOP(9, BIT(4))),
220 BUS_MSTOP(9, BIT(4))),
222 BUS_MSTOP(9, BIT(4))),
224 BUS_MSTOP(9, BIT(5))),
226 BUS_MSTOP(9, BIT(5))),
228 BUS_MSTOP(9, BIT(5))),
229 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
230 BUS_MSTOP(9, BIT(6))),
231 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
232 BUS_MSTOP(9, BIT(6))),
234 BUS_MSTOP(9, BIT(6))),
236 BUS_MSTOP(9, BIT(7))),
238 BUS_MSTOP(9, BIT(7))),
240 BUS_MSTOP(9, BIT(7))),
251 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
252 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
263 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
264 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
265 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
266 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
267 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
268 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
269 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
270 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
271 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
272 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
273 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
276 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
277 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
281 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
282 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */