Lines Matching +full:4 +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
58 {2, 4},
65 {1, 4},
71 {1, 4},
74 {4, 64},
92 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
103 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
106 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
135 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
141 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
143 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
145 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
147 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
149 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
151 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
153 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
155 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
157 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
159 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
161 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
163 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
165 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
173 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
175 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
177 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
179 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
181 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
183 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
184 BUS_MSTOP(1, BIT(4))),
185 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
187 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
188 BUS_MSTOP(1, BIT(6))),
189 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
191 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
195 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
199 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
210 BUS_MSTOP(8, BIT(4))),
212 BUS_MSTOP(8, BIT(4))),
214 BUS_MSTOP(8, BIT(4))),
216 BUS_MSTOP(8, BIT(4))),
217 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
218 BUS_MSTOP(9, BIT(4))),
219 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
220 BUS_MSTOP(9, BIT(4))),
221 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
222 BUS_MSTOP(9, BIT(4))),
223 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
225 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
227 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
229 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
230 BUS_MSTOP(9, BIT(6))),
231 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
232 BUS_MSTOP(9, BIT(6))),
233 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
234 BUS_MSTOP(9, BIT(6))),
235 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
237 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
239 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
247 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
248 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
249 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
250 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
253 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
254 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
255 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
259 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
260 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
261 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
262 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
265 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
266 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
267 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
268 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
269 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
270 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
271 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
272 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
273 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
274 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
275 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
276 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
277 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
279 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
288 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
289 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */