clk/renesas/r9a09g057-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
128 						BUS_MSTOP(5, BIT(9))),
130 						BUS_MSTOP(3, BIT(2))),
132 						BUS_MSTOP(3, BIT(3))),
134 						BUS_MSTOP(10, BIT(11))),
136 						BUS_MSTOP(10, BIT(12))),
140 						BUS_MSTOP(3, BIT(5))),
142 						BUS_MSTOP(5, BIT(10))),
144 						BUS_MSTOP(5, BIT(11))),
146 						BUS_MSTOP(2, BIT(13))),
148 						BUS_MSTOP(2, BIT(14))),
150 						BUS_MSTOP(11, BIT(13))),
152 						BUS_MSTOP(11, BIT(14))),
154 						BUS_MSTOP(11, BIT(15))),
155 	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,
156 						BUS_MSTOP(12, BIT(0))),
158 						BUS_MSTOP(3, BIT(10))),
160 						BUS_MSTOP(3, BIT(10))),
162 						BUS_MSTOP(1, BIT(0))),
164 						BUS_MSTOP(1, BIT(0))),
166 						BUS_MSTOP(5, BIT(12))),
168 						BUS_MSTOP(5, BIT(12))),
170 						BUS_MSTOP(5, BIT(13))),
172 						BUS_MSTOP(5, BIT(13))),
174 						BUS_MSTOP(3, BIT(14))),
176 						BUS_MSTOP(3, BIT(13))),
178 						BUS_MSTOP(1, BIT(1))),
180 						BUS_MSTOP(1, BIT(2))),
182 						BUS_MSTOP(1, BIT(3))),
184 						BUS_MSTOP(1, BIT(4))),
186 						BUS_MSTOP(1, BIT(5))),
188 						BUS_MSTOP(1, BIT(6))),
189 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,
190 						BUS_MSTOP(1, BIT(7))),
192 						BUS_MSTOP(1, BIT(8))),
193 	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
194 						BUS_MSTOP(8, BIT(2))),
195 	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,
196 						BUS_MSTOP(8, BIT(2))),
197 	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,
198 						BUS_MSTOP(8, BIT(2))),
199 	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
200 						BUS_MSTOP(8, BIT(2))),
201 	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,
202 						BUS_MSTOP(8, BIT(3))),
203 	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
204 						BUS_MSTOP(8, BIT(3))),
205 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
206 						BUS_MSTOP(8, BIT(3))),
207 	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
208 						BUS_MSTOP(8, BIT(3))),
209 	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,
210 						BUS_MSTOP(8, BIT(4))),
211 	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,
212 						BUS_MSTOP(8, BIT(4))),
213 	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,
214 						BUS_MSTOP(8, BIT(4))),
215 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
216 						BUS_MSTOP(8, BIT(4))),
218 						BUS_MSTOP(9, BIT(4))),
220 						BUS_MSTOP(9, BIT(4))),
222 						BUS_MSTOP(9, BIT(4))),
224 						BUS_MSTOP(9, BIT(5))),
226 						BUS_MSTOP(9, BIT(5))),
228 						BUS_MSTOP(9, BIT(5))),
230 						BUS_MSTOP(9, BIT(6))),
232 						BUS_MSTOP(9, BIT(6))),
233 	DEF_MOD("cru_2_pclk",			CLK_PLLDTY_DIV16, 13, 10, 6, 26,
234 						BUS_MSTOP(9, BIT(6))),
236 						BUS_MSTOP(9, BIT(7))),
238 						BUS_MSTOP(9, BIT(7))),
240 						BUS_MSTOP(9, BIT(7))),
252 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
267 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
268 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
274 	DEF_RST(10, 0, 4, 17),		/* RIIC_8_MRST */
275 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
276 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
277 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
283 	DEF_RST(12, 10, 5, 27),		/* CRU_1_S_RESETN */